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Searched refs:GPR64 (Results 1 – 13 of 13) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrAtomics.td48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
50 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
65 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
78 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
80 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
93 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
95 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
134 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
136 (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>;
[all …]
HDAArch64InstrInfo.td304 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
305 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
311 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
312 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
316 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
317 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
321 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
322 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
326 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
327 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
[all …]
HDAArch64RegisterInfo.td129 // GPR64/GPR64sp for use by the coalescer.
144 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
145 let AltOrders = [(rotl GPR64, 8)];
191 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
192 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
193 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
194 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
195 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
196 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
197 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
[all …]
HDAArch64InstrFormats.td567 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
589 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
878 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
887 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
931 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
946 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
980 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1064 def X : BaseCmpBranch<GPR64, op, asm, node> {
1136 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1144 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips64InstrInfo.td82 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
83 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
84 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
85 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
86 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
87 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
88 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
89 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
253 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
255 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
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HDMipsCondMov.td208 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
210 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
212 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
214 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
216 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
218 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
220 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
222 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
224 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
229 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
[all …]
HDMipsRegisterInfo.td319 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
554 def GPR64Opnd : RegisterOperand<GPR64> {
HDMipsInstrInfo.td1405 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1406 GPR64:$dst),
1407 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
HDMipsMSAInstrInfo.td3810 GPR64), [HasMSA, IsGP64bit]>;
3831 GPR64), [HasMSA, IsGP64bit]>;
3879 GPR64), [HasMSA, IsGP64bit]>;
3916 GPR64),
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZRegisterInfo.td63 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
70 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
80 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
85 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
86 !cast<GPR64>("R"#I#"D")>;
HDSystemZFrameLowering.cpp112 unsigned GPR64, bool IsImplicit) { in addSavedGPR() argument
115 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR()
116 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR()
118 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
120 MBB.addLiveIn(GPR64); in addSavedGPR()
/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/
HDRegisterContextFreeBSD_powerpc.cpp57 } GPR64; typedef
253 return sizeof(GPR64); in GetGPRSize()
HDRegisterInfos_powerpc.h145 #define GPR GPR64
161 #define GPR GPR64