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Searched refs:GPR32RegClass (Results 1 – 17 of 17) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsFastISel.cpp249 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
280 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
294 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
331 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
337 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
339 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
350 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
372 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
592 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
598 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
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HDMipsOptionRecord.h46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
64 const MCRegisterClass *GPR32RegClass; variable
HDMipsMachineFunction.cpp86 : &Mips::GPR32RegClass; in getGlobalBaseReg()
107 : &Mips::GPR32RegClass; in createEhDataRegsFI()
HDMipsSERegisterInfo.cpp60 return &Mips::GPR32RegClass; in intRegClass()
181 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
HDMipsSEFrameLowering.cpp294 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
350 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
389 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
557 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
657 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
671 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
HDMipsSEInstrInfo.cpp86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
190 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
231 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
391 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
HDMipsSubtarget.cpp134 &Mips::GPR64RegClass : &Mips::GPR32RegClass); in getCriticalPathRCs()
HDMips16InstrInfo.cpp68 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
70 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
HDMipsRegisterInfo.cpp55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
HDMipsAsmPrinter.cpp257 unsigned CPURegSize = Mips::GPR32RegClass.getSize(); in printSavedRegsBitmask()
276 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
HDMipsSEISelDAGToDAG.cpp143 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
HDMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
2913 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
2978 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3206 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
HDMipsISelLowering.cpp3405 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3408 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3432 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64FastISel.cpp345 : &AArch64::GPR32RegClass; in materializeInt()
378 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
1254 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1297 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1335 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1373 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1659 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1765 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1770 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1775 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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HDAArch64InstrInfo.cpp493 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
494 RC = &AArch64::GPR32RegClass; in insertSelect()
1128 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
1773 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
1778 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
1835 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
1933 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2688 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
2703 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
2725 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
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HDAArch64ISelLowering.cpp2140 RC = &AArch64::GPR32RegClass; in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsOptionRecord.cpp79 if (GPR32RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()