| /NextBSD/contrib/one-true-awk/ |
| HD | awk.h | 123 #define FSIN 9 macro
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| HD | lex.c | 79 { "sin", FSIN, BLTIN },
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| HD | run.c | 1504 case FSIN: in bltin()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 506 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| HD | BasicTTIImpl.h | 623 ISD = ISD::FSIN; in getIntrinsicInstrCost()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 150 case ISD::FSIN: return "fsin"; in getOperationName()
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| HD | LegalizeFloatTypes.cpp | 96 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
916 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
1757 case ISD::FSIN: in PromoteFloatResult()
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| HD | LegalizeDAG.cpp | 2342 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2343 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3362 case ISD::FSIN: in ExpandNode()
3365 bool isSIN = Node->getOpcode() == ISD::FSIN; in ExpandNode()
4322 case ISD::FSIN: in PromoteNode()
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| HD | LegalizeVectorOps.cpp | 303 case ISD::FSIN: in LegalizeOp()
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| HD | LegalizeVectorTypes.cpp | 92 case ISD::FSIN: in ScalarizeVectorResult()
640 case ISD::FSIN: in SplitVectorResult()
2009 case ISD::FSIN: in WidenVectorResult()
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| HD | SelectionDAGBuilder.cpp | 4567 case Intrinsic::sin: Opcode = ISD::FSIN; break; in visitIntrinsicCall()
5587 if (visitUnaryFloatCall(I, ISD::FSIN)) in visitCall()
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| HD | DAGCombiner.cpp | 592 case ISD::FSIN: in isNegatibleForFree()
664 case ISD::FSIN: in GetNegatedExpression()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIISelLowering.cpp | 76 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
798 case ISD::FSIN: in LowerOperation()
1404 case ISD::FSIN: in LowerTrig()
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| HD | R600ISelLowering.cpp | 65 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
590 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
959 case ISD::FSIN: in LowerTrig()
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| HD | AMDGPUISelLowering.cpp | 396 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 1517 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1522 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1527 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 174 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
276 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
277 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
306 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
350 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
382 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
537 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
640 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1431 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1490 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 463 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
481 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
498 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
623 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
875 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
876 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 418 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsISelLowering.cpp | 358 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
359 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 163 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
169 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
454 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
672 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
718 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 537 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
540 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
567 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
579 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
595 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
596 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
637 setOperationAction(ISD::FSIN , MVT::f80, Expand); in X86TargetLowering()
686 setOperationAction(ISD::FSIN, VT, Expand); in X86TargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelLowering.cpp | 371 setOperationAction(ISD::FSIN, VT, Expand); in SystemZTargetLowering()
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