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Searched refs:FP_EXTEND (Results 1 – 25 of 25) sorted by relevance

/NextBSD/contrib/gcc/config/rs6000/
HDdarwin-ldouble.c393 FP_EXTEND(Q,D,4,2,X,A); in fmsub()
394 FP_EXTEND(Q,D,4,2,Y,B); in fmsub()
395 FP_EXTEND(Q,D,4,2,Z,C); in fmsub()
397 FP_EXTEND(Q,D,2,1,X,A); in fmsub()
398 FP_EXTEND(Q,D,2,1,Y,B); in fmsub()
399 FP_EXTEND(Q,D,2,1,Z,C); in fmsub()
/NextBSD/contrib/gcc/config/soft-fp/
HDextendsfdf2.c46 FP_EXTEND(D,S,2,1,R,A); in __extendsfdf2()
48 FP_EXTEND(D,S,1,1,R,A); in __extendsfdf2()
HDextenddftf2.c46 FP_EXTEND(Q,D,4,2,R,A); in __extenddftf2()
48 FP_EXTEND(Q,D,2,1,R,A); in __extenddftf2()
HDextendsftf2.c46 FP_EXTEND(Q,S,4,1,R,A); in __extendsftf2()
48 FP_EXTEND(Q,S,2,1,R,A); in __extendsftf2()
HDop-common.h1151 #define FP_EXTEND(dfs,sfs,dwc,swc,D,S) \ macro
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
63 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
HDARMISelLowering.cpp536 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in ARMTargetLowering()
644 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in ARMTargetLowering()
6624 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h468 FP_EXTEND, enumerator
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp590 case ISD::FP_EXTEND: in isNegatibleForFree()
663 case ISD::FP_EXTEND: in GetNegatedExpression()
1386 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
7474 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7478 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7480 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7486 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7490 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7492 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7528 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
[all …]
HDLegalizeFloatTypes.cpp88 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
416 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
603 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL)); in SoftenFloatRes_LOAD()
691 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
911 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1148 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1624 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1675 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
HDLegalizeDAG.cpp438 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : in ExpandUnalignedLoad()
2486 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
3041 case ISD::FP_EXTEND: in ExpandNode()
3500 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4223 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4254 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4267 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4289 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4290 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4297 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
HDLegalizeVectorOps.cpp319 case ISD::FP_EXTEND: in LegalizeOp()
407 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
HDSelectionDAGDumper.cpp241 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
HDLegalizeVectorTypes.cpp87 case ISD::FP_EXTEND: in ScalarizeVectorResult()
634 case ISD::FP_EXTEND: in SplitVectorResult()
1392 case ISD::FP_EXTEND: in SplitVectorOperand()
1980 case ISD::FP_EXTEND: in WidenVectorResult()
2842 case ISD::FP_EXTEND: in WidenVectorOperand()
HDSelectionDAG.cpp254 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
2899 case ISD::FP_EXTEND: { in getNode()
2945 case ISD::FP_EXTEND: in getNode()
3007 case ISD::FP_EXTEND: in getNode()
HDSelectionDAGBuilder.cpp219 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); in getCopyFromParts()
388 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); in getCopyToParts()
2371 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); in visitFPExt()
4637 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, in visitIntrinsicCall()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp506 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
507 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
576 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
HDX86ISelDAGToDAG.cpp516 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
537 if (N->getOpcode() == ISD::FP_EXTEND) in PreprocessISelDAG()
HDX86ISelLowering.cpp932 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in X86TargetLowering()
1349 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal); in X86TargetLowering()
2060 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
2134 } else if (Copy->getOpcode() != ISD::FP_EXTEND) in isUsedByReturnOnly()
12008 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in LowerUINT_TO_FP_i32()
12710 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); in LowerFCOPYSIGN()
18568 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
18721 case ISD::FP_EXTEND: { in ReplaceNodeResults()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp668 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
6005 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6008 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6017 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6025 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6038 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6041 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6048 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6054 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6060 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
325 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
331 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
391 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
546 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1598 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); in LowerVectorFP_TO_INT()
1616 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
1988 case ISD::FP_EXTEND: in LowerOperation()
2721 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3397 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2); in LowerFCOPYSIGN()
[all …]
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1604 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1632 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
2835 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp1582 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td431 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1571 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); in HexagonTargetLowering()