Searched refs:FGETSIGN (Results 1 – 9 of 9) sorted by relevance
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 254 FGETSIGN, enumerator
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 195 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
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| HD | TargetLowering.cpp | 1062 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits()
1063 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1068 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
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| HD | SelectionDAG.cpp | 2325 case ISD::FGETSIGN: in computeKnownBits()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 813 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 415 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 643 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
696 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
18573 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 619 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
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