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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 19 of 19) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
593 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
821 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
823 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
1353 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
1498 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
1500 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
1924 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
2085 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
2088 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
[all …]
HDSelectionDAGDumper.cpp211 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
HDLegalizeIntegerTypes.cpp87 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
882 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
3169 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
HDSelectionDAG.cpp3600 case ISD::EXTRACT_SUBVECTOR: { in getNode()
6965 Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in SplitVector()
6967 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
HDSelectionDAGBuilder.cpp311 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
561 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
2623 ISD::EXTRACT_SUBVECTOR, dl, VT, Src, in visitShuffleVector()
HDDAGCombiner.cpp1402 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
12091 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1, in visitBUILD_VECTOR()
12095 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1, in visitBUILD_VECTOR()
12306 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
12388 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, in visitEXTRACT_SUBVECTOR()
HDLegalizeDAG.cpp3169 case ISD::EXTRACT_SUBVECTOR: in ExpandNode()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h292 EXTRACT_SUBVECTOR, enumerator
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp655 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom); in addTypeForNEON()
2002 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
4628 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4634 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4639 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4642 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4982 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
4986 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
5210 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in LowerVECTOR_SHUFFLE()
7426 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && in performBitcastCombine()
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HDAArch64ISelDAGToDAG.cpp414 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) in checkHighLaneIndex()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
630 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
HDSIISelLowering.cpp188 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
4432 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended, in lowerCTPOP16BitElements()
4435 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, in lowerCTPOP16BitElements()
4474 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended, in lowerCTPOP32BitElements()
4477 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2, in lowerCTPOP32BitElements()
5528 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5534 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5540 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5543 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
6318 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1227 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1468 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
3957 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4211 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in ExtractSubVector()
5373 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
5420 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
9318 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V, in splitAndLowerVectorShuffle()
9320 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V, in splitAndLowerVectorShuffle()
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1500 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1526 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2296 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG); in LowerOperation()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td525 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
530 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXVector.td869 def extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
HDNVPTXISelLowering.cpp1816 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp658 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); in PPCTargetLowering()
708 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); in PPCTargetLowering()
750 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); in PPCTargetLowering()