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Searched refs:Def (Results 1 – 25 of 102) sorted by relevance

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/NextBSD/contrib/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp193 const MachineInstr *Def; member in __anonc2f739380111::ValueTracker
251 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
254 Def = MRI.getVRegDef(Reg); in ValueTracker()
270 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
272 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
273 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
274 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
954 TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg()); in optimizeUncoalescableCopy() local
955 TargetInstrInfo::RegSubRegPair Src = Def; in optimizeUncoalescableCopy()
958 RewritePairs.push_back(std::make_pair(Def, Src)); in optimizeUncoalescableCopy()
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HDMachineCopyPropagation.cpp113 static bool isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, in isNopCopy() argument
116 if (Def == SrcSrc) in isNopCopy()
118 if (TRI->isSubRegister(SrcSrc, Def)) { in isNopCopy()
120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy()
143 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
146 if (TargetRegisterInfo::isVirtualRegister(Def) || in CopyPropagateBlock()
154 if (!MRI->isReserved(Def) && in CopyPropagateBlock()
156 isNopCopy(CopyMI, Def, Src, TRI)) { in CopyPropagateBlock()
176 I->clearRegisterKills(Def, TRI); in CopyPropagateBlock()
206 SourceNoLongerAvailable(Def, SrcMap, AvailCopyMap); in CopyPropagateBlock()
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HDLiveVariables.cpp199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef() local
200 if (!Def) in FindLastPartialDef()
202 unsigned Dist = DistanceMap[Def]; in FindLastPartialDef()
205 LastDef = Def; in FindLastPartialDef()
292 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastRefOrPartRef() local
293 if (Def && Def != LastDef) { in FindLastRefOrPartRef()
296 unsigned Dist = DistanceMap[Def]; in FindLastRefOrPartRef()
341 MachineInstr *Def = PhysRegDef[SubReg]; in HandlePhysRegKill() local
342 if (Def && Def != LastDef) { in HandlePhysRegKill()
345 unsigned Dist = DistanceMap[Def]; in HandlePhysRegKill()
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HDLiveInterval.cpp62 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator) { in createDeadDef() argument
63 assert(!Def.isDead() && "Cannot define a value at the dead slot"); in createDeadDef()
65 iterator I = impl().find(Def); in createDeadDef()
67 VNInfo *VNI = LR->getNextValue(Def, VNInfoAllocator); in createDeadDef()
68 impl().insertAtEnd(Segment(Def, Def.getDeadSlot(), VNI)); in createDeadDef()
73 if (SlotIndex::isSameInstr(Def, S->start)) { in createDeadDef()
81 Def = std::min(Def, S->start); in createDeadDef()
82 if (Def != S->start) in createDeadDef()
83 S->start = S->valno->def = Def; in createDeadDef()
86 assert(SlotIndex::isEarlierInstr(Def, S->start) && "Already live at def"); in createDeadDef()
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HDExecutionDepsFix.cpp126 int Def; member
373 LiveRegs[rx].Def = -(1 << 20); in enterBasicBlock()
384 LiveRegs[rx].Def = -1; in enterBasicBlock()
403 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def); in enterBasicBlock()
443 LiveRegs[i].Def -= CurInstr; in leaveBasicBlock()
478 unsigned Clearance = CurInstr - LiveRegs[rx].Def; in shouldBreakDependence()
535 LiveRegs[rx].Def = CurInstr; in processDefs()
664 if (LR.Def < i->Def) { in visitSoftInstr()
HDSplitKit.cpp382 SlotIndex Def = OldVNI->def; in defValue() local
383 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), OldVNI)); in defValue()
389 SlotIndex Def = VNI->def; in defValue() local
390 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI)); in defValue()
409 SlotIndex Def = VNI->def; in forceRecompute() local
411 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI)); in forceRecompute()
422 SlotIndex Def; in defFromParent() local
432 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late); in defFromParent()
438 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late) in defFromParent()
444 return defValue(RegIdx, ParentVNI, Def); in defFromParent()
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HDMachineLICM.cpp159 unsigned Def; member
162 : MI(mi), Def(def), FI(fi) {} in CandidateInfo()
172 void HoistPostRA(MachineInstr *MI, unsigned Def);
430 unsigned Def = 0; in ProcessMI() local
480 if (Def) in ProcessMI()
483 Def = Reg; in ProcessMI()
501 if (Def && !RuledOut) { in ProcessMI()
505 Candidates.push_back(CandidateInfo(MI, Def, FI)); in ProcessMI()
581 unsigned Def = Candidates[i].Def; in HoistRegionPostRA() local
582 if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) { in HoistRegionPostRA()
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64CollectLOH.cpp488 static bool canDefBePartOfLOH(const MachineInstr *Def) { in canDefBePartOfLOH() argument
489 unsigned Opc = Def->getOpcode(); in canDefBePartOfLOH()
498 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
509 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
563 const MachineInstr *Def = DefsIt.first; in reachedUsesToDefs() local
567 if ((ADRPMode && Def->getOpcode() != AArch64::ADRP) || in reachedUsesToDefs()
568 (!ADRPMode && !canDefBePartOfLOH(Def)) || in reachedUsesToDefs()
689 const MachineInstr *Def = *UseToDefs.find(Instr)->second.begin(); in isCandidate() local
690 if (Def->getOpcode() != AArch64::ADRP) { in isCandidate()
697 if (!MDT->dominates(Def, Instr)) in isCandidate()
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HDAArch64AdvSIMDScalarPass.cpp206 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
208 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
209 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
219 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
221 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
222 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
299 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
301 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
302 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
307 Def->eraseFromParent(); in transformInstruction()
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/NextBSD/contrib/llvm/lib/IR/
HDDominators.cpp77 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
80 const BasicBlock *DefBB = Def->getParent(); in dominates()
91 if (Def == User) in dominates()
98 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
99 return dominates(Def, UseBB); in dominates()
106 for (; &*I != Def && &*I != User; ++I) in dominates()
109 return &*I == Def; in dominates()
114 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
116 const BasicBlock *DefBB = Def->getParent(); in dominates()
129 const InvokeInst *II = dyn_cast<InvokeInst>(Def); in dominates()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIFixSGPRLiveRanges.cpp121 unsigned Def = MO.getReg(); in runOnMachineFunction() local
122 if (TargetRegisterInfo::isVirtualRegister(Def)) { in runOnMachineFunction()
123 if (TRI->isSGPRClass(MRI.getRegClass(Def))) in runOnMachineFunction()
125 std::make_pair(Def, &LIS->getInterval(Def))); in runOnMachineFunction()
126 } else if (TRI->isSGPRClass(TRI->getPhysRegClass(Def))) { in runOnMachineFunction()
128 std::make_pair(Def, &LIS->getRegUnit(Def))); in runOnMachineFunction()
HDSIShrinkInstructions.cpp166 MachineInstr *Def = MRI.getUniqueVRegDef(Reg); in foldImmediates() local
167 if (Def && Def->isMoveImmediate()) { in foldImmediates()
168 MachineOperand &MovSrc = Def->getOperand(1); in foldImmediates()
177 Def->eraseFromParent(); in foldImmediates()
HDR600EmitClauseMarkers.cpp183 MachineBasicBlock::iterator Def, in canClauseLocalKillFitInClause() argument
187 MOI = Def->operands_begin(), in canClauseLocalKillFitInClause()
188 MOE = Def->operands_end(); MOI != MOE; ++MOI) { in canClauseLocalKillFitInClause()
196 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) { in canClauseLocalKillFitInClause()
216 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1) in canClauseLocalKillFitInClause()
HDSIFixSGPRCopies.cpp169 MachineInstr *Def = MRI.getVRegDef(Reg); in inferRegClassFromDef() local
170 if (Def->getOpcode() != AMDGPU::COPY) { in inferRegClassFromDef()
174 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), in inferRegClassFromDef()
175 Def->getOperand(1).getSubReg()); in inferRegClassFromDef()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenSchedule.h61 CodeGenSchedRW(unsigned Idx, Record *Def) in CodeGenSchedRW()
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
63 Name = Def->getName(); in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
67 IsVariadic = Def->getValueAsBit("Variadic"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
324 CodeGenSchedRW &getSchedRW(Record *Def) { in getSchedRW() argument
325 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
326 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
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HDDAGISelMatcherGen.cpp623 Record *Def = DI->getDef(); in EmitResultLeafAsOperand() local
624 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
626 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
632 if (Def->getName() == "zero_reg") { in EmitResultLeafAsOperand()
640 if (Def->isSubClassOf("RegisterOperand")) in EmitResultLeafAsOperand()
641 Def = Def->getValueAsDef("RegClass"); in EmitResultLeafAsOperand()
642 if (Def->isSubClassOf("RegisterClass")) { in EmitResultLeafAsOperand()
643 std::string Value = getQualifiedName(Def) + "RegClassID"; in EmitResultLeafAsOperand()
650 if (Def->isSubClassOf("SubRegIndex")) { in EmitResultLeafAsOperand()
651 std::string Value = getQualifiedName(Def); in EmitResultLeafAsOperand()
/NextBSD/contrib/llvm/tools/clang/lib/Lex/
HDMacroInfo.cpp198 for (DefInfo Def = getDefinition(); Def; Def = Def.getPreviousDefinition()) { in findDirectiveAtLoc() local
199 if (Def.getLocation().isInvalid() || // For macros defined on the command line. in findDirectiveAtLoc()
200 SM.isBeforeInTranslationUnit(Def.getLocation(), L)) in findDirectiveAtLoc()
201 return (!Def.isUndefined() || in findDirectiveAtLoc()
202 SM.isBeforeInTranslationUnit(L, Def.getUndefLocation())) in findDirectiveAtLoc()
203 ? Def : DefInfo(); in findDirectiveAtLoc()
HDPreprocessingRecord.cpp322 MacroDefinitionRecord *Def) { in RegisterMacroDefinition() argument
323 MacroDefinitions[Macro] = Def; in RegisterMacroDefinition()
379 else if (MacroDefinitionRecord *Def = findMacroDefinition(MI)) in addMacroExpansion() local
380 addPreprocessedEntity(new (*this) MacroExpansion(Def, Range)); in addMacroExpansion()
423 MacroDefinitionRecord *Def = in MacroDefined() local
425 addPreprocessedEntity(Def); in MacroDefined()
426 MacroDefinitions[MI] = Def; in MacroDefined()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDA15SDOptimizer.cpp209 MachineInstr *Def = Op->getParent(); in eraseInstrWithNoUses() local
213 if (DeadInstr.find(Def) != DeadInstr.end()) in eraseInstrWithNoUses()
220 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) { in eraseInstrWithNoUses()
221 MachineOperand &MODef = Def->getOperand(j); in eraseInstrWithNoUses()
233 if (&*II == Def) in eraseInstrWithNoUses()
244 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); in eraseInstrWithNoUses()
245 DeadInstr.insert(Def); in eraseInstrWithNoUses()
314 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() local
315 if (!Def) in optimizeSDPattern()
317 if (Def->isImplicitDef()) in optimizeSDPattern()
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/NextBSD/contrib/llvm/tools/clang/utils/TableGen/
HDNeonEmitter.cpp1972 for (auto *Def : Defs) { in genBuiltinsDef() local
1973 if (Def->hasBody()) in genBuiltinsDef()
1977 if (Def->hasSplat()) in genBuiltinsDef()
1980 std::string S = "BUILTIN(__builtin_neon_" + Def->getMangledName() + ", \""; in genBuiltinsDef()
1982 S += Def->getBuiltinTypeStr(); in genBuiltinsDef()
2010 for (auto *Def : Defs) { in genOverloadTypeCheckCode() local
2013 if (Def->hasBody()) in genOverloadTypeCheckCode()
2017 if (Def->hasSplat()) in genOverloadTypeCheckCode()
2021 if (Def->protoHasScalar()) in genOverloadTypeCheckCode()
2025 Type Ty = Def->getReturnType(); in genOverloadTypeCheckCode()
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZElimCompare.cpp40 : Def(false), Use(false), IndirectDef(false), IndirectUse(false) {} in Reference()
43 Def |= Other.Def; in operator |=()
50 explicit operator bool() const { return Def || Use; } in operator bool()
54 bool Def; member
151 Ref.Def = true; in getRegReferences()
347 (!CCRefs.Def && adjustCCMasksForInstr(MI, Compare, CCUsers))) { in optimizeCompareZero()
353 if (SrcRefs.Def) in optimizeCompareZero()
356 if (CCRefs.Use && CCRefs.Def) in optimizeCompareZero()
450 if (CCRefs.Def) { in processBlock()
/NextBSD/contrib/llvm/lib/TableGen/
HDSetTheory.cpp236 void expand(SetTheory &ST, Record *Def, RecSet &Elts) override { in expand()
237 ST.evaluate(Def->getValueInit(FieldName), Elts, Def->getLoc()); in expand()
274 if (DefInit *Def = dyn_cast<DefInit>(Expr)) { in evaluate() local
275 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
277 Elts.insert(Def->getDef()); in evaluate()
/NextBSD/tools/tools/shlib-compat/
HDshlib-compat.py245 class Def(object): class
299 if isinstance(v, Def):
317 class AnonymousDef(Def):
319 Def.__init__(self, id, None, **kwargs)
345 class BaseTypeDef(Def):
364 class TypeAliasDef(Def):
374 class EnumerationTypeDef(Def):
407 class FunctionDef(Def):
416 class FunctionTypeDef(Def):
425 class ParameterDef(Def):
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/NextBSD/contrib/llvm/tools/clang/lib/Serialization/
HDASTCommon.cpp105 if (const TagDecl *Def = cast<TagDecl>(DC)->getDefinition()) in getDefinitiveDeclContext() local
106 return Def; in getDefinitiveDeclContext()
133 if (const ObjCProtocolDecl *Def in getDefinitiveDeclContext() local
135 return Def; in getDefinitiveDeclContext()
/NextBSD/contrib/llvm/include/llvm/IR/
HDDominators.h102 bool dominates(const Instruction *Def, const Use &U) const;
103 bool dominates(const Instruction *Def, const Instruction *User) const;
104 bool dominates(const Instruction *Def, const BasicBlock *BB) const;

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