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Searched refs:DL (Results 1 – 25 of 431) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZSelectionDAGInfo.cpp26 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem() argument
42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
43 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
44 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
46 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
50 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy() argument
59 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
67 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore() argument
74 return DAG.getStore(Chain, DL, in memsetStore()
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HDSystemZISelLowering.cpp87 auto &DL = *TM.getDataLayout(); in SystemZTargetLowering() local
88 MVT PtrVT = getPointerTy(DL); in SystemZTargetLowering()
459 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
512 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
805 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, in convertLocVTToValVT() argument
811 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
814 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
818 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
820 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value, in convertLocVTToValVT()
827 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64, in convertLocVTToValVT()
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/NextBSD/contrib/llvm/lib/IR/
HDMangler.cpp34 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
47 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
49 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
59 const DataLayout &DL, in getNameWithPrefixImpl() argument
61 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
62 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
66 const DataLayout &DL) { in getNameWithPrefix() argument
67 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
71 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
73 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefix()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp615 SDLoc DL(Op); in LowerOperation() local
621 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
622 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
623 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
624 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
626 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
639 SDLoc DL(Op); in LowerOperation() local
659 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, in LowerOperation()
660 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32)); in LowerOperation()
663 DL, MVT::f32, SDValue(interp, 0)); in LowerOperation()
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HDAMDGPUISelLowering.cpp593 SDLoc DL, SelectionDAG &DAG) const { in LowerReturn() argument
594 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
701 SDLoc DL(InitPtr); in LowerConstantInitializer() local
707 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr, in LowerConstantInitializer()
715 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr, in LowerConstantInitializer()
727 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT); in LowerConstantInitializer()
728 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
734 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
751 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT); in LowerConstantInitializer()
752 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
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HDSILowerControlFlow.cpp141 DebugLoc DL = From.getDebugLoc(); in Skip() local
142 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
150 DebugLoc DL = MI.getDebugLoc(); in SkipIfDead() local
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
166 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
178 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
183 DebugLoc DL = MI.getDebugLoc(); in If() local
187 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
190 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
201 DebugLoc DL = MI.getDebugLoc(); in Else() local
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HDAMDGPUISelDAGToDAG.cpp128 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
358 SDLoc DL(N); in Select() local
359 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
373 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
384 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, in Select()
393 DL, EltVT); in Select()
397 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); in Select()
411 SDLoc DL(N); in Select() local
413 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32); in Select()
414 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); in Select()
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HDSIISelLowering.cpp264 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
438 const DataLayout &DL = DAG.getDataLayout(); in LowerParameter() local
447 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerParameter()
456 unsigned Align = DL.getABITypeAlignment(Ty); in LowerParameter()
492 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
616 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain, in LowerFormalArguments()
627 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
644 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
652 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
666 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
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/NextBSD/contrib/llvm/include/llvm/Analysis/
HDInstructionSimplify.h52 const DataLayout &DL,
61 const DataLayout &DL,
70 const DataLayout &DL,
79 const DataLayout &DL,
88 const DataLayout &DL,
96 Value *SimplifyMulInst(Value *LHS, Value *RHS, const DataLayout &DL,
104 Value *SimplifySDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
112 Value *SimplifyUDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
121 const DataLayout &DL,
129 Value *SimplifySRemInst(Value *LHS, Value *RHS, const DataLayout &DL,
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HDValueTracking.h43 const DataLayout &DL, unsigned Depth = 0,
52 bool haveNoCommonBitsSet(Value *LHS, Value *RHS, const DataLayout &DL,
60 const DataLayout &DL, unsigned Depth = 0,
70 bool isKnownToBeAPowerOfTwo(Value *V, const DataLayout &DL,
80 bool isKnownNonZero(Value *V, const DataLayout &DL, unsigned Depth = 0,
94 bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
107 unsigned ComputeNumSignBits(Value *Op, const DataLayout &DL,
152 const DataLayout &DL);
155 const DataLayout &DL) { in GetPointerBaseWithConstantOffset() argument
157 DL); in GetPointerBaseWithConstantOffset()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp483 SDLoc DL(N); in performDivRemCombine() local
485 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
492 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
501 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
561 SDLoc DL(Op); in createFPCmp() local
567 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
568 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
573 SDValue False, SDLoc DL) { in createCMovFP() argument
578 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
612 const SDLoc DL(N); in performSELECTCombine() local
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HDMipsSEISelLowering.cpp428 SDLoc DL(ADDENode); in selectMADD() local
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
500 SDLoc DL(SUBENode); in selectMSUB() local
503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMSUB()
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, in selectMSUB()
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); in selectMSUB()
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HDMipsLongBranch.cpp80 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
216 DebugLoc DL, MachineBasicBlock *MBBOpnd) { in replaceBranch() argument
222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
255 DebugLoc DL = I.Br->getDebugLoc(); in expandToLongBranch() local
296 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
317 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
320 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
321 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
328 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
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/NextBSD/contrib/llvm/lib/Analysis/
HDValueTracking.cpp74 static unsigned getBitWidth(Type *Ty, const DataLayout &DL) { in getBitWidth() argument
78 return DL.getPointerTypeSizeInBits(Ty); in getBitWidth()
130 const DataLayout &DL, unsigned Depth,
134 const DataLayout &DL, unsigned Depth, in computeKnownBits() argument
137 ::computeKnownBits(V, KnownZero, KnownOne, DL, Depth, in computeKnownBits()
141 bool llvm::haveNoCommonBitsSet(Value *LHS, Value *RHS, const DataLayout &DL, in haveNoCommonBitsSet() argument
151 computeKnownBits(LHS, LHSKnownZero, LHSKnownOne, DL, 0, AC, CxtI, DT); in haveNoCommonBitsSet()
152 computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, DL, 0, AC, CxtI, DT); in haveNoCommonBitsSet()
157 const DataLayout &DL, unsigned Depth,
161 const DataLayout &DL, unsigned Depth, in ComputeSignBit() argument
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HDConstantFolding.cpp53 static Constant *FoldBitCast(Constant *C, Type *DestTy, const DataLayout &DL) { in FoldBitCast() argument
86 unsigned BitShift = DL.getTypeAllocSizeInBits(SrcEltTy); in FoldBitCast()
90 if (DL.isLittleEndian()) in FoldBitCast()
108 return FoldBitCast(ConstantVector::get(Ops), DestTy, DL); in FoldBitCast()
140 C = FoldBitCast(C, DestIVTy, DL); in FoldBitCast()
164 bool isLittleEndian = DL.isLittleEndian(); in FoldBitCast()
200 unsigned DstBitSize = DL.getTypeSizeInBits(DstEltTy); in FoldBitCast()
237 APInt &Offset, const DataLayout &DL) { in IsConstantOffsetFromGlobal() argument
240 unsigned BitWidth = DL.getPointerTypeSizeInBits(GV->getType()); in IsConstantOffsetFromGlobal()
253 return IsConstantOffsetFromGlobal(CE->getOperand(0), GV, Offset, DL); in IsConstantOffsetFromGlobal()
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/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
227 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
230 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
234 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
239 DiagnosticInfoUnsupported Err(DL, *MF.getFunction(), in LowerFormalArguments()
247 DL, *MF.getFunction(), in LowerFormalArguments()
288 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(), in LowerCall()
298 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(), in LowerCall()
305 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL); in LowerCall()
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86FrameLowering.cpp249 DebugLoc DL = MBB.findDebugLoc(MBBI); in emitSPUpdate() local
264 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
269 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
288 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
298 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue); in emitSPUpdate()
307 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, in BuildStackAdjustment() argument
333 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
342 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
406 MachineBasicBlock::iterator MBBI, DebugLoc DL, in BuildCFI() argument
410 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineInstrBuilder.h237 DebugLoc DL, in BuildMI() argument
239 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); in BuildMI()
246 DebugLoc DL, in BuildMI() argument
249 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) in BuildMI()
259 DebugLoc DL, in BuildMI() argument
263 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
270 DebugLoc DL, in BuildMI() argument
274 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
281 DebugLoc DL, in BuildMI() argument
286 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
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HDSelectionDAG.h429 SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false,
431 SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false,
433 SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
435 SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget = false);
436 SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,
438 return getConstant(Val, DL, VT, true, isOpaque);
440 SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT,
442 return getConstant(Val, DL, VT, true, isOpaque);
444 SDValue getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
446 return getConstant(Val, DL, VT, true, isOpaque);
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/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDSROA.cpp219 AllocaSlices(const DataLayout &DL, AllocaInst &AI);
640 SliceBuilder(const DataLayout &DL, AllocaInst &AI, AllocaSlices &AS) in SliceBuilder() argument
641 : PtrUseVisitor<SliceBuilder>(DL), in SliceBuilder()
642 AllocSize(DL.getTypeAllocSize(AI.getAllocatedType())), AS(AS) {} in SliceBuilder()
704 const DataLayout &DL = GEPI.getModule()->getDataLayout(); in visitGetElementPtrInst() local
715 const StructLayout *SL = DL.getStructLayout(STy); in visitGetElementPtrInst()
723 DL.getTypeAllocSize(GTI.getIndexedType())); in visitGetElementPtrInst()
754 const DataLayout &DL = LI.getModule()->getDataLayout(); in visitLoadInst() local
755 uint64_t Size = DL.getTypeStoreSize(LI.getType()); in visitLoadInst()
766 const DataLayout &DL = SI.getModule()->getDataLayout(); in visitStoreInst() local
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HDScalarReplAggregates.cpp162 const DataLayout &DL);
164 const DataLayout &DL);
267 const DataLayout &DL; member in __anon38f7cdc50211::ConvertToScalarInfo
310 explicit ConvertToScalarInfo(unsigned Size, const DataLayout &DL, in ConvertToScalarInfo() argument
312 : AllocaSize(Size), DL(DL), ScalarLoadThreshold(SLT), IsNotTrivial(false), in ConvertToScalarInfo()
373 !HadNonMemTransferAccess && !DL.fitsInLegalInteger(BitWidth)) in TryConvert()
530 uint64_t GEPOffset = DL.getIndexedOffset(PtrTy, in CanConvertToScalar()
625 uint64_t GEPOffset = DL.getIndexedOffset(GEP->getPointerOperandType(), in ConvertUsesToScalar()
702 AllocaInst *OrigAI = cast<AllocaInst>(GetUnderlyingObject(Ptr, DL, 0)); in ConvertUsesToScalar()
704 if (GetUnderlyingObject(MTI->getSource(), DL, 0) != OrigAI) { in ConvertUsesToScalar()
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/NextBSD/contrib/llvm/lib/Transforms/ObjCARC/
HDProvenanceAnalysis.cpp35 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedSelect() local
40 return related(A->getTrueValue(), SB->getTrueValue(), DL) || in relatedSelect()
41 related(A->getFalseValue(), SB->getFalseValue(), DL); in relatedSelect()
44 return related(A->getTrueValue(), B, DL) || in relatedSelect()
45 related(A->getFalseValue(), B, DL); in relatedSelect()
50 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedPHI() local
58 PNB->getIncomingValueForBlock(A->getIncomingBlock(i)), DL)) in relatedPHI()
66 if (UniqueSrc.insert(PV1).second && related(PV1, B, DL)) in relatedPHI()
108 const DataLayout &DL) { in relatedCheck() argument
110 A = GetUnderlyingObjCPtr(A, DL); in relatedCheck()
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/NextBSD/contrib/llvm/lib/Target/ARM/
HDA15SDOptimizer.cpp71 DebugLoc DL,
77 DebugLoc DL,
83 DebugLoc DL,
88 DebugLoc DL,
93 DebugLoc DL, unsigned DReg, unsigned Lane,
98 DebugLoc DL);
432 DebugLoc DL, in createDupLane() argument
438 DL, in createDupLane()
451 DebugLoc DL, in createExtractSubreg() argument
457 DL, in createExtractSubreg()
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorOps.cpp721 SDLoc DL(Op); in ExpandSELECT() local
749 Mask = DAG.getSelect(DL, BitTy, Mask, in ExpandSELECT()
750 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, in ExpandSELECT()
752 DAG.getConstant(0, DL, BitTy)); in ExpandSELECT()
756 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); in ExpandSELECT()
761 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
762 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
765 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy); in ExpandSELECT()
766 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); in ExpandSELECT()
768 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); in ExpandSELECT()
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstrInfo.cpp233 DebugLoc DL) const { in InsertBranch()
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in InsertBranch()
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in InsertBranch()
281 MachineBasicBlock::iterator I, DebugLoc DL, in copyPhysReg() argument
295 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
298 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
302 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
313 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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12345678910>>...18