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Searched refs:Cond (Results 1 – 25 of 178) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsInstrInfo.cpp73 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
80 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
83 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
89 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in AnalyzeBranch()
99 DebugLoc DL, ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
100 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
104 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
105 if (Cond[i].isReg()) in BuildCondBr()
106 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
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HDMipsInstrInfo.h56 SmallVectorImpl<MachineOperand> &Cond,
62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
66 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
70 SmallVectorImpl<MachineOperand> &Cond,
139 SmallVectorImpl<MachineOperand> &Cond) const;
142 ArrayRef<MachineOperand> Cond) const;
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreInstrInfo.cpp196 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
224 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
225 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
246 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
247 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
279 ArrayRef<MachineOperand> Cond, in InsertBranch() argument
283 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
287 if (Cond.empty()) { in InsertBranch()
292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
293 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
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HDXCoreInstrInfo.h55 SmallVectorImpl<MachineOperand> &Cond,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 SmallVectorImpl<MachineOperand> &Cond) const override;
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfo.cpp162 ArrayRef<MachineOperand> Cond, DebugLoc DL) const { in InsertBranch() argument
172 if (!Cond.empty() && Cond[0].isImm()) in InsertBranch()
173 BccOpc = Cond[0].getImm(); in InsertBranch()
176 if (Cond.empty()) { in InsertBranch()
182 SmallVector<MachineOperand, 4> Cond; in InsertBranch() local
185 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) { in InsertBranch()
189 ReverseBranchCondition(Cond); in InsertBranch()
191 return InsertBranch(MBB, TBB, nullptr, Cond, DL); in InsertBranch()
195 } else if (isEndLoopN(Cond[0].getImm())) { in InsertBranch()
196 int EndLoopOp = Cond[0].getImm(); in InsertBranch()
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HDHexagonExpandCondsets.cpp157 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
159 unsigned DstSR, const MachineOperand &PredOp, bool Cond);
165 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
169 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
171 bool Cond, MachineBasicBlock::iterator First,
173 bool predicate(MachineInstr *TfrI, bool Cond);
650 bool Cond) { in getCondTfrOpcode() argument
667 return Cond ? A2_tfrt : A2_tfrf; in getCondTfrOpcode()
669 return Cond ? A2_tfrpt : A2_tfrpf; in getCondTfrOpcode()
674 return Cond ? C2_cmoveit : C2_cmoveif; in getCondTfrOpcode()
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HDHexagonInstrInfo.h66 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
131 ArrayRef<MachineOperand> Cond) const override;
155 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
224 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
226 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430InstrInfo.cpp130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
157 Cond[0].setImm(CC); in ReverseBranchCondition()
175 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
210 Cond.clear(); in AnalyzeBranch()
234 if (Cond.empty()) { in AnalyzeBranch()
237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
243 assert(Cond.size() == 1); in AnalyzeBranch()
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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HDMSP430BranchSelector.cpp152 SmallVector<MachineOperand, 1> Cond; in runOnMachineFunction() local
153 Cond.push_back(I->getOperand(1)); in runOnMachineFunction()
156 TII->ReverseBranchCondition(Cond); in runOnMachineFunction()
158 .addImm(4).addOperand(Cond[0]); in runOnMachineFunction()
HDMSP430InstrInfo.h76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
80 SmallVectorImpl<MachineOperand> &Cond,
85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp1246 ISD::CondCode Cond, bool foldBooleans, in SimplifySetCC() argument
1251 switch (Cond) { in SimplifySetCC()
1267 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); in SimplifySetCC()
1284 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1286 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1289 Cond = ISD::SETNE; in SimplifySetCC()
1293 Cond = ISD::SETEQ; in SimplifySetCC()
1297 Zero, Cond); in SimplifySetCC()
1314 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1318 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
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/NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
HDSimpleConstraintManager.cpp69 DefinedSVal Cond, in assume() argument
72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assume()
84 return assume(state, Cond.castAs<NonLoc>(), Assumption); in assume()
115 NonLoc Cond, in assumeAux() argument
120 if (!canReasonAbout(Cond)) { in assumeAux()
122 SymbolRef sym = Cond.getAsSymExpr(); in assumeAux()
126 switch (Cond.getSubKind()) { in assumeAux()
131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
182 bool b = Cond.castAs<nonloc::ConcreteInt>().getValue() != 0; in assumeAux()
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HDSimpleConstraintManager.h36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
88 NonLoc Cond,
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.cpp388 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
415 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
416 Cond.push_back(LastInst->getOperand(1)); in AnalyzeBranch()
423 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in AnalyzeBranch()
424 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
431 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in AnalyzeBranch()
432 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
441 Cond.push_back(MachineOperand::CreateImm(1)); in AnalyzeBranch()
442 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
452 Cond.push_back(MachineOperand::CreateImm(0)); in AnalyzeBranch()
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HDPPCInstrInfo.h144 SmallVectorImpl<MachineOperand> &Cond,
148 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
152 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
155 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
176 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.cpp170 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { in AnalyzeBranch() argument
187 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
205 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
251 ArrayRef<MachineOperand> Cond, DebugLoc DL) const { in InsertBranch() argument
254 assert((Cond.size() == 1 || Cond.size() == 0) && in InsertBranch()
259 if (Cond.empty()) // Unconditional branch in InsertBranch()
262 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in InsertBranch()
268 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in InsertBranch()
/NextBSD/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
HDConstraintManager.h68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
76 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
86 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
91 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.cpp62 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
69 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
76 Cond.push_back(MachineOperand::CreateImm(-1)); in parseCondBranch()
77 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in parseCondBranch()
78 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
85 Cond.push_back(MachineOperand::CreateImm(-1)); in parseCondBranch()
86 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in parseCondBranch()
87 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
88 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
96 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
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HDAArch64InstrInfo.h139 SmallVectorImpl<MachineOperand> &Cond,
143 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
146 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
147 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
150 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
187 ArrayRef<MachineOperand> Cond) const;
/NextBSD/contrib/llvm/lib/CodeGen/
HDMachineBasicBlock.cpp387 SmallVector<MachineOperand, 4> Cond; in updateTerminator() local
389 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); in updateTerminator()
392 if (Cond.empty()) { in updateTerminator()
417 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
425 if (TII->ReverseBranchCondition(Cond)) in updateTerminator()
428 TII->InsertBranch(*this, FBB, nullptr, Cond, dl); in updateTerminator()
431 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
455 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
461 if (TII->ReverseBranchCondition(Cond)) { in updateTerminator()
463 Cond.clear(); in updateTerminator()
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HDIfConversion.cpp201 bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
212 SmallVectorImpl<MachineOperand> &Cond,
215 SmallVectorImpl<MachineOperand> &Cond,
750 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end()); in FeasibilityAnalysis() local
752 if (TII->ReverseBranchCondition(Cond)) in FeasibilityAnalysis()
756 !TII->SubsumesPredicate(Cond, RevPred)) in FeasibilityAnalysis()
1004 SmallVector<MachineOperand, 4> Cond; in RemoveExtraEdges() local
1005 if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond)) in RemoveExtraEdges()
1006 BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); in RemoveExtraEdges()
1078 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end()); in IfConvertSimple() local
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/NextBSD/contrib/llvm/tools/clang/lib/Sema/
HDScopeInfo.cpp165 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) { in markSafeWeakUse() local
166 markSafeWeakUse(Cond->getTrueExpr()); in markSafeWeakUse()
167 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
171 if (const BinaryConditionalOperator *Cond = in markSafeWeakUse() local
173 markSafeWeakUse(Cond->getCommon()); in markSafeWeakUse()
174 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFInstrInfo.cpp81 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
111 Cond.clear(); in AnalyzeBranch()
136 ArrayRef<MachineOperand> Cond, in InsertBranch() argument
141 if (Cond.empty()) { in InsertBranch()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIAnnotateControlFlow.cpp86 Value *handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L);
210 Value *SIAnnotateControlFlow::handleLoopCondition(Value *Cond, PHINode *Broken, in handleLoopCondition() argument
219 if ((Phi = dyn_cast<PHINode>(Cond)) && L->contains(Phi)) { in handleLoopCondition()
263 } else if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
271 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
287 Value *Cond = Term->getCondition(); in handleLoop() local
289 Value *Arg = handleLoopCondition(Cond, Broken, L); in handleLoop()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstrInfo.cpp130 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
162 Cond.clear(); in AnalyzeBranch()
183 if (Cond.empty()) { in AnalyzeBranch()
219 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
232 ArrayRef<MachineOperand> Cond, in InsertBranch() argument
235 assert((Cond.size() == 1 || Cond.size() == 0) && in InsertBranch()
238 if (Cond.empty()) { in InsertBranch()
245 unsigned CC = Cond[0].getImm(); in InsertBranch()

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