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Searched refs:CSR_READ_1 (Results 1 – 25 of 47) sorted by relevance

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/NextBSD/sys/dev/ex/
HDif_ex.c327 temp_reg = CSR_READ_1(sc, EEPROM_REG); in ex_init_locked()
339 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr); in ex_init_locked()
340 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem); in ex_init_locked()
341 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ ); in ex_init_locked()
350 (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | in ex_init_locked()
372 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT); in ex_init_locked()
600 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT); in ex_stop()
631 (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) { in ex_intr()
767 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG); in ex_rx_intr()
885 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode); in ex_setmulti()
[all …]
HDif_ex_isa.c330 if (((count1 = CSR_READ_1(sc, ID_REG)) & Id_Mask) != Id_Sig) in ex_look_for_card()
332 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
333 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
334 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
HDif_exvar.h95 #define CSR_READ_1(sc, off) (bus_read_1((sc)->ioport, off)) macro
/NextBSD/sys/dev/ste/
HDif_ste.c197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
213 val = CSR_READ_1(sc, STE_PHYCTL); in ste_mii_bitbang_read()
418 rxcfg = CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
453 CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
814 CSR_READ_1(sc, STE_STAT_RX_BCAST); in ste_stats_clear()
815 CSR_READ_1(sc, STE_STAT_RX_MCAST); in ste_stats_clear()
816 CSR_READ_1(sc, STE_STAT_RX_LOST); in ste_stats_clear()
821 CSR_READ_1(sc, STE_STAT_TX_BCAST); in ste_stats_clear()
822 CSR_READ_1(sc, STE_STAT_TX_MCAST); in ste_stats_clear()
[all …]
/NextBSD/sys/dev/sn/
HDif_sn.c452 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) in snstart_locked()
466 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; in snstart_locked()
478 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); in snstart_locked()
548 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); in snstart_locked()
661 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); in snresume()
746 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); in snresume()
809 mask = CSR_READ_1(sc, INTR_MASK_REG_B); in snintr_locked()
816 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); in snintr_locked()
991 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); in snintr_locked()
1085 *data = CSR_READ_1(sc, DATA_REG_B); in snread()
HDif_snvar.h58 #define CSR_READ_1(sc, off) (bus_read_1((sc)->port_res, off)) macro
/NextBSD/sys/dev/re/
HDif_re.c350 CSR_READ_1(sc, RL_EECMD) | x)
354 CSR_READ_1(sc, RL_EECMD) & ~x)
404 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in re_eeprom_getword()
449 rval = CSR_READ_1(sc, RL_GMEDIASTAT); in re_gmii_readreg()
547 rval = CSR_READ_1(sc, RL_MEDIASTAT); in re_miibus_readreg()
730 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in re_reset()
1313 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1350 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1545 cfg = CSR_READ_1(sc, sc->rl_cfg1); in re_attach()
1548 cfg = CSR_READ_1(sc, sc->rl_cfg5); in re_attach()
[all …]
/NextBSD/sys/dev/vge/
HDif_vge.c260 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword()
301 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom()
314 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_stop()
334 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_start()
351 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) in vge_miipoll_start()
379 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) in vge_miibus_readreg()
415 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) in vge_miibus_writereg()
484 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) in vge_cam_set()
522 cfg = CSR_READ_1(sc, VGE_RXCFG); in vge_setvlan()
550 rxcfg = CSR_READ_1(sc, VGE_RXCTL); in vge_rxfilter()
[all …]
HDif_vgevar.h228 #define CSR_READ_1(sc, reg) \ macro
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/NextBSD/sys/dev/vr/
HDif_vr.c255 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) in vr_miibus_readreg()
279 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) in vr_miibus_writereg()
324 cr0 = CSR_READ_1(sc, VR_CR0); in vr_miibus_statchg()
325 cr1 = CSR_READ_1(sc, VR_CR1); in vr_miibus_statchg()
349 fc = CSR_READ_1(sc, VR_FLOWCR1); in vr_miibus_statchg()
362 fc = CSR_READ_1(sc, VR_MISC_CR0); in vr_miibus_statchg()
421 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) in vr_cam_data()
450 rxfilt = CSR_READ_1(sc, VR_RXCFG); in vr_set_filter()
533 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) in vr_reset()
718 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) in vr_attach()
[all …]
HDif_vrreg.h756 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/NextBSD/sys/dev/rl/
HDif_rl.c267 CSR_READ_1(sc, RL_EECMD) | x)
271 CSR_READ_1(sc, RL_EECMD) & ~x)
325 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in rl_eeprom_getword()
367 val = CSR_READ_1(sc, RL_MII); in rl_mii_bitbang_read()
424 return (CSR_READ_1(sc, RL_MEDIASTAT)); in rl_miibus_readreg()
572 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in rl_reset()
777 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in rl_attach()
1143 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { in rl_rxeof()
1929 if ((CSR_READ_1(sc, RL_COMMAND) & in rl_stop()
2068 v = CSR_READ_1(sc, sc->rl_cfg1); in rl_setwol()
[all …]
HDif_rlreg.h959 #define CSR_READ_1(sc, reg) \ macro
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/NextBSD/sys/dev/ipw/
HDif_ipwreg.h325 #define CSR_READ_1(sc, reg) \ macro
352 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
/NextBSD/sys/dev/vx/
HDif_vxvar.h71 #define CSR_READ_1(sc, reg) \ macro
/NextBSD/sys/dev/fxp/
HDif_fxp.c334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait()
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); in fxp_scb_wait()
338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); in fxp_scb_wait()
340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), in fxp_scb_wait()
341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), in fxp_scb_wait()
342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); in fxp_scb_wait()
918 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_attach()
1116 CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_resume()
1693 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_poll()
1732 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { in fxp_intr()
[all …]
HDif_fxpvar.h244 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
/NextBSD/sys/dev/bm/
HDif_bmreg.h166 #define CSR_READ_1(sc, reg) \ macro
/NextBSD/sys/dev/tx/
HDif_txvar.h140 #define CSR_READ_1(sc, reg) \ macro
/NextBSD/sys/dev/xl/
HDif_xl.c453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_miibus_statchg()
616 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90x()
664 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90xB()
817 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode()
2090 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc()
2313 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update()
2329 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update()
2828 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init_locked()
2954 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
2963 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
/NextBSD/sys/dev/ep/
HDif_epvar.h86 #define CSR_READ_1(sc, off) (bus_space_read_1((sc)->bst, (sc)->bsh, off)) macro
HDif_ep.c426 CSR_READ_1(sc, EP_W1_TX_STATUS); in epinit_locked()
669 while ((status = CSR_READ_1(sc, EP_W1_TX_STATUS)) & in ep_intr_locked()
807 CSR_READ_1(sc, EP_W1_RX_PIO_RD_1); in epread()
/NextBSD/sys/dev/msk/
HDif_msk.c1207 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; in mskc_setup_rambuffer()
1669 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); in msk_attach()
1783 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); in mskc_attach()
1784 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; in mskc_attach()
1821 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); in mskc_attach()
1824 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in mskc_attach()
1826 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in mskc_attach()
3422 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_intr_gmac()
3850 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_init_locked()
4105 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
[all …]
/NextBSD/sys/dev/stge/
HDif_stge.c257 val = CSR_READ_1(sc, STGE_PhyCtrl); in stge_mii_bitbang_read()
296 error = CSR_READ_1(sc, STGE_PhyCtrl); in stge_miibus_readreg()
594 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
990 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_setwol()
1036 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_resume()
1959 v = CSR_READ_1(sc, STGE_PhySet); in stge_reset()
/NextBSD/sys/dev/wb/
HDif_wbreg.h379 #define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg) macro

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