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Searched refs:COPY_TO_REGCLASS (Results 1 – 25 of 28) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrAVX512.td613 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
621 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
749 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
755 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
760 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
832 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
835 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
980 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
982 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1252 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
[all …]
HDX86InstrFMA.td192 (COPY_TO_REGCLASS
194 (COPY_TO_REGCLASS $src1, FR32),
195 (COPY_TO_REGCLASS $src2, FR32),
196 (COPY_TO_REGCLASS $src3, FR32)),
200 (COPY_TO_REGCLASS
202 (COPY_TO_REGCLASS $src1, FR64),
203 (COPY_TO_REGCLASS $src2, FR64),
204 (COPY_TO_REGCLASS $src3, FR64)),
HDX86InstrCompiler.td1284 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1291 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1327 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1334 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1366 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1370 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1388 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1392 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1398 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1403 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
[all …]
HDX86InstrSSE.td334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
[all …]
HDX86InstrFPStack.td682 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
684 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
686 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
692 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
694 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
696 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
HDX86ISelDAGToDAG.cpp2725 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
2761 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrVSX.td882 (COPY_TO_REGCLASS $A, VSRC)>;
884 (COPY_TO_REGCLASS $A, VSRC)>;
886 (COPY_TO_REGCLASS $A, VSRC)>;
888 (COPY_TO_REGCLASS $A, VSRC)>;
891 (COPY_TO_REGCLASS $A, VRRC)>;
893 (COPY_TO_REGCLASS $A, VRRC)>;
895 (COPY_TO_REGCLASS $A, VRRC)>;
897 (COPY_TO_REGCLASS $A, VRRC)>;
900 (COPY_TO_REGCLASS $A, VSRC)>;
902 (COPY_TO_REGCLASS $A, VSRC)>;
[all …]
HDPPCInstrQPX.td880 (QVFCPSGN (COPY_TO_REGCLASS $frA, QFRC), $frB)>;
882 (QVFCPSGNs (COPY_TO_REGCLASS $frA, QSRC), $frB)>;
1107 (COPY_TO_REGCLASS $src, QFRC)>;
1110 (COPY_TO_REGCLASS $src, QSRC)>;
1115 (COPY_TO_REGCLASS $src, QFRC)>;
HDPPCVSXSwapRemoval.cpp412 case PPC::COPY_TO_REGCLASS: in gatherVectorInstructions()
HDPPCInstrInfo.td2762 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2764 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2767 (COPY_TO_REGCLASS $src, F8RC)>;
2791 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2793 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
HDPPCFastISel.cpp1127 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg) in SelectFPToI()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetOpcodes.h66 COPY_TO_REGCLASS = 10, enumerator
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsMSAInstrInfo.td3613 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3671 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3679 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3694 (COPY_TO_REGCLASS
3696 (COPY_TO_REGCLASS
3697 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3792 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3797 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3802 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3807 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
[all …]
HDMipsDSPInstrInfo.td1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1289 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1291 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1293 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1295 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1340 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1348 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
HDMipsSEISelDAGToDAG.cpp937 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL, in selectNode()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrVFP.td613 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
616 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
619 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
622 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
676 (COPY_TO_REGCLASS
680 (COPY_TO_REGCLASS
686 (COPY_TO_REGCLASS
690 (COPY_TO_REGCLASS
1004 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1022 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
[all …]
HDARMInstrNEON.td5623 (COPY_TO_REGCLASS
5627 (COPY_TO_REGCLASS
5631 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5634 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5693 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5696 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
6254 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6256 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6263 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6270 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td520 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
522 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
3765 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3768 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3772 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3775 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
5331 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5332 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5333 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5334 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
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/NextBSD/contrib/llvm/lib/Target/PowerPC/InstPrinter/
HDPPCInstPrinter.cpp147 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS) in printInst()
/NextBSD/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/
HDPPCMCCodeEmitter.cpp110 if (Opcode == TargetOpcode::COPY_TO_REGCLASS) in encodeInstruction()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstr64Bit.td22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.cpp734 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { in EmitMachineNode()
HDScheduleDAGRRList.cpp2955 TargetOpcode::COPY_TO_REGCLASS) in AddPseudoTwoAddrDeps()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelDAGToDAG.cpp362 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, in Select()
HDSIISelLowering.cpp2048 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in adjustWritemask()

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