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Searched refs:BasePtr (Results 1 – 25 of 27) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZRegisterInfo.cpp72 unsigned BasePtr = getFrameRegister(MF); in eliminateFrameIndex() local
78 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false); in eliminateFrameIndex()
88 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
110 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
118 .addReg(BasePtr).addImm(HighOffset).addReg(0); in eliminateFrameIndex()
124 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr); in eliminateFrameIndex()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCLoopPreIncPrep.cpp118 static bool IsPtrInBounds(Value *BasePtr) { in IsPtrInBounds() argument
119 Value *StrippedBasePtr = BasePtr; in IsPtrInBounds()
266 Value *BasePtr = GetPointerOperand(MemI); in runOnLoop() local
267 assert(BasePtr && "No pointer operand"); in runOnLoop()
271 BasePtr->getType()->getPointerAddressSpace()); in runOnLoop()
309 PtrInc->setIsInBounds(IsPtrInBounds(BasePtr)); in runOnLoop()
319 if (PtrInc->getType() != BasePtr->getType()) in runOnLoop()
320 NewBasePtr = new BitCastInst(PtrInc, BasePtr->getType(), in runOnLoop()
325 if (Instruction *IDel = dyn_cast<Instruction>(BasePtr)) in runOnLoop()
327 BasePtr->replaceAllUsesWith(NewBasePtr); in runOnLoop()
[all …]
HDPPCISelLowering.cpp5928 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD() local
5933 BasePtr, MVT::i8, MMO); in LowerLOAD()
5953 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE() local
5959 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
7587 SDValue BasePtr = LN->getBasePtr(); in LowerVectorLoad() local
7608 BasePtr, in LowerVectorLoad()
7615 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr, in LowerVectorLoad()
7624 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(), in LowerVectorLoad()
7631 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, in LowerVectorLoad()
7633 BasePtr.getValueType())); in LowerVectorLoad()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86RegisterInfo.cpp79 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
84 BasePtr = X86::ESI; in X86RegisterInfo()
374 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64, in getReservedRegs() local
376 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true); in getReservedRegs()
474 return MRI->canReserveReg(BasePtr); in canRealignStack()
508 unsigned BasePtr; in eliminateFrameIndex() local
514 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister()); in eliminateFrameIndex()
516 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); in eliminateFrameIndex()
518 BasePtr = StackPtr; in eliminateFrameIndex()
520 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); in eliminateFrameIndex()
[all …]
HDX86RegisterInfo.h50 unsigned BasePtr; variable
126 unsigned getBaseRegister() const { return BasePtr; } in getBaseRegister()
HDX86FrameLowering.cpp660 unsigned BasePtr = TRI->getBaseRegister(); in emitPrologue() local
966 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr) in emitPrologue()
985 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), BasePtr, true, in emitPrologue()
/NextBSD/contrib/llvm/lib/CodeGen/
HDShadowStackGCLowering.cpp56 Type *Ty, Value *BasePtr, int Idx1,
59 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
351 Value *BasePtr, int Idx, in CreateGEP() argument
357 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name); in CreateGEP()
365 IRBuilder<> &B, Type *Ty, Value *BasePtr, in CreateGEP() argument
369 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name); in CreateGEP()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430RegisterInfo.cpp116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); in eliminateFrameIndex() local
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseRegisterInfo.h84 unsigned BasePtr;
153 unsigned getBaseRegister() const { return BasePtr; } in getBaseRegister()
HDARMBaseRegisterInfo.cpp49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {} in ARMBaseRegisterInfo()
141 Reserved.set(BasePtr); in getReservedRegs()
355 return MRI->canReserveReg(BasePtr); in canRealignStack()
HDThumb1FrameLowering.cpp105 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue() local
296 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
HDThumbRegisterInfo.cpp527 FrameReg = BasePtr; in eliminateFrameIndex()
HDARMISelLowering.cpp8772 SDValue BasePtr = LD->getBasePtr(); in PerformVMOVRRDCombine() local
8773 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, in PerformVMOVRRDCombine()
8778 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformVMOVRRDCombine()
9448 SDValue BasePtr = St->getBasePtr(); in PerformSTORECombine() local
9456 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr, in PerformSTORECombine()
9459 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr, in PerformSTORECombine()
9476 SDValue BasePtr = St->getBasePtr(); in PerformSTORECombine() local
9479 BasePtr, St->getPointerInfo(), St->isVolatile(), in PerformSTORECombine()
9482 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformSTORECombine()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp3213 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorLoads() local
3227 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), in GenWidenVectorLoads()
3263 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, in GenWidenVectorLoads()
3264 DAG.getConstant(Increment, dl, BasePtr.getValueType())); in GenWidenVectorLoads()
3271 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, in GenWidenVectorLoads()
3287 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, in GenWidenVectorLoads()
3366 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorExtLoads() local
3381 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, in GenWidenVectorExtLoads()
3388 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), in GenWidenVectorExtLoads()
3389 BasePtr, in GenWidenVectorExtLoads()
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HDDAGCombiner.cpp5185 SDValue BasePtr = MSC->getBasePtr(); in visitMSCATTER() local
5194 SDValue OpsLo[] = { Chain, DataLo, MaskLo, BasePtr, IndexLo }; in visitMSCATTER()
5198 SDValue OpsHi[] = {Chain, DataHi, MaskHi, BasePtr, IndexHi}; in visitMSCATTER()
5323 SDValue BasePtr = MGT->getBasePtr(); in visitMGATHER() local
5333 SDValue OpsLo[] = { Chain, Src0Lo, MaskLo, BasePtr, IndexLo }; in visitMGATHER()
5337 SDValue OpsHi[] = {Chain, Src0Hi, MaskHi, BasePtr, IndexHi}; in visitMGATHER()
5790 SDValue BasePtr = LN0->getBasePtr(); in CombineExtLoad() local
5796 ExtType, DL, SplitDstVT, LN0->getChain(), BasePtr, in CombineExtLoad()
5801 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr, in CombineExtLoad()
5802 DAG.getConstant(Stride, DL, BasePtr.getValueType())); in CombineExtLoad()
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HDSelectionDAGBuilder.cpp3153 Value *BasePtr = Ptr; in visitMaskedScatter() local
3154 bool UniformBase = getUniformBase(BasePtr, Base, Index, this); in visitMaskedScatter()
3156 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr; in visitMaskedScatter()
3232 Value *BasePtr = Ptr; in visitMaskedGather() local
3233 bool UniformBase = getUniformBase(BasePtr, Base, Index, this); in visitMaskedGather()
3237 MemoryLocation(BasePtr, AA->getTypeStoreSize(I.getType()), AAInfo))) { in visitMaskedGather()
3245 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr), in visitMaskedGather()
/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDLoopIdiomRecognize.cpp948 Value *BasePtr = in processLoopStridedStore() local
952 if (mayLoopAccessLocation(BasePtr, AliasAnalysis::ModRef, in processLoopStridedStore()
957 RecursivelyDeleteTriviallyDeadInstructions(BasePtr, TLI); in processLoopStridedStore()
980 NewCall = Builder.CreateMemSet(BasePtr, in processLoopStridedStore()
1004 NewCall = Builder.CreateCall(MSP, {BasePtr, PatternPtr, NumBytes}); in processLoopStridedStore()
HDSROA.cpp1545 static Value *buildGEP(IRBuilderTy &IRB, Value *BasePtr, in buildGEP() argument
1548 return BasePtr; in buildGEP()
1553 return BasePtr; in buildGEP()
1555 return IRB.CreateInBoundsGEP(nullptr, BasePtr, Indices, in buildGEP()
1569 Value *BasePtr, Type *Ty, Type *TargetTy, in getNaturalGEPWithType() argument
1573 return buildGEP(IRB, BasePtr, Indices, NamePrefix); in getNaturalGEPWithType()
1576 unsigned PtrSize = DL.getPointerTypeSizeInBits(BasePtr->getType()); in getNaturalGEPWithType()
1605 return buildGEP(IRB, BasePtr, Indices, NamePrefix); in getNaturalGEPWithType()
3775 Instruction *BasePtr = cast<Instruction>(LI->getPointerOperand()); in presplitLoadsAndStores() local
3786 getAdjustedPtr(IRB, DL, BasePtr, in presplitLoadsAndStores()
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp447 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD() local
453 if (DAG.isBaseWithConstantOffset(BasePtr) && in LowerLOAD()
454 isWordAligned(BasePtr->getOperand(0), DAG)) { in LowerLOAD()
455 SDValue NewBasePtr = BasePtr->getOperand(0); in LowerLOAD()
456 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); in LowerLOAD()
460 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && in LowerLOAD()
463 BasePtr->getValueType(0)); in LowerLOAD()
471 BasePtr, LD->getPointerInfo(), MVT::i16, in LowerLOAD()
474 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in LowerLOAD()
496 Entry.Node = BasePtr; in LowerLOAD()
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/NextBSD/contrib/llvm/tools/clang/lib/AST/
HDCXXInheritance.cpp105 const void *BasePtr = static_cast<const void*>(Base->getCanonicalDecl()); in isVirtuallyDerivedFrom() local
107 const_cast<void *>(BasePtr), in isVirtuallyDerivedFrom()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp1259 SDValue BasePtr = Load->getBasePtr(); in SplitVectorLoad() local
1260 EVT PtrVT = BasePtr.getValueType(); in SplitVectorLoad()
1274 Load->getChain(), BasePtr, in SplitVectorLoad()
1279 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in SplitVectorLoad()
1402 SDValue BasePtr = Store->getBasePtr(); in SplitVectorStore() local
1413 EVT PtrVT = BasePtr.getValueType(); in SplitVectorStore()
1414 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in SplitVectorStore()
1421 BasePtr, in SplitVectorStore()
1453 SDValue BasePtr = Load->getBasePtr(); in LowerLOAD() local
1457 BasePtr, MVT::i8, MMO); in LowerLOAD()
[all …]
HDSIISelLowering.cpp449 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL, in LowerParameter() local
451 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in LowerParameter()
/NextBSD/contrib/llvm/lib/Analysis/
HDConstantFolding.cpp791 APInt BasePtr(BitWidth, 0); in SymbolicallyEvaluateGEP() local
795 BasePtr = Base->getValue().zextOrTrunc(BitWidth); in SymbolicallyEvaluateGEP()
799 if (Ptr->isNullValue() || BasePtr != 0) { in SymbolicallyEvaluateGEP()
800 Constant *C = ConstantInt::get(Ptr->getContext(), Offset + BasePtr); in SymbolicallyEvaluateGEP()
/NextBSD/contrib/llvm/tools/clang/lib/CodeGen/
HDCGClass.cpp653 llvm::Type *BasePtr = ConvertType(BaseElementTy); in EmitInitializerForField() local
654 BasePtr = llvm::PointerType::getUnqual(BasePtr); in EmitInitializerForField()
656 BasePtr); in EmitInitializerForField()
/NextBSD/contrib/llvm/lib/Bitcode/Reader/
HDBitcodeReader.cpp3539 Value *BasePtr; in parseFunctionBody() local
3540 if (getValueTypePair(Record, OpNum, NextValueNo, BasePtr)) in parseFunctionBody()
3544 Ty = cast<SequentialType>(BasePtr->getType()->getScalarType()) in parseFunctionBody()
3547 cast<SequentialType>(BasePtr->getType()->getScalarType()) in parseFunctionBody()
3560 I = GetElementPtrInst::Create(Ty, BasePtr, GEPIdx); in parseFunctionBody()

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