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Searched refs:BUILD_PAIR (Results 1 – 20 of 20) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h181 BUILD_PAIR, enumerator
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp700 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
708 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
723 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
767 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1814 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp289 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
HDLegalizeFloatTypes.cpp64 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
126 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
887 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
1321 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
HDLegalizeTypesGeneric.cpp139 Vals.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, in ExpandRes_BITCAST()
HDLegalizeIntegerTypes.cpp57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
856 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
1254 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
HDSelectionDAGBuilder.cpp152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
7279 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
HDTargetLowering.cpp882 case ISD::BUILD_PAIR: { in SimplifyDemandedBits()
HDSelectionDAG.cpp728 case ISD::BUILD_PAIR: { in VerifySDNode()
3589 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
HDDAGCombiner.cpp1371 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
7080 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
7243 if (N0.getOpcode() == ISD::BUILD_PAIR) { in visitBITCAST()
HDLegalizeDAG.cpp3827 case ISD::BUILD_PAIR: { in ExpandNode()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp1709 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero); in LowerUDIVREM64()
1710 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero); in LowerUDIVREM64()
1721 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero); in LowerUDIVREM64()
1751 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi); in LowerUDIVREM64()
2443 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo); in performShlCombine()
HDAMDGPUISelDAGToDAG.cpp406 case ISD::BUILD_PAIR: { in Select()
HDSIISelLowering.cpp960 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in LowerGlobalAddress()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp400 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
456 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1339 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp4151 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
4195 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
4569 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
6542 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceREADCYCLECOUNTER()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp1303 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in extractLOHI()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
5128 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
8009 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp12323 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops) in FP_TO_INTHelper()
15969 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadPerformanceCounter()
16023 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadTimeStampCounter()
18797 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF)); in ReplaceNodeResults()