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Searched refs:BLR (Results 1 – 11 of 11) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCEarlyReturn.cpp66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
HDPPCFrameLowering.cpp930 assert((RetOpcode == PPC::BLR || in emitEpilogue()
1113 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && in emitEpilogue()
HDPPCInstrInfo.cpp1247 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
1409 case PPC::BLR: in isPredicable()
HDPPCInstrInfo.td1098 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64AsmPrinter.cpp421 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
531 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
HDAArch64SchedA57.td132 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
HDAArch64FastISel.cpp3137 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL); in fastLowerCall()
3170 const MCInstrDesc &II = TII.get(AArch64::BLR); in fastLowerCall()
HDAArch64InstrInfo.td1121 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1139 // (which in the usual case is a BLR).
/NextBSD/contrib/binutils/bfd/
HDelf64-ppc.c199 #define BLR 0x4e800020 /* blr */ macro
5552 bfd_put_32 (abfd, BLR, p); in savegpr0_tail()
5576 bfd_put_32 (abfd, BLR, p); in restgpr0_tail()
5591 bfd_put_32 (abfd, BLR, p); in savegpr1_tail()
5606 bfd_put_32 (abfd, BLR, p); in restgpr1_tail()
5623 bfd_put_32 (abfd, BLR, p); in savefpr0_tail()
5647 bfd_put_32 (abfd, BLR, p); in restfpr0_tail()
5655 bfd_put_32 (abfd, BLR, p); in savefpr1_tail()
5663 bfd_put_32 (abfd, BLR, p); in restfpr1_tail()
5680 bfd_put_32 (abfd, BLR, p); in savevr_tail()
[all …]
HDChangeLog-020310162 * elf64-ppc.c (STFD_FR0_0R1, LFD_FR0_0R1, BLR): Define.
/NextBSD/share/misc/
HDiso316642 BY BLR 112 Belarus