| /NextBSD/crypto/heimdal/lib/asn1/ |
| HD | asn1-common.h | 51 #define ASN1_MALLOC_ENCODE(T, B, BL, S, L, R) \ argument 53 (BL) = length_##T((S)); \ 54 (B) = malloc((BL)); \ 58 (R) = encode_##T(((unsigned char*)(B)) + (BL) - 1, (BL), \
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| /NextBSD/contrib/gcc/config/arm/ |
| HD | README-interworking | 57 * Normal function calls can just use the BL instruction. The 242 pointer), the compiler generates a BL instruction to do this. The 243 Thumb version of the BL instruction has the special property of 246 return the instruction after the BL instruction, in Thumb mode. 248 The BL instruction does not change modes itself however, so if an ARM 252 into the BL instruction. If the BL instruction is an ARM style BL 255 mode to Thumb mode, puts the address of this stub into the BL 257 stub. Similarly if the BL instruction is a Thumb BL instruction, and 260 stub into the BL instruction, and the address of the referenced 311 The BL instruction ensures that the correct return address is stored [all …]
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86RegisterInfo.cpp | 622 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 634 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 635 return X86::BL; in getX86SubSuperRegisterOrZero() 671 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 707 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 743 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
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| HD | X86RegisterInfo.td | 51 def BL : X86Reg<"bl", 3>; 81 def BX : X86Reg<"bx", 3, [BL,BH]>; 329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 369 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 382 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreISelLowering.h | 34 BL, enumerator
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| HD | XCoreISelLowering.cpp | 50 case XCoreISD::BL : return "XCoreISD::BL"; in getTargetNodeName() 1242 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops); in LowerCCCCallTo()
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| HD | XCoreInstrInfo.td | 31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
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| /NextBSD/sys/i386/i386/ |
| HD | bpf_jit_machdep.h | 61 #define BL 3 macro
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| /NextBSD/contrib/llvm/include/llvm/DebugInfo/PDB/ |
| HD | PDBTypes.h | 375 BL = 4, enumerator
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| /NextBSD/sys/amd64/amd64/ |
| HD | bpf_jit_machdep.h | 86 #define BL 3 macro
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCAsmPrinter.cpp | 530 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BL).addExpr(OffsExpr)); in EmitInstruction() 542 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BL) in EmitInstruction() 819 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BL) in EmitInstruction()
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| /NextBSD/share/misc/ |
| HD | iso3166 | 206 BL BLM 652 Saint Barthelemy 526 # Added SAINT BARTHELEMY (BL) and SAINT MARTIN (MF).
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| /NextBSD/contrib/llvm/lib/Target/X86/Disassembler/ |
| HD | X86DisassemblerDecoder.h | 80 ENTRY(BL) \
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| /NextBSD/contrib/llvm/lib/DebugInfo/PDB/ |
| HD | PDBExtras.cpp | 99 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, BL, OS) in operator <<()
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| /NextBSD/contrib/llvm/tools/clang/lib/Frontend/ |
| HD | ASTUnit.cpp | 2542 SourceLocation BL = FileLoc.getLocWithOffset(Range.first); in TranslateStoredDiagnostics() local 2544 Ranges.push_back(CharSourceRange::getCharRange(BL, EL)); in TranslateStoredDiagnostics() 2553 SourceLocation BL = FileLoc.getLocWithOffset(FixIt.RemoveRange.first); in TranslateStoredDiagnostics() local 2555 FH.RemoveRange = CharSourceRange::getCharRange(BL, EL); in TranslateStoredDiagnostics()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| HD | AArch64MCCodeEmitter.cpp | 391 MCFixupKind Kind = MI.getOpcode() == AArch64::BL in getBranchTargetOpValue()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64CallingConvention.td | 252 // is currently safe since BL has LR as an implicit-def and what happens after a
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| HD | AArch64SchedA57.td | 131 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
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| /NextBSD/contrib/llvm/tools/clang/include/clang/AST/ |
| HD | Stmt.h | 1319 BreakStmt(SourceLocation BL) : Stmt(BreakStmtClass), BreakLoc(BL) { in BreakStmt() argument
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| /NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/ |
| HD | RetainCountChecker.cpp | 1930 else if (const ObjCBoxedExpr *BL = dyn_cast<ObjCBoxedExpr>(S)) { in VisitNode() local 1931 if (isNumericLiteralExpression(BL->getSubExpr())) in VisitNode() 1935 if (const ObjCMethodDecl *Method = BL->getBoxingMethod()) in VisitNode()
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| /NextBSD/contrib/tzdata/ |
| HD | zone.tab | 82 BL +1753-06251 America/St_Barthelemy
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| HD | zone1970.tab | 330 TT,AG,AI,BL,DM,GD,GP,KN,LC,MF,MS,VC,VG,VI +1039-06131 America/Port_of_Spain
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| /NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
| HD | BugReporter.cpp | 1509 PathDiagnosticLocation BL = in GenerateExtensivePathDiagnostic() local 1511 EB.addEdge(BL); in GenerateExtensivePathDiagnostic()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMExpandPseudoInsts.cpp | 941 TII->get( ARM::BL)) in ExpandMI()
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| HD | ARMFrameLowering.cpp | 2089 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
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