1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __R500_REG_H__ 29 #define __R500_REG_H__ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* pipe config regs */ 35 #define R300_GA_POLY_MODE 0x4288 36 # define R300_FRONT_PTYPE_POINT (0 << 4) 37 # define R300_FRONT_PTYPE_LINE (1 << 4) 38 # define R300_FRONT_PTYPE_TRIANGE (2 << 4) 39 # define R300_BACK_PTYPE_POINT (0 << 7) 40 # define R300_BACK_PTYPE_LINE (1 << 7) 41 # define R300_BACK_PTYPE_TRIANGE (2 << 7) 42 #define R300_GA_ROUND_MODE 0x428c 43 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) 44 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) 45 # define R300_COLOR_ROUND_TRUNC (0 << 2) 46 # define R300_COLOR_ROUND_NEAREST (1 << 2) 47 #define R300_GB_MSPOS0 0x4010 48 # define R300_MS_X0_SHIFT 0 49 # define R300_MS_Y0_SHIFT 4 50 # define R300_MS_X1_SHIFT 8 51 # define R300_MS_Y1_SHIFT 12 52 # define R300_MS_X2_SHIFT 16 53 # define R300_MS_Y2_SHIFT 20 54 # define R300_MSBD0_Y_SHIFT 24 55 # define R300_MSBD0_X_SHIFT 28 56 #define R300_GB_MSPOS1 0x4014 57 # define R300_MS_X3_SHIFT 0 58 # define R300_MS_Y3_SHIFT 4 59 # define R300_MS_X4_SHIFT 8 60 # define R300_MS_Y4_SHIFT 12 61 # define R300_MS_X5_SHIFT 16 62 # define R300_MS_Y5_SHIFT 20 63 # define R300_MSBD1_SHIFT 24 64 65 #define R300_GA_ENHANCE 0x4274 66 # define R300_GA_DEADLOCK_CNTL (1 << 0) 67 # define R300_GA_FASTSYNC_CNTL (1 << 1) 68 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 69 # define R300_RB3D_DC_FLUSH (2 << 0) 70 # define R300_RB3D_DC_FREE (2 << 2) 71 # define R300_RB3D_DC_FINISH (1 << 4) 72 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 73 # define R300_ZC_FLUSH (1 << 0) 74 # define R300_ZC_FREE (1 << 1) 75 # define R300_ZC_FLUSH_ALL 0x3 76 #define R400_GB_PIPE_SELECT 0x402c 77 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 78 #define R500_SU_REG_DEST 0x42c8 79 #define R300_GB_TILE_CONFIG 0x4018 80 # define R300_ENABLE_TILING (1 << 0) 81 # define R300_PIPE_COUNT_RV350 (0 << 1) 82 # define R300_PIPE_COUNT_R300 (3 << 1) 83 # define R300_PIPE_COUNT_R420_3P (6 << 1) 84 # define R300_PIPE_COUNT_R420 (7 << 1) 85 # define R300_TILE_SIZE_8 (0 << 4) 86 # define R300_TILE_SIZE_16 (1 << 4) 87 # define R300_TILE_SIZE_32 (2 << 4) 88 # define R300_SUBPIXEL_1_12 (0 << 16) 89 # define R300_SUBPIXEL_1_16 (1 << 16) 90 #define R300_DST_PIPE_CONFIG 0x170c 91 # define R300_PIPE_AUTO_CONFIG (1U << 31) 92 #define R300_RB2D_DSTCACHE_MODE 0x3428 93 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 94 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 95 96 #define RADEON_CP_STAT 0x7C0 97 #define RADEON_RBBM_CMDFIFO_ADDR 0xE70 98 #define RADEON_RBBM_CMDFIFO_DATA 0xE74 99 #define RADEON_ISYNC_CNTL 0x1724 100 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 101 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 102 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 103 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 104 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 105 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 106 107 #define RS480_NB_MC_INDEX 0x168 108 # define RS480_NB_MC_IND_WR_EN (1 << 8) 109 #define RS480_NB_MC_DATA 0x16c 110 111 /* 112 * RS690 113 */ 114 #define RS690_MCCFG_FB_LOCATION 0x100 115 #define RS690_MC_FB_START_MASK 0x0000FFFF 116 #define RS690_MC_FB_START_SHIFT 0 117 #define RS690_MC_FB_TOP_MASK 0xFFFF0000 118 #define RS690_MC_FB_TOP_SHIFT 16 119 #define RS690_MCCFG_AGP_LOCATION 0x101 120 #define RS690_MC_AGP_START_MASK 0x0000FFFF 121 #define RS690_MC_AGP_START_SHIFT 0 122 #define RS690_MC_AGP_TOP_MASK 0xFFFF0000 123 #define RS690_MC_AGP_TOP_SHIFT 16 124 #define RS690_MCCFG_AGP_BASE 0x102 125 #define RS690_MCCFG_AGP_BASE_2 0x103 126 #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 127 #define RS690_HDP_FB_LOCATION 0x0134 128 #define RS690_MC_INDEX 0x78 129 # define RS690_MC_INDEX_MASK 0x1ff 130 # define RS690_MC_INDEX_WR_EN (1 << 9) 131 # define RS690_MC_INDEX_WR_ACK 0x7f 132 #define RS690_MC_DATA 0x7c 133 #define RS690_MC_STATUS 0x90 134 #define RS690_MC_STATUS_IDLE (1 << 0) 135 #define RS480_AGP_BASE_2 0x0164 136 #define RS480_MC_MISC_CNTL 0x18 137 # define RS480_DISABLE_GTW (1 << 1) 138 # define RS480_GART_INDEX_REG_EN (1 << 12) 139 # define RS690_BLOCK_GFX_D3_EN (1 << 14) 140 #define RS480_GART_FEATURE_ID 0x2b 141 # define RS480_HANG_EN (1 << 11) 142 # define RS480_TLB_ENABLE (1 << 18) 143 # define RS480_P2P_ENABLE (1 << 19) 144 # define RS480_GTW_LAC_EN (1 << 25) 145 # define RS480_2LEVEL_GART (0 << 30) 146 # define RS480_1LEVEL_GART (1 << 30) 147 # define RS480_PDC_EN (1U << 31) 148 #define RS480_GART_BASE 0x2c 149 #define RS480_GART_CACHE_CNTRL 0x2e 150 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 151 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 152 # define RS480_GART_EN (1 << 0) 153 # define RS480_VA_SIZE_32MB (0 << 1) 154 # define RS480_VA_SIZE_64MB (1 << 1) 155 # define RS480_VA_SIZE_128MB (2 << 1) 156 # define RS480_VA_SIZE_256MB (3 << 1) 157 # define RS480_VA_SIZE_512MB (4 << 1) 158 # define RS480_VA_SIZE_1GB (5 << 1) 159 # define RS480_VA_SIZE_2GB (6 << 1) 160 #define RS480_AGP_MODE_CNTL 0x39 161 # define RS480_POST_GART_Q_SIZE (1 << 18) 162 # define RS480_NONGART_SNOOP (1 << 19) 163 # define RS480_AGP_RD_BUF_SIZE (1 << 20) 164 # define RS480_REQ_TYPE_SNOOP_SHIFT 22 165 # define RS480_REQ_TYPE_SNOOP_MASK 0x3 166 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 167 168 #define RS690_AIC_CTRL_SCRATCH 0x3A 169 # define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) 170 171 /* 172 * RS600 173 */ 174 #define RS600_MC_STATUS 0x0 175 #define RS600_MC_STATUS_IDLE (1 << 0) 176 #define RS600_MC_INDEX 0x70 177 # define RS600_MC_ADDR_MASK 0xffff 178 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 179 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 180 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 181 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 182 # define RS600_MC_IND_AIC_RBS (1 << 20) 183 # define RS600_MC_IND_CITF_ARB0 (1 << 21) 184 # define RS600_MC_IND_CITF_ARB1 (1 << 22) 185 # define RS600_MC_IND_WR_EN (1 << 23) 186 #define RS600_MC_DATA 0x74 187 #define RS600_MC_STATUS 0x0 188 # define RS600_MC_IDLE (1 << 1) 189 #define RS600_MC_FB_LOCATION 0x4 190 #define RS600_MC_FB_START_MASK 0x0000FFFF 191 #define RS600_MC_FB_START_SHIFT 0 192 #define RS600_MC_FB_TOP_MASK 0xFFFF0000 193 #define RS600_MC_FB_TOP_SHIFT 16 194 #define RS600_MC_AGP_LOCATION 0x5 195 #define RS600_MC_AGP_START_MASK 0x0000FFFF 196 #define RS600_MC_AGP_START_SHIFT 0 197 #define RS600_MC_AGP_TOP_MASK 0xFFFF0000 198 #define RS600_MC_AGP_TOP_SHIFT 16 199 #define RS600_MC_AGP_BASE 0x6 200 #define RS600_MC_AGP_BASE_2 0x7 201 #define RS600_MC_CNTL1 0x9 202 # define RS600_ENABLE_PAGE_TABLES (1 << 26) 203 #define RS600_MC_PT0_CNTL 0x100 204 # define RS600_ENABLE_PT (1 << 0) 205 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 206 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 207 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 208 # define RS600_INVALIDATE_L2_CACHE (1 << 29) 209 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 210 # define RS600_ENABLE_PAGE_TABLE (1 << 0) 211 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 212 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 213 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 214 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 215 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 216 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 217 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 218 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c 219 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 220 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 221 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 222 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 223 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 224 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 225 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 226 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 227 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 228 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 229 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 230 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 231 # define RS600_INVALIDATE_L1_TLB (1 << 20) 232 /* rs600/rs690/rs740 */ 233 # define RS600_BUS_MASTER_DIS (1 << 14) 234 # define RS600_MSI_REARM (1 << 20) 235 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 236 237 238 239 #define RV515_MC_FB_LOCATION 0x01 240 #define RV515_MC_FB_START_MASK 0x0000FFFF 241 #define RV515_MC_FB_START_SHIFT 0 242 #define RV515_MC_FB_TOP_MASK 0xFFFF0000 243 #define RV515_MC_FB_TOP_SHIFT 16 244 #define RV515_MC_AGP_LOCATION 0x02 245 #define RV515_MC_AGP_START_MASK 0x0000FFFF 246 #define RV515_MC_AGP_START_SHIFT 0 247 #define RV515_MC_AGP_TOP_MASK 0xFFFF0000 248 #define RV515_MC_AGP_TOP_SHIFT 16 249 #define RV515_MC_AGP_BASE 0x03 250 #define RV515_MC_AGP_BASE_2 0x04 251 252 #define R520_MC_FB_LOCATION 0x04 253 #define R520_MC_FB_START_MASK 0x0000FFFF 254 #define R520_MC_FB_START_SHIFT 0 255 #define R520_MC_FB_TOP_MASK 0xFFFF0000 256 #define R520_MC_FB_TOP_SHIFT 16 257 #define R520_MC_AGP_LOCATION 0x05 258 #define R520_MC_AGP_START_MASK 0x0000FFFF 259 #define R520_MC_AGP_START_SHIFT 0 260 #define R520_MC_AGP_TOP_MASK 0xFFFF0000 261 #define R520_MC_AGP_TOP_SHIFT 16 262 #define R520_MC_AGP_BASE 0x06 263 #define R520_MC_AGP_BASE_2 0x07 264 265 266 #define AVIVO_MC_INDEX 0x0070 267 #define R520_MC_STATUS 0x00 268 #define R520_MC_STATUS_IDLE (1<<1) 269 #define RV515_MC_STATUS 0x08 270 #define RV515_MC_STATUS_IDLE (1<<4) 271 #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 272 #define AVIVO_MC_DATA 0x0074 273 274 #define R520_MC_IND_INDEX 0x70 275 #define R520_MC_IND_WR_EN (1 << 24) 276 #define R520_MC_IND_DATA 0x74 277 278 #define RV515_MC_CNTL 0x5 279 # define RV515_MEM_NUM_CHANNELS_MASK 0x3 280 #define R520_MC_CNTL0 0x8 281 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) 282 # define R520_MEM_NUM_CHANNELS_SHIFT 24 283 # define R520_MC_CHANNEL_SIZE (1 << 23) 284 285 #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ 286 # define AVIVO_CP_FORCEON (1 << 0) 287 #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ 288 # define AVIVO_E2_FORCEON (1 << 0) 289 #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ 290 # define AVIVO_IDCT_FORCEON (1 << 0) 291 292 #define AVIVO_HDP_FB_LOCATION 0x134 293 294 #define AVIVO_VGA_RENDER_CONTROL 0x0300 295 # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) 296 #define AVIVO_D1VGA_CONTROL 0x0330 297 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) 298 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) 299 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) 300 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) 301 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) 302 # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) 303 #define AVIVO_D2VGA_CONTROL 0x0338 304 305 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 306 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 307 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 308 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c 309 310 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 311 #define AVIVO_EXT2_PPLL_REF_DIV 0x414 312 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 313 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c 314 315 #define AVIVO_EXT1_PPLL_FB_DIV 0x430 316 #define AVIVO_EXT2_PPLL_FB_DIV 0x434 317 318 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 319 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c 320 321 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 322 #define AVIVO_EXT2_PPLL_POST_DIV 0x444 323 324 #define AVIVO_EXT1_PPLL_CNTL 0x448 325 #define AVIVO_EXT2_PPLL_CNTL 0x44c 326 327 #define AVIVO_P1PLL_CNTL 0x450 328 #define AVIVO_P2PLL_CNTL 0x454 329 #define AVIVO_P1PLL_INT_SS_CNTL 0x458 330 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c 331 #define AVIVO_P1PLL_TMDSA_CNTL 0x460 332 #define AVIVO_P2PLL_LVTMA_CNTL 0x464 333 334 #define AVIVO_PCLK_CRTC1_CNTL 0x480 335 #define AVIVO_PCLK_CRTC2_CNTL 0x484 336 337 #define AVIVO_D1CRTC_H_TOTAL 0x6000 338 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 339 #define AVIVO_D1CRTC_H_SYNC_A 0x6008 340 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c 341 #define AVIVO_D1CRTC_H_SYNC_B 0x6010 342 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 343 344 #define AVIVO_D1CRTC_V_TOTAL 0x6020 345 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 346 #define AVIVO_D1CRTC_V_SYNC_A 0x6028 347 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c 348 #define AVIVO_D1CRTC_V_SYNC_B 0x6030 349 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 350 351 #define AVIVO_D1CRTC_CONTROL 0x6080 352 # define AVIVO_CRTC_EN (1 << 0) 353 # define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 354 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 355 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 356 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c 357 #define AVIVO_D1CRTC_STATUS 0x609c 358 # define AVIVO_D1CRTC_V_BLANK (1 << 0) 359 #define AVIVO_D1CRTC_STATUS_POSITION 0x60a0 360 #define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 361 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 362 363 #define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0 364 #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 365 #define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8 366 367 /* master controls */ 368 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 369 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc 370 371 #define AVIVO_D1GRPH_ENABLE 0x6100 372 #define AVIVO_D1GRPH_CONTROL 0x6104 373 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) 374 # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) 375 # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) 376 # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) 377 378 # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) 379 380 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) 381 # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) 382 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) 383 # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) 384 # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) 385 386 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) 387 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) 388 # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) 389 # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) 390 391 392 # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) 393 394 # define AVIVO_D1GRPH_SWAP_RB (1 << 16) 395 # define AVIVO_D1GRPH_TILED (1 << 20) 396 # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 397 398 # define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 399 # define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 400 # define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 401 # define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 402 403 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 404 * block and vice versa. This applies to GRPH, CUR, etc. 405 */ 406 #define AVIVO_D1GRPH_LUT_SEL 0x6108 407 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 408 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 409 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 410 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 411 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 412 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 413 #define AVIVO_D1GRPH_PITCH 0x6120 414 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 415 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 416 #define AVIVO_D1GRPH_X_START 0x612c 417 #define AVIVO_D1GRPH_Y_START 0x6130 418 #define AVIVO_D1GRPH_X_END 0x6134 419 #define AVIVO_D1GRPH_Y_END 0x6138 420 #define AVIVO_D1GRPH_UPDATE 0x6144 421 # define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2) 422 # define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) 423 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 424 # define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 425 426 #define AVIVO_D1CUR_CONTROL 0x6400 427 # define AVIVO_D1CURSOR_EN (1 << 0) 428 # define AVIVO_D1CURSOR_MODE_SHIFT 8 429 # define AVIVO_D1CURSOR_MODE_MASK (3 << 8) 430 # define AVIVO_D1CURSOR_MODE_24BPP 2 431 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 432 #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c 433 #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c 434 #define AVIVO_D1CUR_SIZE 0x6410 435 #define AVIVO_D1CUR_POSITION 0x6414 436 #define AVIVO_D1CUR_HOT_SPOT 0x6418 437 #define AVIVO_D1CUR_UPDATE 0x6424 438 # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) 439 440 #define AVIVO_DC_LUT_RW_SELECT 0x6480 441 #define AVIVO_DC_LUT_RW_MODE 0x6484 442 #define AVIVO_DC_LUT_RW_INDEX 0x6488 443 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 444 #define AVIVO_DC_LUT_PWL_DATA 0x6490 445 #define AVIVO_DC_LUT_30_COLOR 0x6494 446 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 447 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 448 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 449 450 #define AVIVO_DC_LUTA_CONTROL 0x64c0 451 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 452 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 453 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 454 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 455 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 456 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 457 458 #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 459 # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 460 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 461 # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 462 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 463 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 464 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 465 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 466 # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 467 # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 468 469 #define AVIVO_D1MODE_DATA_FORMAT 0x6528 470 # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 471 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 472 #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 473 # define AVIVO_VBLANK_ACK (1 << 4) 474 #define AVIVO_D1MODE_VLINE_START_END 0x6538 475 #define AVIVO_D1MODE_VLINE_STATUS 0x653c 476 # define AVIVO_D1MODE_VLINE_STAT (1 << 12) 477 #define AVIVO_DxMODE_INT_MASK 0x6540 478 # define AVIVO_D1MODE_INT_MASK (1 << 0) 479 # define AVIVO_D2MODE_INT_MASK (1 << 8) 480 #define AVIVO_D1MODE_VIEWPORT_START 0x6580 481 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 482 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 483 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c 484 485 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 486 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 487 #define AVIVO_D1SCL_UPDATE 0x65cc 488 # define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) 489 490 /* second crtc */ 491 #define AVIVO_D2CRTC_H_TOTAL 0x6800 492 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 493 #define AVIVO_D2CRTC_H_SYNC_A 0x6808 494 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c 495 #define AVIVO_D2CRTC_H_SYNC_B 0x6810 496 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 497 498 #define AVIVO_D2CRTC_V_TOTAL 0x6820 499 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 500 #define AVIVO_D2CRTC_V_SYNC_A 0x6828 501 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c 502 #define AVIVO_D2CRTC_V_SYNC_B 0x6830 503 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 504 505 #define AVIVO_D2CRTC_CONTROL 0x6880 506 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 507 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 508 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c 509 #define AVIVO_D2CRTC_STATUS_POSITION 0x68a0 510 #define AVIVO_D2CRTC_FRAME_COUNT 0x68a4 511 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 512 513 #define AVIVO_D2GRPH_ENABLE 0x6900 514 #define AVIVO_D2GRPH_CONTROL 0x6904 515 #define AVIVO_D2GRPH_LUT_SEL 0x6908 516 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 517 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 518 #define AVIVO_D2GRPH_PITCH 0x6920 519 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 520 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 521 #define AVIVO_D2GRPH_X_START 0x692c 522 #define AVIVO_D2GRPH_Y_START 0x6930 523 #define AVIVO_D2GRPH_X_END 0x6934 524 #define AVIVO_D2GRPH_Y_END 0x6938 525 #define AVIVO_D2GRPH_UPDATE 0x6944 526 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 527 528 #define AVIVO_D2CUR_CONTROL 0x6c00 529 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 530 #define AVIVO_D2CUR_SIZE 0x6c10 531 #define AVIVO_D2CUR_POSITION 0x6c14 532 533 #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 534 #define AVIVO_D2MODE_VLINE_START_END 0x6d38 535 #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c 536 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 537 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 538 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 539 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c 540 541 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 542 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 543 544 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 545 546 #define AVIVO_DACA_ENABLE 0x7800 547 # define AVIVO_DAC_ENABLE (1 << 0) 548 #define AVIVO_DACA_SOURCE_SELECT 0x7804 549 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) 550 # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) 551 # define AVIVO_DAC_SOURCE_TV (2 << 0) 552 553 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c 554 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 555 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 556 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 557 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 558 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 559 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 560 #define AVIVO_DACA_POWERDOWN 0x7850 561 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) 562 # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) 563 # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) 564 # define AVIVO_DACA_POWERDOWN_RED (1 << 24) 565 566 #define AVIVO_DACB_ENABLE 0x7a00 567 #define AVIVO_DACB_SOURCE_SELECT 0x7a04 568 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c 569 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 570 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 571 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 572 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 573 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 574 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 575 #define AVIVO_DACB_POWERDOWN 0x7a50 576 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) 577 # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) 578 # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) 579 # define AVIVO_DACB_POWERDOWN_RED 580 581 #define AVIVO_TMDSA_CNTL 0x7880 582 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) 583 # define AVIVO_TMDSA_CNTL_HDMI_EN (1 << 2) 584 # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) 585 # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) 586 # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) 587 # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) 588 # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) 589 # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) 590 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 591 /* 78a8 appears to be some kind of (reasonably tolerant) clock? 592 * 78d0 definitely hits the transmitter, definitely clock. */ 593 /* MYSTERY1 This appears to control dithering? */ 594 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 595 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 596 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 597 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 598 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 599 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 600 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 601 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 602 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 603 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 604 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) 605 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 606 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 607 # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) 608 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 609 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 610 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 611 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 612 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 613 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) 614 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 615 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 616 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 617 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 618 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) 619 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 620 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 621 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 622 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) 623 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 624 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 625 626 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 627 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 628 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 629 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 630 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 631 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 632 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 633 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 634 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 635 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 636 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 637 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 638 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 639 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 640 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) 641 642 #define AVIVO_LVTMA_CNTL 0x7a80 643 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) 644 # define AVIVO_LVTMA_CNTL_HDMI_EN (1 << 2) 645 # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) 646 # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) 647 # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) 648 # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) 649 # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) 650 # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) 651 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 652 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 653 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 654 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 655 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 656 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 657 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 658 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 659 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 660 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 661 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 662 663 664 665 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 666 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) 667 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 668 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 669 # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) 670 671 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 672 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 673 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 674 #define R500_LVTMA_CLOCK_ENABLE 0x7b00 675 #define R600_LVTMA_CLOCK_ENABLE 0x7b04 676 677 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 678 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 679 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 680 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 681 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 682 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 683 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) 684 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) 685 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 686 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 687 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 688 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 689 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 690 691 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 692 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 693 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 694 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 695 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 696 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 697 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 698 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 699 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 700 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 701 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 702 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 703 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 704 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 705 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 706 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) 707 708 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 709 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 710 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) 711 # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) 712 # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) 713 # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) 714 # define AVIVO_LVTMA_SYNCEN (1 << 8) 715 # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) 716 # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) 717 # define AVIVO_LVTMA_DIGON (1 << 16) 718 # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) 719 # define AVIVO_LVTMA_DIGON_POL (1 << 18) 720 # define AVIVO_LVTMA_BLON (1 << 24) 721 # define AVIVO_LVTMA_BLON_OVRD (1 << 25) 722 # define AVIVO_LVTMA_BLON_POL (1 << 26) 723 724 #define R500_LVTMA_PWRSEQ_STATE 0x7af4 725 #define R600_LVTMA_PWRSEQ_STATE 0x7af8 726 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) 727 # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) 728 # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) 729 # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) 730 # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) 731 # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) 732 733 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 734 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) 735 # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 736 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 737 738 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 739 740 #define AVIVO_DC_GPIO_HPD_A 0x7e94 741 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c 742 743 #define AVIVO_DC_I2C_STATUS1 0x7d30 744 # define AVIVO_DC_I2C_DONE (1 << 0) 745 # define AVIVO_DC_I2C_NACK (1 << 1) 746 # define AVIVO_DC_I2C_HALT (1 << 2) 747 # define AVIVO_DC_I2C_GO (1 << 3) 748 #define AVIVO_DC_I2C_RESET 0x7d34 749 # define AVIVO_DC_I2C_SOFT_RESET (1 << 0) 750 # define AVIVO_DC_I2C_ABORT (1 << 8) 751 #define AVIVO_DC_I2C_CONTROL1 0x7d38 752 # define AVIVO_DC_I2C_START (1 << 0) 753 # define AVIVO_DC_I2C_STOP (1 << 1) 754 # define AVIVO_DC_I2C_RECEIVE (1 << 2) 755 # define AVIVO_DC_I2C_EN (1 << 8) 756 # define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) 757 # define AVIVO_SEL_DDC1 0 758 # define AVIVO_SEL_DDC2 1 759 # define AVIVO_SEL_DDC3 2 760 #define AVIVO_DC_I2C_CONTROL2 0x7d3c 761 # define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) 762 # define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) 763 #define AVIVO_DC_I2C_CONTROL3 0x7d40 764 # define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) 765 # define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) 766 # define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) 767 # define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) 768 # define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) 769 # define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) 770 #define AVIVO_DC_I2C_DATA 0x7d44 771 #define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 772 # define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) 773 # define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) 774 # define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) 775 #define AVIVO_DC_I2C_ARBITRATION 0x7d50 776 # define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) 777 # define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) 778 # define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) 779 # define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) 780 # define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) 781 # define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) 782 783 #define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 784 #define AVIVO_DC_GPIO_DDC1_A 0x7e44 785 #define AVIVO_DC_GPIO_DDC1_EN 0x7e48 786 #define AVIVO_DC_GPIO_DDC1_Y 0x7e4c 787 788 #define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 789 #define AVIVO_DC_GPIO_DDC2_A 0x7e54 790 #define AVIVO_DC_GPIO_DDC2_EN 0x7e58 791 #define AVIVO_DC_GPIO_DDC2_Y 0x7e5c 792 793 #define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 794 #define AVIVO_DC_GPIO_DDC3_A 0x7e64 795 #define AVIVO_DC_GPIO_DDC3_EN 0x7e68 796 #define AVIVO_DC_GPIO_DDC3_Y 0x7e6c 797 798 #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc 799 # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) 800 # define AVIVO_D2_VBLANK_INTERRUPT (1 << 5) 801 802 #endif 803