1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2006 ATMEL 4 * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Device Port (UDP) register definition, based on "AT91RM9200.h" provided 31 * by ATMEL. 32 */ 33 34 #ifndef _AT9100_DCI_H_ 35 #define _AT9100_DCI_H_ 36 37 #define AT91_MAX_DEVICES (USB_MIN_DEVICES + 1) 38 39 #define AT91_UDP_FRM 0x00 /* Frame number register */ 40 #define AT91_UDP_FRM_MASK (0x7FF << 0) /* Frame Number as Defined in 41 * the Packet Field Formats */ 42 #define AT91_UDP_FRM_ERR (0x1 << 16) /* Frame Error */ 43 #define AT91_UDP_FRM_OK (0x1 << 17) /* Frame OK */ 44 45 #define AT91_UDP_GSTATE 0x04 /* Global state register */ 46 #define AT91_UDP_GSTATE_ADDR (0x1 << 0) /* Addressed state */ 47 #define AT91_UDP_GSTATE_CONFG (0x1 << 1) /* Configured */ 48 #define AT91_UDP_GSTATE_ESR (0x1 << 2) /* Enable Send Resume */ 49 #define AT91_UDP_GSTATE_RSM (0x1 << 3) /* A Resume Has Been Sent to 50 * the Host */ 51 #define AT91_UDP_GSTATE_RMW (0x1 << 4) /* Remote Wake Up Enable */ 52 53 #define AT91_UDP_FADDR 0x08 /* Function Address Register */ 54 #define AT91_UDP_FADDR_MASK (0x7F << 0)/* Function Address Mask */ 55 #define AT91_UDP_FADDR_EN (0x1 << 8)/* Function Enable */ 56 57 #define AT91_UDP_RES0 0x0C /* Reserved 0 */ 58 59 #define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ 60 #define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ 61 #define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ 62 #define AT91_UDP_ISR 0x1C /* Interrupt Status Register */ 63 #define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ 64 #define AT91_UDP_INT_EP(n) (0x1 <<(n))/* Endpoint "n" Interrupt */ 65 #define AT91_UDP_INT_RXSUSP (0x1 << 8)/* USB Suspend Interrupt */ 66 #define AT91_UDP_INT_RXRSM (0x1 << 9)/* USB Resume Interrupt */ 67 #define AT91_UDP_INT_EXTRSM (0x1 << 10)/* USB External Resume Interrupt */ 68 #define AT91_UDP_INT_SOFINT (0x1 << 11)/* USB Start Of frame Interrupt */ 69 #define AT91_UDP_INT_END_BR (0x1 << 12)/* USB End Of Bus Reset Interrupt */ 70 #define AT91_UDP_INT_WAKEUP (0x1 << 13)/* USB Resume Interrupt */ 71 72 #define AT91_UDP_INT_BUS \ 73 (AT91_UDP_INT_RXSUSP|AT91_UDP_INT_RXRSM| \ 74 AT91_UDP_INT_END_BR) 75 76 #define AT91_UDP_INT_EPS \ 77 (AT91_UDP_INT_EP(0)|AT91_UDP_INT_EP(1)| \ 78 AT91_UDP_INT_EP(2)|AT91_UDP_INT_EP(3)| \ 79 AT91_UDP_INT_EP(4)|AT91_UDP_INT_EP(5)) 80 81 #define AT91_UDP_INT_DEFAULT \ 82 (AT91_UDP_INT_EPS|AT91_UDP_INT_BUS) 83 84 #define AT91_UDP_RES1 0x24 /* Reserved 1 */ 85 #define AT91_UDP_RST 0x28 /* Reset Endpoint Register */ 86 #define AT91_UDP_RST_EP(n) (0x1 << (n))/* Reset Endpoint "n" */ 87 88 #define AT91_UDP_RES2 0x2C /* Reserved 2 */ 89 90 #define AT91_UDP_CSR(n) (0x30 + (4*(n)))/* Endpoint Control and Status 91 * Register */ 92 #define AT91_UDP_CSR_TXCOMP (0x1 << 0) /* Generates an IN packet with data 93 * previously written in the DPR */ 94 #define AT91_UDP_CSR_RX_DATA_BK0 (0x1 << 1) /* Receive Data Bank 0 */ 95 #define AT91_UDP_CSR_RXSETUP (0x1 << 2) /* Sends STALL to the Host 96 * (Control endpoints) */ 97 #define AT91_UDP_CSR_ISOERROR (0x1 << 3) /* Isochronous error 98 * (Isochronous endpoints) */ 99 #define AT91_UDP_CSR_STALLSENT (0x1 << 3) /* Stall sent (Control, bulk, 100 * interrupt endpoints) */ 101 #define AT91_UDP_CSR_TXPKTRDY (0x1 << 4) /* Transmit Packet Ready */ 102 #define AT91_UDP_CSR_FORCESTALL (0x1 << 5) /* Force Stall (used by 103 * Control, Bulk and 104 * Isochronous endpoints). */ 105 #define AT91_UDP_CSR_RX_DATA_BK1 (0x1 << 6) /* Receive Data Bank 1 (only 106 * used by endpoints with 107 * ping-pong attributes). */ 108 #define AT91_UDP_CSR_DIR (0x1 << 7) /* Transfer Direction */ 109 #define AT91_UDP_CSR_ET_MASK (0x7 << 8) /* Endpoint transfer type mask */ 110 #define AT91_UDP_CSR_ET_CTRL (0x0 << 8) /* Control IN+OUT */ 111 #define AT91_UDP_CSR_ET_ISO (0x1 << 8) /* Isochronous */ 112 #define AT91_UDP_CSR_ET_BULK (0x2 << 8) /* Bulk */ 113 #define AT91_UDP_CSR_ET_INT (0x3 << 8) /* Interrupt */ 114 #define AT91_UDP_CSR_ET_DIR_OUT (0x0 << 8) /* OUT tokens */ 115 #define AT91_UDP_CSR_ET_DIR_IN (0x4 << 8) /* IN tokens */ 116 #define AT91_UDP_CSR_DTGLE (0x1 << 11) /* Data Toggle */ 117 #define AT91_UDP_CSR_EPEDS (0x1 << 15) /* Endpoint Enable Disable */ 118 #define AT91_UDP_CSR_RXBYTECNT (0x7FF << 16) /* Number Of Bytes Available 119 * in the FIFO */ 120 121 #define AT91_UDP_FDR(n) (0x50 + (4*(n)))/* Endpoint FIFO Data Register */ 122 #define AT91_UDP_RES3 0x70 /* Reserved 3 */ 123 #define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ 124 #define AT91_UDP_TXVC_DIS (0x1 << 8) 125 126 #define AT91_UDP_EP_MAX 6 /* maximum number of endpoints 127 * supported */ 128 129 #define AT91_UDP_READ_4(sc, reg) \ 130 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 131 132 #define AT91_UDP_WRITE_4(sc, reg, data) \ 133 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 134 135 struct at91dci_td; 136 struct at91dci_softc; 137 138 typedef uint8_t (at91dci_cmd_t)(struct at91dci_softc *sc, struct at91dci_td *td); 139 140 struct at91dci_td { 141 struct at91dci_td *obj_next; 142 at91dci_cmd_t *func; 143 struct usb_page_cache *pc; 144 uint32_t offset; 145 uint32_t remainder; 146 uint16_t max_packet_size; 147 uint8_t status_reg; 148 uint8_t fifo_reg; 149 uint8_t fifo_bank:1; 150 uint8_t error:1; 151 uint8_t alt_next:1; 152 uint8_t short_pkt:1; 153 uint8_t support_multi_buffer:1; 154 uint8_t did_stall:1; 155 }; 156 157 struct at91dci_std_temp { 158 at91dci_cmd_t *func; 159 struct usb_page_cache *pc; 160 struct at91dci_td *td; 161 struct at91dci_td *td_next; 162 uint32_t len; 163 uint32_t offset; 164 uint16_t max_frame_size; 165 uint8_t short_pkt; 166 /* 167 * short_pkt = 0: transfer should be short terminated 168 * short_pkt = 1: transfer should not be short terminated 169 */ 170 uint8_t setup_alt_next; 171 uint8_t did_stall; 172 }; 173 174 struct at91dci_config_desc { 175 struct usb_config_descriptor confd; 176 struct usb_interface_descriptor ifcd; 177 struct usb_endpoint_descriptor endpd; 178 } __packed; 179 180 union at91dci_hub_temp { 181 uWord wValue; 182 struct usb_port_status ps; 183 }; 184 185 struct at91dci_ep_flags { 186 uint8_t fifo_bank:1; /* hardware specific */ 187 }; 188 189 struct at91dci_flags { 190 uint8_t change_connect:1; 191 uint8_t change_suspend:1; 192 uint8_t status_suspend:1; /* set if suspended */ 193 uint8_t status_vbus:1; /* set if present */ 194 uint8_t status_bus_reset:1; /* set if reset complete */ 195 uint8_t remote_wakeup:1; 196 uint8_t self_powered:1; 197 uint8_t clocks_off:1; 198 uint8_t port_powered:1; 199 uint8_t port_enabled:1; 200 uint8_t d_pulled_up:1; 201 }; 202 203 struct at91dci_softc { 204 struct usb_bus sc_bus; 205 union at91dci_hub_temp sc_hub_temp; 206 207 struct usb_device *sc_devices[AT91_MAX_DEVICES]; 208 struct resource *sc_io_res; 209 struct resource *sc_irq_res; 210 void *sc_intr_hdl; 211 bus_size_t sc_io_size; 212 bus_space_tag_t sc_io_tag; 213 bus_space_handle_t sc_io_hdl; 214 215 void (*sc_clocks_on) (void *arg); 216 void (*sc_clocks_off) (void *arg); 217 void *sc_clocks_arg; 218 219 void (*sc_pull_up) (void *arg); 220 void (*sc_pull_down) (void *arg); 221 void *sc_pull_arg; 222 223 uint32_t sc_xfer_complete; 224 225 uint8_t sc_rt_addr; /* root HUB address */ 226 uint8_t sc_dv_addr; /* device address */ 227 uint8_t sc_conf; /* root HUB config */ 228 229 uint8_t sc_hub_idata[1]; 230 231 struct at91dci_flags sc_flags; 232 struct at91dci_ep_flags sc_ep_flags[AT91_UDP_EP_MAX]; 233 }; 234 235 /* prototypes */ 236 237 usb_error_t at91dci_init(struct at91dci_softc *sc); 238 void at91dci_uninit(struct at91dci_softc *sc); 239 driver_filter_t at91dci_filter_interrupt; 240 driver_intr_t at91dci_interrupt; 241 void at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on); 242 243 #endif /* _AT9100_DCI_H_ */ 244