1 /* $FreeBSD$ */
2 /*-
3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
4 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
5 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * USB Universal Host Controller driver.
31 * Handles e.g. PIIX3 and PIIX4.
32 *
33 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
34 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
35 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
36 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
37 */
38
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
41 #else
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/module.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
55 #include <sys/sx.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
59 #include <sys/priv.h>
60
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63
64 #define USB_DEBUG_VAR uhcidebug
65
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
74
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
78
79 #include <dev/usb/controller/uhci.h>
80 #include <dev/usb/controller/uhcireg.h>
81
82 #define alt_next next
83 #define UHCI_BUS2SC(bus) \
84 ((uhci_softc_t *)(((uint8_t *)(bus)) - \
85 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus))))
86
87 #ifdef USB_DEBUG
88 static int uhcidebug = 0;
89 static int uhcinoloop = 0;
90
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci");
92 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN,
93 &uhcidebug, 0, "uhci debug level");
94 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN,
95 &uhcinoloop, 0, "uhci noloop");
96
97 static void uhci_dumpregs(uhci_softc_t *sc);
98 static void uhci_dump_tds(uhci_td_t *td);
99
100 #endif
101
102 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
103 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
104 #define UWRITE1(sc, r, x) \
105 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
106 } while (/*CONSTCOND*/0)
107 #define UWRITE2(sc, r, x) \
108 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
109 } while (/*CONSTCOND*/0)
110 #define UWRITE4(sc, r, x) \
111 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
112 } while (/*CONSTCOND*/0)
113 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
114 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
115 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
116
117 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
118 #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
119
120 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
121
122 #define UHCI_INTR_ENDPT 1
123
124 struct uhci_mem_layout {
125
126 struct usb_page_search buf_res;
127 struct usb_page_search fix_res;
128
129 struct usb_page_cache *buf_pc;
130 struct usb_page_cache *fix_pc;
131
132 uint32_t buf_offset;
133
134 uint16_t max_frame_size;
135 };
136
137 struct uhci_std_temp {
138
139 struct uhci_mem_layout ml;
140 uhci_td_t *td;
141 uhci_td_t *td_next;
142 uint32_t average;
143 uint32_t td_status;
144 uint32_t td_token;
145 uint32_t len;
146 uint16_t max_frame_size;
147 uint8_t shortpkt;
148 uint8_t setup_alt_next;
149 uint8_t last_frame;
150 };
151
152 static const struct usb_bus_methods uhci_bus_methods;
153 static const struct usb_pipe_methods uhci_device_bulk_methods;
154 static const struct usb_pipe_methods uhci_device_ctrl_methods;
155 static const struct usb_pipe_methods uhci_device_intr_methods;
156 static const struct usb_pipe_methods uhci_device_isoc_methods;
157
158 static uint8_t uhci_restart(uhci_softc_t *sc);
159 static void uhci_do_poll(struct usb_bus *);
160 static void uhci_device_done(struct usb_xfer *, usb_error_t);
161 static void uhci_transfer_intr_enqueue(struct usb_xfer *);
162 static void uhci_timeout(void *);
163 static uint8_t uhci_check_transfer(struct usb_xfer *);
164 static void uhci_root_intr(uhci_softc_t *sc);
165
166 void
uhci_iterate_hw_softc(struct usb_bus * bus,usb_bus_mem_sub_cb_t * cb)167 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
168 {
169 struct uhci_softc *sc = UHCI_BUS2SC(bus);
170 uint32_t i;
171
172 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
173 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN);
174
175 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg,
176 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
177
178 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg,
179 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
180
181 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
182 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
183
184 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg,
185 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
186
187 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg,
188 sizeof(uhci_td_t), UHCI_TD_ALIGN);
189
190 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) {
191 cb(bus, sc->sc_hw.isoc_start_pc + i,
192 sc->sc_hw.isoc_start_pg + i,
193 sizeof(uhci_td_t), UHCI_TD_ALIGN);
194 }
195
196 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) {
197 cb(bus, sc->sc_hw.intr_start_pc + i,
198 sc->sc_hw.intr_start_pg + i,
199 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
200 }
201 }
202
203 static void
uhci_mem_layout_init(struct uhci_mem_layout * ml,struct usb_xfer * xfer)204 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
205 {
206 ml->buf_pc = xfer->frbuffers + 0;
207 ml->fix_pc = xfer->buf_fixup;
208
209 ml->buf_offset = 0;
210
211 ml->max_frame_size = xfer->max_frame_size;
212 }
213
214 static void
uhci_mem_layout_fixup(struct uhci_mem_layout * ml,struct uhci_td * td)215 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
216 {
217 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res);
218
219 if (ml->buf_res.length < td->len) {
220
221 /* need to do a fixup */
222
223 usbd_get_page(ml->fix_pc, 0, &ml->fix_res);
224
225 td->td_buffer = htole32(ml->fix_res.physaddr);
226
227 /*
228 * The UHCI driver cannot handle
229 * page crossings, so a fixup is
230 * needed:
231 *
232 * +----+----+ - - -
233 * | YYY|Y |
234 * +----+----+ - - -
235 * \ \
236 * \ \
237 * +----+
238 * |YYYY| (fixup)
239 * +----+
240 */
241
242 if ((td->td_token & htole32(UHCI_TD_PID)) ==
243 htole32(UHCI_TD_PID_IN)) {
244 td->fix_pc = ml->fix_pc;
245 usb_pc_cpu_invalidate(ml->fix_pc);
246
247 } else {
248 td->fix_pc = NULL;
249
250 /* copy data to fixup location */
251
252 usbd_copy_out(ml->buf_pc, ml->buf_offset,
253 ml->fix_res.buffer, td->len);
254
255 usb_pc_cpu_flush(ml->fix_pc);
256 }
257
258 /* prepare next fixup */
259
260 ml->fix_pc++;
261
262 } else {
263
264 td->td_buffer = htole32(ml->buf_res.physaddr);
265 td->fix_pc = NULL;
266 }
267
268 /* prepare next data location */
269
270 ml->buf_offset += td->len;
271 }
272
273 /*
274 * Return values:
275 * 0: Success
276 * Else: Failure
277 */
278 static uint8_t
uhci_restart(uhci_softc_t * sc)279 uhci_restart(uhci_softc_t *sc)
280 {
281 struct usb_page_search buf_res;
282
283 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
284
285 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) {
286 DPRINTFN(2, "Already started\n");
287 return (0);
288 }
289
290 DPRINTFN(2, "Restarting\n");
291
292 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
293
294 /* Reload fresh base address */
295 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr);
296
297 /*
298 * Assume 64 byte packets at frame end and start HC controller:
299 */
300 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
301
302 /* wait 10 milliseconds */
303
304 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
305
306 /* check that controller has started */
307
308 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
309 DPRINTFN(2, "Failed\n");
310 return (1);
311 }
312 return (0);
313 }
314
315 void
uhci_reset(uhci_softc_t * sc)316 uhci_reset(uhci_softc_t *sc)
317 {
318 uint16_t n;
319
320 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
321
322 DPRINTF("resetting the HC\n");
323
324 /* disable interrupts */
325
326 UWRITE2(sc, UHCI_INTR, 0);
327
328 /* global reset */
329
330 UHCICMD(sc, UHCI_CMD_GRESET);
331
332 /* wait */
333
334 usb_pause_mtx(&sc->sc_bus.bus_mtx,
335 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY));
336
337 /* terminate all transfers */
338
339 UHCICMD(sc, UHCI_CMD_HCRESET);
340
341 /* the reset bit goes low when the controller is done */
342
343 n = UHCI_RESET_TIMEOUT;
344 while (n--) {
345 /* wait one millisecond */
346
347 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
348
349 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
350 goto done_1;
351 }
352 }
353
354 device_printf(sc->sc_bus.bdev,
355 "controller did not reset\n");
356
357 done_1:
358
359 n = 10;
360 while (n--) {
361 /* wait one millisecond */
362
363 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
364
365 /* check if HC is stopped */
366 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
367 goto done_2;
368 }
369 }
370
371 device_printf(sc->sc_bus.bdev,
372 "controller did not stop\n");
373
374 done_2:
375
376 /* reset frame number */
377 UWRITE2(sc, UHCI_FRNUM, 0);
378 /* set default SOF value */
379 UWRITE1(sc, UHCI_SOF, 0x40);
380
381 USB_BUS_UNLOCK(&sc->sc_bus);
382
383 /* stop root interrupt */
384 usb_callout_drain(&sc->sc_root_intr);
385
386 USB_BUS_LOCK(&sc->sc_bus);
387 }
388
389 static void
uhci_start(uhci_softc_t * sc)390 uhci_start(uhci_softc_t *sc)
391 {
392 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
393
394 DPRINTFN(2, "enabling\n");
395
396 /* enable interrupts */
397
398 UWRITE2(sc, UHCI_INTR,
399 (UHCI_INTR_TOCRCIE |
400 UHCI_INTR_RIE |
401 UHCI_INTR_IOCE |
402 UHCI_INTR_SPIE));
403
404 if (uhci_restart(sc)) {
405 device_printf(sc->sc_bus.bdev,
406 "cannot start HC controller\n");
407 }
408
409 /* start root interrupt */
410 uhci_root_intr(sc);
411 }
412
413 static struct uhci_qh *
uhci_init_qh(struct usb_page_cache * pc)414 uhci_init_qh(struct usb_page_cache *pc)
415 {
416 struct usb_page_search buf_res;
417 struct uhci_qh *qh;
418
419 usbd_get_page(pc, 0, &buf_res);
420
421 qh = buf_res.buffer;
422
423 qh->qh_self =
424 htole32(buf_res.physaddr) |
425 htole32(UHCI_PTR_QH);
426
427 qh->page_cache = pc;
428
429 return (qh);
430 }
431
432 static struct uhci_td *
uhci_init_td(struct usb_page_cache * pc)433 uhci_init_td(struct usb_page_cache *pc)
434 {
435 struct usb_page_search buf_res;
436 struct uhci_td *td;
437
438 usbd_get_page(pc, 0, &buf_res);
439
440 td = buf_res.buffer;
441
442 td->td_self =
443 htole32(buf_res.physaddr) |
444 htole32(UHCI_PTR_TD);
445
446 td->page_cache = pc;
447
448 return (td);
449 }
450
451 usb_error_t
uhci_init(uhci_softc_t * sc)452 uhci_init(uhci_softc_t *sc)
453 {
454 uint16_t bit;
455 uint16_t x;
456 uint16_t y;
457
458 DPRINTF("start\n");
459
460 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0);
461
462 #ifdef USB_DEBUG
463 if (uhcidebug > 2) {
464 uhci_dumpregs(sc);
465 }
466 #endif
467 /*
468 * Setup QH's
469 */
470 sc->sc_ls_ctl_p_last =
471 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc);
472
473 sc->sc_fs_ctl_p_last =
474 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc);
475
476 sc->sc_bulk_p_last =
477 uhci_init_qh(&sc->sc_hw.bulk_start_pc);
478 #if 0
479 sc->sc_reclaim_qh_p =
480 sc->sc_fs_ctl_p_last;
481 #else
482 /* setup reclaim looping point */
483 sc->sc_reclaim_qh_p =
484 sc->sc_bulk_p_last;
485 #endif
486
487 sc->sc_last_qh_p =
488 uhci_init_qh(&sc->sc_hw.last_qh_pc);
489
490 sc->sc_last_td_p =
491 uhci_init_td(&sc->sc_hw.last_td_pc);
492
493 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
494 sc->sc_isoc_p_last[x] =
495 uhci_init_td(sc->sc_hw.isoc_start_pc + x);
496 }
497
498 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) {
499 sc->sc_intr_p_last[x] =
500 uhci_init_qh(sc->sc_hw.intr_start_pc + x);
501 }
502
503 /*
504 * the QHs are arranged to give poll intervals that are
505 * powers of 2 times 1ms
506 */
507 bit = UHCI_IFRAMELIST_COUNT / 2;
508 while (bit) {
509 x = bit;
510 while (x & bit) {
511 uhci_qh_t *qh_x;
512 uhci_qh_t *qh_y;
513
514 y = (x ^ bit) | (bit / 2);
515
516 /*
517 * the next QH has half the poll interval
518 */
519 qh_x = sc->sc_intr_p_last[x];
520 qh_y = sc->sc_intr_p_last[y];
521
522 qh_x->h_next = NULL;
523 qh_x->qh_h_next = qh_y->qh_self;
524 qh_x->e_next = NULL;
525 qh_x->qh_e_next = htole32(UHCI_PTR_T);
526 x++;
527 }
528 bit >>= 1;
529 }
530
531 if (1) {
532 uhci_qh_t *qh_ls;
533 uhci_qh_t *qh_intr;
534
535 qh_ls = sc->sc_ls_ctl_p_last;
536 qh_intr = sc->sc_intr_p_last[0];
537
538 /* start QH for interrupt traffic */
539 qh_intr->h_next = qh_ls;
540 qh_intr->qh_h_next = qh_ls->qh_self;
541 qh_intr->e_next = 0;
542 qh_intr->qh_e_next = htole32(UHCI_PTR_T);
543 }
544 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
545
546 uhci_td_t *td_x;
547 uhci_qh_t *qh_intr;
548
549 td_x = sc->sc_isoc_p_last[x];
550 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)];
551
552 /* start TD for isochronous traffic */
553 td_x->next = NULL;
554 td_x->td_next = qh_intr->qh_self;
555 td_x->td_status = htole32(UHCI_TD_IOS);
556 td_x->td_token = htole32(0);
557 td_x->td_buffer = htole32(0);
558 }
559
560 if (1) {
561 uhci_qh_t *qh_ls;
562 uhci_qh_t *qh_fs;
563
564 qh_ls = sc->sc_ls_ctl_p_last;
565 qh_fs = sc->sc_fs_ctl_p_last;
566
567 /* start QH where low speed control traffic will be queued */
568 qh_ls->h_next = qh_fs;
569 qh_ls->qh_h_next = qh_fs->qh_self;
570 qh_ls->e_next = 0;
571 qh_ls->qh_e_next = htole32(UHCI_PTR_T);
572 }
573 if (1) {
574 uhci_qh_t *qh_ctl;
575 uhci_qh_t *qh_blk;
576 uhci_qh_t *qh_lst;
577 uhci_td_t *td_lst;
578
579 qh_ctl = sc->sc_fs_ctl_p_last;
580 qh_blk = sc->sc_bulk_p_last;
581
582 /* start QH where full speed control traffic will be queued */
583 qh_ctl->h_next = qh_blk;
584 qh_ctl->qh_h_next = qh_blk->qh_self;
585 qh_ctl->e_next = 0;
586 qh_ctl->qh_e_next = htole32(UHCI_PTR_T);
587
588 qh_lst = sc->sc_last_qh_p;
589
590 /* start QH where bulk traffic will be queued */
591 qh_blk->h_next = qh_lst;
592 qh_blk->qh_h_next = qh_lst->qh_self;
593 qh_blk->e_next = 0;
594 qh_blk->qh_e_next = htole32(UHCI_PTR_T);
595
596 td_lst = sc->sc_last_td_p;
597
598 /* end QH which is used for looping the QHs */
599 qh_lst->h_next = 0;
600 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */
601 qh_lst->e_next = td_lst;
602 qh_lst->qh_e_next = td_lst->td_self;
603
604 /*
605 * end TD which hangs from the last QH, to avoid a bug in the PIIX
606 * that makes it run berserk otherwise
607 */
608 td_lst->next = 0;
609 td_lst->td_next = htole32(UHCI_PTR_T);
610 td_lst->td_status = htole32(0); /* inactive */
611 td_lst->td_token = htole32(0);
612 td_lst->td_buffer = htole32(0);
613 }
614 if (1) {
615 struct usb_page_search buf_res;
616 uint32_t *pframes;
617
618 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
619
620 pframes = buf_res.buffer;
621
622
623 /*
624 * Setup UHCI framelist
625 *
626 * Execution order:
627 *
628 * pframes -> full speed isochronous -> interrupt QH's -> low
629 * speed control -> full speed control -> bulk transfers
630 *
631 */
632
633 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) {
634 pframes[x] =
635 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self;
636 }
637 }
638 /* flush all cache into memory */
639
640 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc);
641
642 /* set up the bus struct */
643 sc->sc_bus.methods = &uhci_bus_methods;
644
645 USB_BUS_LOCK(&sc->sc_bus);
646 /* reset the controller */
647 uhci_reset(sc);
648
649 /* start the controller */
650 uhci_start(sc);
651 USB_BUS_UNLOCK(&sc->sc_bus);
652
653 /* catch lost interrupts */
654 uhci_do_poll(&sc->sc_bus);
655
656 return (0);
657 }
658
659 static void
uhci_suspend(uhci_softc_t * sc)660 uhci_suspend(uhci_softc_t *sc)
661 {
662 #ifdef USB_DEBUG
663 if (uhcidebug > 2) {
664 uhci_dumpregs(sc);
665 }
666 #endif
667
668 USB_BUS_LOCK(&sc->sc_bus);
669
670 /* stop the controller */
671
672 uhci_reset(sc);
673
674 /* enter global suspend */
675
676 UHCICMD(sc, UHCI_CMD_EGSM);
677
678 USB_BUS_UNLOCK(&sc->sc_bus);
679 }
680
681 static void
uhci_resume(uhci_softc_t * sc)682 uhci_resume(uhci_softc_t *sc)
683 {
684 USB_BUS_LOCK(&sc->sc_bus);
685
686 /* reset the controller */
687
688 uhci_reset(sc);
689
690 /* force global resume */
691
692 UHCICMD(sc, UHCI_CMD_FGR);
693
694 /* and start traffic again */
695
696 uhci_start(sc);
697
698 USB_BUS_UNLOCK(&sc->sc_bus);
699
700 #ifdef USB_DEBUG
701 if (uhcidebug > 2)
702 uhci_dumpregs(sc);
703 #endif
704
705 /* catch lost interrupts */
706 uhci_do_poll(&sc->sc_bus);
707 }
708
709 #ifdef USB_DEBUG
710 static void
uhci_dumpregs(uhci_softc_t * sc)711 uhci_dumpregs(uhci_softc_t *sc)
712 {
713 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
714 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
715 device_get_nameunit(sc->sc_bus.bdev),
716 UREAD2(sc, UHCI_CMD),
717 UREAD2(sc, UHCI_STS),
718 UREAD2(sc, UHCI_INTR),
719 UREAD2(sc, UHCI_FRNUM),
720 UREAD4(sc, UHCI_FLBASEADDR),
721 UREAD1(sc, UHCI_SOF),
722 UREAD2(sc, UHCI_PORTSC1),
723 UREAD2(sc, UHCI_PORTSC2));
724 }
725
726 static uint8_t
uhci_dump_td(uhci_td_t * p)727 uhci_dump_td(uhci_td_t *p)
728 {
729 uint32_t td_next;
730 uint32_t td_status;
731 uint32_t td_token;
732 uint8_t temp;
733
734 usb_pc_cpu_invalidate(p->page_cache);
735
736 td_next = le32toh(p->td_next);
737 td_status = le32toh(p->td_status);
738 td_token = le32toh(p->td_token);
739
740 /*
741 * Check whether the link pointer in this TD marks the link pointer
742 * as end of queue:
743 */
744 temp = ((td_next & UHCI_PTR_T) || (td_next == 0));
745
746 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x "
747 "token=0x%08x buffer=0x%08x\n",
748 p,
749 le32toh(p->td_self),
750 td_next,
751 td_status,
752 td_token,
753 le32toh(p->td_buffer));
754
755 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x,"
756 "addr=%d,endpt=%d,D=%d,maxlen=%d\n",
757 p,
758 (td_next & 1) ? "-T" : "",
759 (td_next & 2) ? "-Q" : "",
760 (td_next & 4) ? "-VF" : "",
761 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "",
762 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "",
763 (td_status & UHCI_TD_NAK) ? "-NAK" : "",
764 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "",
765 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "",
766 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "",
767 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "",
768 (td_status & UHCI_TD_IOC) ? "-IOC" : "",
769 (td_status & UHCI_TD_IOS) ? "-IOS" : "",
770 (td_status & UHCI_TD_LS) ? "-LS" : "",
771 (td_status & UHCI_TD_SPD) ? "-SPD" : "",
772 UHCI_TD_GET_ERRCNT(td_status),
773 UHCI_TD_GET_ACTLEN(td_status),
774 UHCI_TD_GET_PID(td_token),
775 UHCI_TD_GET_DEVADDR(td_token),
776 UHCI_TD_GET_ENDPT(td_token),
777 UHCI_TD_GET_DT(td_token),
778 UHCI_TD_GET_MAXLEN(td_token));
779
780 return (temp);
781 }
782
783 static uint8_t
uhci_dump_qh(uhci_qh_t * sqh)784 uhci_dump_qh(uhci_qh_t *sqh)
785 {
786 uint8_t temp;
787 uint32_t qh_h_next;
788 uint32_t qh_e_next;
789
790 usb_pc_cpu_invalidate(sqh->page_cache);
791
792 qh_h_next = le32toh(sqh->qh_h_next);
793 qh_e_next = le32toh(sqh->qh_e_next);
794
795 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh,
796 le32toh(sqh->qh_self), qh_h_next, qh_e_next);
797
798 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) |
799 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0));
800
801 return (temp);
802 }
803
804 static void
uhci_dump_all(uhci_softc_t * sc)805 uhci_dump_all(uhci_softc_t *sc)
806 {
807 uhci_dumpregs(sc);
808 uhci_dump_qh(sc->sc_ls_ctl_p_last);
809 uhci_dump_qh(sc->sc_fs_ctl_p_last);
810 uhci_dump_qh(sc->sc_bulk_p_last);
811 uhci_dump_qh(sc->sc_last_qh_p);
812 }
813
814 static void
uhci_dump_tds(uhci_td_t * td)815 uhci_dump_tds(uhci_td_t *td)
816 {
817 for (;
818 td != NULL;
819 td = td->obj_next) {
820 if (uhci_dump_td(td)) {
821 break;
822 }
823 }
824 }
825
826 #endif
827
828 /*
829 * Let the last QH loop back to the full speed control transfer QH.
830 * This is what intel calls "bandwidth reclamation" and improves
831 * USB performance a lot for some devices.
832 * If we are already looping, just count it.
833 */
834 static void
uhci_add_loop(uhci_softc_t * sc)835 uhci_add_loop(uhci_softc_t *sc)
836 {
837 struct uhci_qh *qh_lst;
838 struct uhci_qh *qh_rec;
839
840 #ifdef USB_DEBUG
841 if (uhcinoloop) {
842 return;
843 }
844 #endif
845 if (++(sc->sc_loops) == 1) {
846 DPRINTFN(6, "add\n");
847
848 qh_lst = sc->sc_last_qh_p;
849 qh_rec = sc->sc_reclaim_qh_p;
850
851 /* NOTE: we don't loop back the soft pointer */
852
853 qh_lst->qh_h_next = qh_rec->qh_self;
854 usb_pc_cpu_flush(qh_lst->page_cache);
855 }
856 }
857
858 static void
uhci_rem_loop(uhci_softc_t * sc)859 uhci_rem_loop(uhci_softc_t *sc)
860 {
861 struct uhci_qh *qh_lst;
862
863 #ifdef USB_DEBUG
864 if (uhcinoloop) {
865 return;
866 }
867 #endif
868 if (--(sc->sc_loops) == 0) {
869 DPRINTFN(6, "remove\n");
870
871 qh_lst = sc->sc_last_qh_p;
872 qh_lst->qh_h_next = htole32(UHCI_PTR_T);
873 usb_pc_cpu_flush(qh_lst->page_cache);
874 }
875 }
876
877 static void
uhci_transfer_intr_enqueue(struct usb_xfer * xfer)878 uhci_transfer_intr_enqueue(struct usb_xfer *xfer)
879 {
880 /* check for early completion */
881 if (uhci_check_transfer(xfer)) {
882 return;
883 }
884 /* put transfer on interrupt queue */
885 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
886
887 /* start timeout, if any */
888 if (xfer->timeout != 0) {
889 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout);
890 }
891 }
892
893 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last)
894 static uhci_td_t *
_uhci_append_td(uhci_td_t * std,uhci_td_t * last)895 _uhci_append_td(uhci_td_t *std, uhci_td_t *last)
896 {
897 DPRINTFN(11, "%p to %p\n", std, last);
898
899 /* (sc->sc_bus.mtx) must be locked */
900
901 std->next = last->next;
902 std->td_next = last->td_next;
903
904 std->prev = last;
905
906 usb_pc_cpu_flush(std->page_cache);
907
908 /*
909 * the last->next->prev is never followed: std->next->prev = std;
910 */
911 last->next = std;
912 last->td_next = std->td_self;
913
914 usb_pc_cpu_flush(last->page_cache);
915
916 return (std);
917 }
918
919 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last)
920 static uhci_qh_t *
_uhci_append_qh(uhci_qh_t * sqh,uhci_qh_t * last)921 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
922 {
923 DPRINTFN(11, "%p to %p\n", sqh, last);
924
925 if (sqh->h_prev != NULL) {
926 /* should not happen */
927 DPRINTFN(0, "QH already linked!\n");
928 return (last);
929 }
930 /* (sc->sc_bus.mtx) must be locked */
931
932 sqh->h_next = last->h_next;
933 sqh->qh_h_next = last->qh_h_next;
934
935 sqh->h_prev = last;
936
937 usb_pc_cpu_flush(sqh->page_cache);
938
939 /*
940 * The "last->h_next->h_prev" is never followed:
941 *
942 * "sqh->h_next->h_prev" = sqh;
943 */
944
945 last->h_next = sqh;
946 last->qh_h_next = sqh->qh_self;
947
948 usb_pc_cpu_flush(last->page_cache);
949
950 return (sqh);
951 }
952
953 /**/
954
955 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last)
956 static uhci_td_t *
_uhci_remove_td(uhci_td_t * std,uhci_td_t * last)957 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
958 {
959 DPRINTFN(11, "%p from %p\n", std, last);
960
961 /* (sc->sc_bus.mtx) must be locked */
962
963 std->prev->next = std->next;
964 std->prev->td_next = std->td_next;
965
966 usb_pc_cpu_flush(std->prev->page_cache);
967
968 if (std->next) {
969 std->next->prev = std->prev;
970 usb_pc_cpu_flush(std->next->page_cache);
971 }
972 return ((last == std) ? std->prev : last);
973 }
974
975 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last)
976 static uhci_qh_t *
_uhci_remove_qh(uhci_qh_t * sqh,uhci_qh_t * last)977 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
978 {
979 DPRINTFN(11, "%p from %p\n", sqh, last);
980
981 /* (sc->sc_bus.mtx) must be locked */
982
983 /* only remove if not removed from a queue */
984 if (sqh->h_prev) {
985
986 sqh->h_prev->h_next = sqh->h_next;
987 sqh->h_prev->qh_h_next = sqh->qh_h_next;
988
989 usb_pc_cpu_flush(sqh->h_prev->page_cache);
990
991 if (sqh->h_next) {
992 sqh->h_next->h_prev = sqh->h_prev;
993 usb_pc_cpu_flush(sqh->h_next->page_cache);
994 }
995 last = ((last == sqh) ? sqh->h_prev : last);
996
997 sqh->h_prev = 0;
998
999 usb_pc_cpu_flush(sqh->page_cache);
1000 }
1001 return (last);
1002 }
1003
1004 static void
uhci_isoc_done(uhci_softc_t * sc,struct usb_xfer * xfer)1005 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
1006 {
1007 struct usb_page_search res;
1008 uint32_t nframes = xfer->nframes;
1009 uint32_t status;
1010 uint32_t offset = 0;
1011 uint32_t *plen = xfer->frlengths;
1012 uint16_t len = 0;
1013 uhci_td_t *td = xfer->td_transfer_first;
1014 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos];
1015
1016 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1017 xfer, xfer->endpoint);
1018
1019 /* sync any DMA memory before doing fixups */
1020
1021 usb_bdma_post_sync(xfer);
1022
1023 while (nframes--) {
1024 if (td == NULL) {
1025 panic("%s:%d: out of TD's\n",
1026 __FUNCTION__, __LINE__);
1027 }
1028 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
1029 pp_last = &sc->sc_isoc_p_last[0];
1030 }
1031 #ifdef USB_DEBUG
1032 if (uhcidebug > 5) {
1033 DPRINTF("isoc TD\n");
1034 uhci_dump_td(td);
1035 }
1036 #endif
1037 usb_pc_cpu_invalidate(td->page_cache);
1038 status = le32toh(td->td_status);
1039
1040 len = UHCI_TD_GET_ACTLEN(status);
1041
1042 if (len > *plen) {
1043 len = *plen;
1044 }
1045 if (td->fix_pc) {
1046
1047 usbd_get_page(td->fix_pc, 0, &res);
1048
1049 /* copy data from fixup location to real location */
1050
1051 usb_pc_cpu_invalidate(td->fix_pc);
1052
1053 usbd_copy_in(xfer->frbuffers, offset,
1054 res.buffer, len);
1055 }
1056 offset += *plen;
1057
1058 *plen = len;
1059
1060 /* remove TD from schedule */
1061 UHCI_REMOVE_TD(td, *pp_last);
1062
1063 pp_last++;
1064 plen++;
1065 td = td->obj_next;
1066 }
1067
1068 xfer->aframes = xfer->nframes;
1069 }
1070
1071 static usb_error_t
uhci_non_isoc_done_sub(struct usb_xfer * xfer)1072 uhci_non_isoc_done_sub(struct usb_xfer *xfer)
1073 {
1074 struct usb_page_search res;
1075 uhci_td_t *td;
1076 uhci_td_t *td_alt_next;
1077 uint32_t status;
1078 uint32_t token;
1079 uint16_t len;
1080
1081 td = xfer->td_transfer_cache;
1082 td_alt_next = td->alt_next;
1083
1084 if (xfer->aframes != xfer->nframes) {
1085 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1086 }
1087 while (1) {
1088
1089 usb_pc_cpu_invalidate(td->page_cache);
1090 status = le32toh(td->td_status);
1091 token = le32toh(td->td_token);
1092
1093 /*
1094 * Verify the status and add
1095 * up the actual length:
1096 */
1097
1098 len = UHCI_TD_GET_ACTLEN(status);
1099 if (len > td->len) {
1100 /* should not happen */
1101 DPRINTF("Invalid status length, "
1102 "0x%04x/0x%04x bytes\n", len, td->len);
1103 status |= UHCI_TD_STALLED;
1104
1105 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) {
1106
1107 if (td->fix_pc) {
1108
1109 usbd_get_page(td->fix_pc, 0, &res);
1110
1111 /*
1112 * copy data from fixup location to real
1113 * location
1114 */
1115
1116 usb_pc_cpu_invalidate(td->fix_pc);
1117
1118 usbd_copy_in(xfer->frbuffers + xfer->aframes,
1119 xfer->frlengths[xfer->aframes], res.buffer, len);
1120 }
1121 /* update actual length */
1122
1123 xfer->frlengths[xfer->aframes] += len;
1124 }
1125 /* Check for last transfer */
1126 if (((void *)td) == xfer->td_transfer_last) {
1127 td = NULL;
1128 break;
1129 }
1130 if (status & UHCI_TD_STALLED) {
1131 /* the transfer is finished */
1132 td = NULL;
1133 break;
1134 }
1135 /* Check for short transfer */
1136 if (len != td->len) {
1137 if (xfer->flags_int.short_frames_ok) {
1138 /* follow alt next */
1139 td = td->alt_next;
1140 } else {
1141 /* the transfer is finished */
1142 td = NULL;
1143 }
1144 break;
1145 }
1146 td = td->obj_next;
1147
1148 if (td->alt_next != td_alt_next) {
1149 /* this USB frame is complete */
1150 break;
1151 }
1152 }
1153
1154 /* update transfer cache */
1155
1156 xfer->td_transfer_cache = td;
1157
1158 /* update data toggle */
1159
1160 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1;
1161
1162 #ifdef USB_DEBUG
1163 if (status & UHCI_TD_ERROR) {
1164 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x "
1165 "status=%s%s%s%s%s%s%s%s%s%s%s\n",
1166 xfer->address, xfer->endpointno, xfer->aframes,
1167 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "",
1168 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "",
1169 (status & UHCI_TD_NAK) ? "[NAK]" : "",
1170 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "",
1171 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "",
1172 (status & UHCI_TD_STALLED) ? "[STALLED]" : "",
1173 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1174 (status & UHCI_TD_IOC) ? "[IOC]" : "",
1175 (status & UHCI_TD_IOS) ? "[IOS]" : "",
1176 (status & UHCI_TD_LS) ? "[LS]" : "",
1177 (status & UHCI_TD_SPD) ? "[SPD]" : "");
1178 }
1179 #endif
1180 if (status & UHCI_TD_STALLED) {
1181 /* try to separate I/O errors from STALL */
1182 if (UHCI_TD_GET_ERRCNT(status) == 0)
1183 return (USB_ERR_IOERROR);
1184 return (USB_ERR_STALLED);
1185 }
1186 return (USB_ERR_NORMAL_COMPLETION);
1187 }
1188
1189 static void
uhci_non_isoc_done(struct usb_xfer * xfer)1190 uhci_non_isoc_done(struct usb_xfer *xfer)
1191 {
1192 usb_error_t err = 0;
1193
1194 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1195 xfer, xfer->endpoint);
1196
1197 #ifdef USB_DEBUG
1198 if (uhcidebug > 10) {
1199 uhci_dump_tds(xfer->td_transfer_first);
1200 }
1201 #endif
1202
1203 /* sync any DMA memory before doing fixups */
1204
1205 usb_bdma_post_sync(xfer);
1206
1207 /* reset scanner */
1208
1209 xfer->td_transfer_cache = xfer->td_transfer_first;
1210
1211 if (xfer->flags_int.control_xfr) {
1212 if (xfer->flags_int.control_hdr) {
1213
1214 err = uhci_non_isoc_done_sub(xfer);
1215 }
1216 xfer->aframes = 1;
1217
1218 if (xfer->td_transfer_cache == NULL) {
1219 goto done;
1220 }
1221 }
1222 while (xfer->aframes != xfer->nframes) {
1223
1224 err = uhci_non_isoc_done_sub(xfer);
1225 xfer->aframes++;
1226
1227 if (xfer->td_transfer_cache == NULL) {
1228 goto done;
1229 }
1230 }
1231
1232 if (xfer->flags_int.control_xfr &&
1233 !xfer->flags_int.control_act) {
1234
1235 err = uhci_non_isoc_done_sub(xfer);
1236 }
1237 done:
1238 uhci_device_done(xfer, err);
1239 }
1240
1241 /*------------------------------------------------------------------------*
1242 * uhci_check_transfer_sub
1243 *
1244 * The main purpose of this function is to update the data-toggle
1245 * in case it is wrong.
1246 *------------------------------------------------------------------------*/
1247 static void
uhci_check_transfer_sub(struct usb_xfer * xfer)1248 uhci_check_transfer_sub(struct usb_xfer *xfer)
1249 {
1250 uhci_qh_t *qh;
1251 uhci_td_t *td;
1252 uhci_td_t *td_alt_next;
1253
1254 uint32_t td_token;
1255 uint32_t td_self;
1256
1257 td = xfer->td_transfer_cache;
1258 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1259
1260 td_token = td->obj_next->td_token;
1261 td = td->alt_next;
1262 xfer->td_transfer_cache = td;
1263 td_self = td->td_self;
1264 td_alt_next = td->alt_next;
1265
1266 if (xfer->flags_int.control_xfr)
1267 goto skip; /* don't touch the DT value! */
1268
1269 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))))
1270 goto skip; /* data toggle has correct value */
1271
1272 /*
1273 * The data toggle is wrong and we need to toggle it !
1274 */
1275 while (1) {
1276
1277 td->td_token ^= htole32(UHCI_TD_SET_DT(1));
1278 usb_pc_cpu_flush(td->page_cache);
1279
1280 if (td == xfer->td_transfer_last) {
1281 /* last transfer */
1282 break;
1283 }
1284 td = td->obj_next;
1285
1286 if (td->alt_next != td_alt_next) {
1287 /* next frame */
1288 break;
1289 }
1290 }
1291 skip:
1292
1293 /* update the QH */
1294 qh->qh_e_next = td_self;
1295 usb_pc_cpu_flush(qh->page_cache);
1296
1297 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1298 }
1299
1300 /*------------------------------------------------------------------------*
1301 * uhci_check_transfer
1302 *
1303 * Return values:
1304 * 0: USB transfer is not finished
1305 * Else: USB transfer is finished
1306 *------------------------------------------------------------------------*/
1307 static uint8_t
uhci_check_transfer(struct usb_xfer * xfer)1308 uhci_check_transfer(struct usb_xfer *xfer)
1309 {
1310 uint32_t status;
1311 uint32_t token;
1312 uhci_td_t *td;
1313
1314 DPRINTFN(16, "xfer=%p checking transfer\n", xfer);
1315
1316 if (xfer->endpoint->methods == &uhci_device_isoc_methods) {
1317 /* isochronous transfer */
1318
1319 td = xfer->td_transfer_last;
1320
1321 usb_pc_cpu_invalidate(td->page_cache);
1322 status = le32toh(td->td_status);
1323
1324 /* check also if the first is complete */
1325
1326 td = xfer->td_transfer_first;
1327
1328 usb_pc_cpu_invalidate(td->page_cache);
1329 status |= le32toh(td->td_status);
1330
1331 if (!(status & UHCI_TD_ACTIVE)) {
1332 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1333 goto transferred;
1334 }
1335 } else {
1336 /* non-isochronous transfer */
1337
1338 /*
1339 * check whether there is an error somewhere
1340 * in the middle, or whether there was a short
1341 * packet (SPD and not ACTIVE)
1342 */
1343 td = xfer->td_transfer_cache;
1344
1345 while (1) {
1346 usb_pc_cpu_invalidate(td->page_cache);
1347 status = le32toh(td->td_status);
1348 token = le32toh(td->td_token);
1349
1350 /*
1351 * if there is an active TD the transfer isn't done
1352 */
1353 if (status & UHCI_TD_ACTIVE) {
1354 /* update cache */
1355 xfer->td_transfer_cache = td;
1356 goto done;
1357 }
1358 /*
1359 * last transfer descriptor makes the transfer done
1360 */
1361 if (((void *)td) == xfer->td_transfer_last) {
1362 break;
1363 }
1364 /*
1365 * any kind of error makes the transfer done
1366 */
1367 if (status & UHCI_TD_STALLED) {
1368 break;
1369 }
1370 /*
1371 * check if we reached the last packet
1372 * or if there is a short packet:
1373 */
1374 if ((td->td_next == htole32(UHCI_PTR_T)) ||
1375 (UHCI_TD_GET_ACTLEN(status) < td->len)) {
1376
1377 if (xfer->flags_int.short_frames_ok) {
1378 /* follow alt next */
1379 if (td->alt_next) {
1380 /* update cache */
1381 xfer->td_transfer_cache = td;
1382 uhci_check_transfer_sub(xfer);
1383 goto done;
1384 }
1385 }
1386 /* transfer is done */
1387 break;
1388 }
1389 td = td->obj_next;
1390 }
1391 uhci_non_isoc_done(xfer);
1392 goto transferred;
1393 }
1394
1395 done:
1396 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1397 return (0);
1398
1399 transferred:
1400 return (1);
1401 }
1402
1403 static void
uhci_interrupt_poll(uhci_softc_t * sc)1404 uhci_interrupt_poll(uhci_softc_t *sc)
1405 {
1406 struct usb_xfer *xfer;
1407
1408 repeat:
1409 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1410 /*
1411 * check if transfer is transferred
1412 */
1413 if (uhci_check_transfer(xfer)) {
1414 /* queue has been modified */
1415 goto repeat;
1416 }
1417 }
1418 }
1419
1420 /*------------------------------------------------------------------------*
1421 * uhci_interrupt - UHCI interrupt handler
1422 *
1423 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1424 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1425 * is present !
1426 *------------------------------------------------------------------------*/
1427 void
uhci_interrupt(uhci_softc_t * sc)1428 uhci_interrupt(uhci_softc_t *sc)
1429 {
1430 uint32_t status;
1431
1432 USB_BUS_LOCK(&sc->sc_bus);
1433
1434 DPRINTFN(16, "real interrupt\n");
1435
1436 #ifdef USB_DEBUG
1437 if (uhcidebug > 15) {
1438 uhci_dumpregs(sc);
1439 }
1440 #endif
1441 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1442 if (status == 0) {
1443 /* the interrupt was not for us */
1444 goto done;
1445 }
1446 if (status & (UHCI_STS_RD | UHCI_STS_HSE |
1447 UHCI_STS_HCPE | UHCI_STS_HCH)) {
1448
1449 if (status & UHCI_STS_RD) {
1450 #ifdef USB_DEBUG
1451 printf("%s: resume detect\n",
1452 __FUNCTION__);
1453 #endif
1454 }
1455 if (status & UHCI_STS_HSE) {
1456 printf("%s: host system error\n",
1457 __FUNCTION__);
1458 }
1459 if (status & UHCI_STS_HCPE) {
1460 printf("%s: host controller process error\n",
1461 __FUNCTION__);
1462 }
1463 if (status & UHCI_STS_HCH) {
1464 /* no acknowledge needed */
1465 DPRINTF("%s: host controller halted\n",
1466 __FUNCTION__);
1467 #ifdef USB_DEBUG
1468 if (uhcidebug > 0) {
1469 uhci_dump_all(sc);
1470 }
1471 #endif
1472 }
1473 }
1474 /* get acknowledge bits */
1475 status &= (UHCI_STS_USBINT |
1476 UHCI_STS_USBEI |
1477 UHCI_STS_RD |
1478 UHCI_STS_HSE |
1479 UHCI_STS_HCPE |
1480 UHCI_STS_HCH);
1481
1482 if (status == 0) {
1483 /* nothing to acknowledge */
1484 goto done;
1485 }
1486 /* acknowledge interrupts */
1487 UWRITE2(sc, UHCI_STS, status);
1488
1489 /* poll all the USB transfers */
1490 uhci_interrupt_poll(sc);
1491
1492 done:
1493 USB_BUS_UNLOCK(&sc->sc_bus);
1494 }
1495
1496 /*
1497 * called when a request does not complete
1498 */
1499 static void
uhci_timeout(void * arg)1500 uhci_timeout(void *arg)
1501 {
1502 struct usb_xfer *xfer = arg;
1503
1504 DPRINTF("xfer=%p\n", xfer);
1505
1506 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1507
1508 /* transfer is transferred */
1509 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1510 }
1511
1512 static void
uhci_do_poll(struct usb_bus * bus)1513 uhci_do_poll(struct usb_bus *bus)
1514 {
1515 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1516
1517 USB_BUS_LOCK(&sc->sc_bus);
1518 uhci_interrupt_poll(sc);
1519 USB_BUS_UNLOCK(&sc->sc_bus);
1520 }
1521
1522 static void
uhci_setup_standard_chain_sub(struct uhci_std_temp * temp)1523 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1524 {
1525 uhci_td_t *td;
1526 uhci_td_t *td_next;
1527 uhci_td_t *td_alt_next;
1528 uint32_t average;
1529 uint32_t len_old;
1530 uint8_t shortpkt_old;
1531 uint8_t precompute;
1532
1533 td_alt_next = NULL;
1534 shortpkt_old = temp->shortpkt;
1535 len_old = temp->len;
1536 precompute = 1;
1537
1538 /* software is used to detect short incoming transfers */
1539
1540 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) {
1541 temp->td_status |= htole32(UHCI_TD_SPD);
1542 } else {
1543 temp->td_status &= ~htole32(UHCI_TD_SPD);
1544 }
1545
1546 temp->ml.buf_offset = 0;
1547
1548 restart:
1549
1550 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1551 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average));
1552
1553 td = temp->td;
1554 td_next = temp->td_next;
1555
1556 while (1) {
1557
1558 if (temp->len == 0) {
1559
1560 if (temp->shortpkt) {
1561 break;
1562 }
1563 /* send a Zero Length Packet, ZLP, last */
1564
1565 temp->shortpkt = 1;
1566 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0));
1567 average = 0;
1568
1569 } else {
1570
1571 average = temp->average;
1572
1573 if (temp->len < average) {
1574 temp->shortpkt = 1;
1575 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1576 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len));
1577 average = temp->len;
1578 }
1579 }
1580
1581 if (td_next == NULL) {
1582 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__);
1583 }
1584 /* get next TD */
1585
1586 td = td_next;
1587 td_next = td->obj_next;
1588
1589 /* check if we are pre-computing */
1590
1591 if (precompute) {
1592
1593 /* update remaining length */
1594
1595 temp->len -= average;
1596
1597 continue;
1598 }
1599 /* fill out current TD */
1600
1601 td->td_status = temp->td_status;
1602 td->td_token = temp->td_token;
1603
1604 /* update data toggle */
1605
1606 temp->td_token ^= htole32(UHCI_TD_SET_DT(1));
1607
1608 if (average == 0) {
1609
1610 td->len = 0;
1611 td->td_buffer = 0;
1612 td->fix_pc = NULL;
1613
1614 } else {
1615
1616 /* update remaining length */
1617
1618 temp->len -= average;
1619
1620 td->len = average;
1621
1622 /* fill out buffer pointer and do fixup, if any */
1623
1624 uhci_mem_layout_fixup(&temp->ml, td);
1625 }
1626
1627 td->alt_next = td_alt_next;
1628
1629 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1630 /* we need to receive these frames one by one ! */
1631 td->td_status |= htole32(UHCI_TD_IOC);
1632 td->td_next = htole32(UHCI_PTR_T);
1633 } else {
1634 if (td_next) {
1635 /* link the current TD with the next one */
1636 td->td_next = td_next->td_self;
1637 }
1638 }
1639
1640 usb_pc_cpu_flush(td->page_cache);
1641 }
1642
1643 if (precompute) {
1644 precompute = 0;
1645
1646 /* setup alt next pointer, if any */
1647 if (temp->last_frame) {
1648 td_alt_next = NULL;
1649 } else {
1650 /* we use this field internally */
1651 td_alt_next = td_next;
1652 }
1653
1654 /* restore */
1655 temp->shortpkt = shortpkt_old;
1656 temp->len = len_old;
1657 goto restart;
1658 }
1659 temp->td = td;
1660 temp->td_next = td_next;
1661 }
1662
1663 static uhci_td_t *
uhci_setup_standard_chain(struct usb_xfer * xfer)1664 uhci_setup_standard_chain(struct usb_xfer *xfer)
1665 {
1666 struct uhci_std_temp temp;
1667 uhci_td_t *td;
1668 uint32_t x;
1669
1670 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1671 xfer->address, UE_GET_ADDR(xfer->endpointno),
1672 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1673
1674 temp.average = xfer->max_frame_size;
1675 temp.max_frame_size = xfer->max_frame_size;
1676
1677 /* toggle the DMA set we are using */
1678 xfer->flags_int.curr_dma_set ^= 1;
1679
1680 /* get next DMA set */
1681 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1682 xfer->td_transfer_first = td;
1683 xfer->td_transfer_cache = td;
1684
1685 temp.td = NULL;
1686 temp.td_next = td;
1687 temp.last_frame = 0;
1688 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1689
1690 uhci_mem_layout_init(&temp.ml, xfer);
1691
1692 temp.td_status =
1693 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) |
1694 UHCI_TD_ACTIVE));
1695
1696 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1697 temp.td_status |= htole32(UHCI_TD_LS);
1698 }
1699 temp.td_token =
1700 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) |
1701 UHCI_TD_SET_DEVADDR(xfer->address));
1702
1703 if (xfer->endpoint->toggle_next) {
1704 /* DATA1 is next */
1705 temp.td_token |= htole32(UHCI_TD_SET_DT(1));
1706 }
1707 /* check if we should prepend a setup message */
1708
1709 if (xfer->flags_int.control_xfr) {
1710
1711 if (xfer->flags_int.control_hdr) {
1712
1713 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1714 UHCI_TD_SET_ENDPT(0xF));
1715 temp.td_token |= htole32(UHCI_TD_PID_SETUP |
1716 UHCI_TD_SET_DT(0));
1717
1718 temp.len = xfer->frlengths[0];
1719 temp.ml.buf_pc = xfer->frbuffers + 0;
1720 temp.shortpkt = temp.len ? 1 : 0;
1721 /* check for last frame */
1722 if (xfer->nframes == 1) {
1723 /* no STATUS stage yet, SETUP is last */
1724 if (xfer->flags_int.control_act) {
1725 temp.last_frame = 1;
1726 temp.setup_alt_next = 0;
1727 }
1728 }
1729 uhci_setup_standard_chain_sub(&temp);
1730 }
1731 x = 1;
1732 } else {
1733 x = 0;
1734 }
1735
1736 while (x != xfer->nframes) {
1737
1738 /* DATA0 / DATA1 message */
1739
1740 temp.len = xfer->frlengths[x];
1741 temp.ml.buf_pc = xfer->frbuffers + x;
1742
1743 x++;
1744
1745 if (x == xfer->nframes) {
1746 if (xfer->flags_int.control_xfr) {
1747 /* no STATUS stage yet, DATA is last */
1748 if (xfer->flags_int.control_act) {
1749 temp.last_frame = 1;
1750 temp.setup_alt_next = 0;
1751 }
1752 } else {
1753 temp.last_frame = 1;
1754 temp.setup_alt_next = 0;
1755 }
1756 }
1757 /*
1758 * Keep previous data toggle,
1759 * device address and endpoint number:
1760 */
1761
1762 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1763 UHCI_TD_SET_ENDPT(0xF) |
1764 UHCI_TD_SET_DT(1));
1765
1766 if (temp.len == 0) {
1767
1768 /* make sure that we send an USB packet */
1769
1770 temp.shortpkt = 0;
1771
1772 } else {
1773
1774 /* regular data transfer */
1775
1776 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1777 }
1778
1779 /* set endpoint direction */
1780
1781 temp.td_token |=
1782 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1783 htole32(UHCI_TD_PID_IN) :
1784 htole32(UHCI_TD_PID_OUT);
1785
1786 uhci_setup_standard_chain_sub(&temp);
1787 }
1788
1789 /* check if we should append a status stage */
1790
1791 if (xfer->flags_int.control_xfr &&
1792 !xfer->flags_int.control_act) {
1793
1794 /*
1795 * send a DATA1 message and reverse the current endpoint
1796 * direction
1797 */
1798
1799 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1800 UHCI_TD_SET_ENDPT(0xF) |
1801 UHCI_TD_SET_DT(1));
1802 temp.td_token |=
1803 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1804 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) :
1805 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1));
1806
1807 temp.len = 0;
1808 temp.ml.buf_pc = NULL;
1809 temp.shortpkt = 0;
1810 temp.last_frame = 1;
1811 temp.setup_alt_next = 0;
1812
1813 uhci_setup_standard_chain_sub(&temp);
1814 }
1815 td = temp.td;
1816
1817 /* Ensure that last TD is terminating: */
1818 td->td_next = htole32(UHCI_PTR_T);
1819
1820 /* set interrupt bit */
1821
1822 td->td_status |= htole32(UHCI_TD_IOC);
1823
1824 usb_pc_cpu_flush(td->page_cache);
1825
1826 /* must have at least one frame! */
1827
1828 xfer->td_transfer_last = td;
1829
1830 #ifdef USB_DEBUG
1831 if (uhcidebug > 8) {
1832 DPRINTF("nexttog=%d; data before transfer:\n",
1833 xfer->endpoint->toggle_next);
1834 uhci_dump_tds(xfer->td_transfer_first);
1835 }
1836 #endif
1837 return (xfer->td_transfer_first);
1838 }
1839
1840 /* NOTE: "done" can be run two times in a row,
1841 * from close and from interrupt
1842 */
1843
1844 static void
uhci_device_done(struct usb_xfer * xfer,usb_error_t error)1845 uhci_device_done(struct usb_xfer *xfer, usb_error_t error)
1846 {
1847 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1848 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1849 uhci_qh_t *qh;
1850
1851 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1852
1853 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1854 xfer, xfer->endpoint, error);
1855
1856 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1857 if (qh) {
1858 usb_pc_cpu_invalidate(qh->page_cache);
1859 }
1860 if (xfer->flags_int.bandwidth_reclaimed) {
1861 xfer->flags_int.bandwidth_reclaimed = 0;
1862 uhci_rem_loop(sc);
1863 }
1864 if (methods == &uhci_device_bulk_methods) {
1865 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
1866 }
1867 if (methods == &uhci_device_ctrl_methods) {
1868 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1869 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
1870 } else {
1871 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
1872 }
1873 }
1874 if (methods == &uhci_device_intr_methods) {
1875 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
1876 }
1877 /*
1878 * Only finish isochronous transfers once
1879 * which will update "xfer->frlengths".
1880 */
1881 if (xfer->td_transfer_first &&
1882 xfer->td_transfer_last) {
1883 if (methods == &uhci_device_isoc_methods) {
1884 uhci_isoc_done(sc, xfer);
1885 }
1886 xfer->td_transfer_first = NULL;
1887 xfer->td_transfer_last = NULL;
1888 }
1889 /* dequeue transfer and start next transfer */
1890 usbd_transfer_done(xfer, error);
1891 }
1892
1893 /*------------------------------------------------------------------------*
1894 * uhci bulk support
1895 *------------------------------------------------------------------------*/
1896 static void
uhci_device_bulk_open(struct usb_xfer * xfer)1897 uhci_device_bulk_open(struct usb_xfer *xfer)
1898 {
1899 return;
1900 }
1901
1902 static void
uhci_device_bulk_close(struct usb_xfer * xfer)1903 uhci_device_bulk_close(struct usb_xfer *xfer)
1904 {
1905 uhci_device_done(xfer, USB_ERR_CANCELLED);
1906 }
1907
1908 static void
uhci_device_bulk_enter(struct usb_xfer * xfer)1909 uhci_device_bulk_enter(struct usb_xfer *xfer)
1910 {
1911 return;
1912 }
1913
1914 static void
uhci_device_bulk_start(struct usb_xfer * xfer)1915 uhci_device_bulk_start(struct usb_xfer *xfer)
1916 {
1917 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1918 uhci_td_t *td;
1919 uhci_qh_t *qh;
1920
1921 /* setup TD's */
1922 td = uhci_setup_standard_chain(xfer);
1923
1924 /* setup QH */
1925 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1926
1927 qh->e_next = td;
1928 qh->qh_e_next = td->td_self;
1929
1930 if (xfer->xroot->udev->flags.self_suspended == 0) {
1931 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
1932 uhci_add_loop(sc);
1933 xfer->flags_int.bandwidth_reclaimed = 1;
1934 } else {
1935 usb_pc_cpu_flush(qh->page_cache);
1936 }
1937
1938 /* put transfer on interrupt queue */
1939 uhci_transfer_intr_enqueue(xfer);
1940 }
1941
1942 static const struct usb_pipe_methods uhci_device_bulk_methods =
1943 {
1944 .open = uhci_device_bulk_open,
1945 .close = uhci_device_bulk_close,
1946 .enter = uhci_device_bulk_enter,
1947 .start = uhci_device_bulk_start,
1948 };
1949
1950 /*------------------------------------------------------------------------*
1951 * uhci control support
1952 *------------------------------------------------------------------------*/
1953 static void
uhci_device_ctrl_open(struct usb_xfer * xfer)1954 uhci_device_ctrl_open(struct usb_xfer *xfer)
1955 {
1956 return;
1957 }
1958
1959 static void
uhci_device_ctrl_close(struct usb_xfer * xfer)1960 uhci_device_ctrl_close(struct usb_xfer *xfer)
1961 {
1962 uhci_device_done(xfer, USB_ERR_CANCELLED);
1963 }
1964
1965 static void
uhci_device_ctrl_enter(struct usb_xfer * xfer)1966 uhci_device_ctrl_enter(struct usb_xfer *xfer)
1967 {
1968 return;
1969 }
1970
1971 static void
uhci_device_ctrl_start(struct usb_xfer * xfer)1972 uhci_device_ctrl_start(struct usb_xfer *xfer)
1973 {
1974 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1975 uhci_qh_t *qh;
1976 uhci_td_t *td;
1977
1978 /* setup TD's */
1979 td = uhci_setup_standard_chain(xfer);
1980
1981 /* setup QH */
1982 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1983
1984 qh->e_next = td;
1985 qh->qh_e_next = td->td_self;
1986
1987 /*
1988 * NOTE: some devices choke on bandwidth- reclamation for control
1989 * transfers
1990 */
1991 if (xfer->xroot->udev->flags.self_suspended == 0) {
1992 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1993 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
1994 } else {
1995 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
1996 }
1997 } else {
1998 usb_pc_cpu_flush(qh->page_cache);
1999 }
2000 /* put transfer on interrupt queue */
2001 uhci_transfer_intr_enqueue(xfer);
2002 }
2003
2004 static const struct usb_pipe_methods uhci_device_ctrl_methods =
2005 {
2006 .open = uhci_device_ctrl_open,
2007 .close = uhci_device_ctrl_close,
2008 .enter = uhci_device_ctrl_enter,
2009 .start = uhci_device_ctrl_start,
2010 };
2011
2012 /*------------------------------------------------------------------------*
2013 * uhci interrupt support
2014 *------------------------------------------------------------------------*/
2015 static void
uhci_device_intr_open(struct usb_xfer * xfer)2016 uhci_device_intr_open(struct usb_xfer *xfer)
2017 {
2018 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2019 uint16_t best;
2020 uint16_t bit;
2021 uint16_t x;
2022
2023 best = 0;
2024 bit = UHCI_IFRAMELIST_COUNT / 2;
2025 while (bit) {
2026 if (xfer->interval >= bit) {
2027 x = bit;
2028 best = bit;
2029 while (x & bit) {
2030 if (sc->sc_intr_stat[x] <
2031 sc->sc_intr_stat[best]) {
2032 best = x;
2033 }
2034 x++;
2035 }
2036 break;
2037 }
2038 bit >>= 1;
2039 }
2040
2041 sc->sc_intr_stat[best]++;
2042 xfer->qh_pos = best;
2043
2044 DPRINTFN(3, "best=%d interval=%d\n",
2045 best, xfer->interval);
2046 }
2047
2048 static void
uhci_device_intr_close(struct usb_xfer * xfer)2049 uhci_device_intr_close(struct usb_xfer *xfer)
2050 {
2051 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2052
2053 sc->sc_intr_stat[xfer->qh_pos]--;
2054
2055 uhci_device_done(xfer, USB_ERR_CANCELLED);
2056 }
2057
2058 static void
uhci_device_intr_enter(struct usb_xfer * xfer)2059 uhci_device_intr_enter(struct usb_xfer *xfer)
2060 {
2061 return;
2062 }
2063
2064 static void
uhci_device_intr_start(struct usb_xfer * xfer)2065 uhci_device_intr_start(struct usb_xfer *xfer)
2066 {
2067 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2068 uhci_qh_t *qh;
2069 uhci_td_t *td;
2070
2071 /* setup TD's */
2072 td = uhci_setup_standard_chain(xfer);
2073
2074 /* setup QH */
2075 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2076
2077 qh->e_next = td;
2078 qh->qh_e_next = td->td_self;
2079
2080 if (xfer->xroot->udev->flags.self_suspended == 0) {
2081 /* enter QHs into the controller data structures */
2082 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
2083 } else {
2084 usb_pc_cpu_flush(qh->page_cache);
2085 }
2086
2087 /* put transfer on interrupt queue */
2088 uhci_transfer_intr_enqueue(xfer);
2089 }
2090
2091 static const struct usb_pipe_methods uhci_device_intr_methods =
2092 {
2093 .open = uhci_device_intr_open,
2094 .close = uhci_device_intr_close,
2095 .enter = uhci_device_intr_enter,
2096 .start = uhci_device_intr_start,
2097 };
2098
2099 /*------------------------------------------------------------------------*
2100 * uhci isochronous support
2101 *------------------------------------------------------------------------*/
2102 static void
uhci_device_isoc_open(struct usb_xfer * xfer)2103 uhci_device_isoc_open(struct usb_xfer *xfer)
2104 {
2105 uhci_td_t *td;
2106 uint32_t td_token;
2107 uint8_t ds;
2108
2109 td_token =
2110 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
2111 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) :
2112 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0);
2113
2114 td_token = htole32(td_token);
2115
2116 /* initialize all TD's */
2117
2118 for (ds = 0; ds != 2; ds++) {
2119
2120 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2121
2122 /* mark TD as inactive */
2123 td->td_status = htole32(UHCI_TD_IOS);
2124 td->td_token = td_token;
2125
2126 usb_pc_cpu_flush(td->page_cache);
2127 }
2128 }
2129 }
2130
2131 static void
uhci_device_isoc_close(struct usb_xfer * xfer)2132 uhci_device_isoc_close(struct usb_xfer *xfer)
2133 {
2134 uhci_device_done(xfer, USB_ERR_CANCELLED);
2135 }
2136
2137 static void
uhci_device_isoc_enter(struct usb_xfer * xfer)2138 uhci_device_isoc_enter(struct usb_xfer *xfer)
2139 {
2140 struct uhci_mem_layout ml;
2141 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2142 uint32_t nframes;
2143 uint32_t temp;
2144 uint32_t *plen;
2145
2146 #ifdef USB_DEBUG
2147 uint8_t once = 1;
2148
2149 #endif
2150 uhci_td_t *td;
2151 uhci_td_t *td_last = NULL;
2152 uhci_td_t **pp_last;
2153
2154 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2155 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2156
2157 nframes = UREAD2(sc, UHCI_FRNUM);
2158
2159 temp = (nframes - xfer->endpoint->isoc_next) &
2160 (UHCI_VFRAMELIST_COUNT - 1);
2161
2162 if ((xfer->endpoint->is_synced == 0) ||
2163 (temp < xfer->nframes)) {
2164 /*
2165 * If there is data underflow or the pipe queue is empty we
2166 * schedule the transfer a few frames ahead of the current
2167 * frame position. Else two isochronous transfers might
2168 * overlap.
2169 */
2170 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1);
2171 xfer->endpoint->is_synced = 1;
2172 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2173 }
2174 /*
2175 * compute how many milliseconds the insertion is ahead of the
2176 * current frame position:
2177 */
2178 temp = (xfer->endpoint->isoc_next - nframes) &
2179 (UHCI_VFRAMELIST_COUNT - 1);
2180
2181 /*
2182 * pre-compute when the isochronous transfer will be finished:
2183 */
2184 xfer->isoc_time_complete =
2185 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2186 xfer->nframes;
2187
2188 /* get the real number of frames */
2189
2190 nframes = xfer->nframes;
2191
2192 uhci_mem_layout_init(&ml, xfer);
2193
2194 plen = xfer->frlengths;
2195
2196 /* toggle the DMA set we are using */
2197 xfer->flags_int.curr_dma_set ^= 1;
2198
2199 /* get next DMA set */
2200 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2201 xfer->td_transfer_first = td;
2202
2203 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next];
2204
2205 /* store starting position */
2206
2207 xfer->qh_pos = xfer->endpoint->isoc_next;
2208
2209 while (nframes--) {
2210 if (td == NULL) {
2211 panic("%s:%d: out of TD's\n",
2212 __FUNCTION__, __LINE__);
2213 }
2214 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
2215 pp_last = &sc->sc_isoc_p_last[0];
2216 }
2217 if (*plen > xfer->max_frame_size) {
2218 #ifdef USB_DEBUG
2219 if (once) {
2220 once = 0;
2221 printf("%s: frame length(%d) exceeds %d "
2222 "bytes (frame truncated)\n",
2223 __FUNCTION__, *plen,
2224 xfer->max_frame_size);
2225 }
2226 #endif
2227 *plen = xfer->max_frame_size;
2228 }
2229 /* reuse td_token from last transfer */
2230
2231 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2232 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen));
2233
2234 td->len = *plen;
2235
2236 if (td->len == 0) {
2237 /*
2238 * Do not call "uhci_mem_layout_fixup()" when the
2239 * length is zero!
2240 */
2241 td->td_buffer = 0;
2242 td->fix_pc = NULL;
2243
2244 } else {
2245
2246 /* fill out buffer pointer and do fixup, if any */
2247
2248 uhci_mem_layout_fixup(&ml, td);
2249
2250 }
2251
2252 /* update status */
2253 if (nframes == 0) {
2254 td->td_status = htole32
2255 (UHCI_TD_ZERO_ACTLEN
2256 (UHCI_TD_SET_ERRCNT(0) |
2257 UHCI_TD_ACTIVE |
2258 UHCI_TD_IOS |
2259 UHCI_TD_IOC));
2260 } else {
2261 td->td_status = htole32
2262 (UHCI_TD_ZERO_ACTLEN
2263 (UHCI_TD_SET_ERRCNT(0) |
2264 UHCI_TD_ACTIVE |
2265 UHCI_TD_IOS));
2266 }
2267
2268 usb_pc_cpu_flush(td->page_cache);
2269
2270 #ifdef USB_DEBUG
2271 if (uhcidebug > 5) {
2272 DPRINTF("TD %d\n", nframes);
2273 uhci_dump_td(td);
2274 }
2275 #endif
2276 /* insert TD into schedule */
2277 UHCI_APPEND_TD(td, *pp_last);
2278 pp_last++;
2279
2280 plen++;
2281 td_last = td;
2282 td = td->obj_next;
2283 }
2284
2285 xfer->td_transfer_last = td_last;
2286
2287 /* update isoc_next */
2288 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) &
2289 (UHCI_VFRAMELIST_COUNT - 1);
2290 }
2291
2292 static void
uhci_device_isoc_start(struct usb_xfer * xfer)2293 uhci_device_isoc_start(struct usb_xfer *xfer)
2294 {
2295 /* put transfer on interrupt queue */
2296 uhci_transfer_intr_enqueue(xfer);
2297 }
2298
2299 static const struct usb_pipe_methods uhci_device_isoc_methods =
2300 {
2301 .open = uhci_device_isoc_open,
2302 .close = uhci_device_isoc_close,
2303 .enter = uhci_device_isoc_enter,
2304 .start = uhci_device_isoc_start,
2305 };
2306
2307 /*------------------------------------------------------------------------*
2308 * uhci root control support
2309 *------------------------------------------------------------------------*
2310 * Simulate a hardware hub by handling all the necessary requests.
2311 *------------------------------------------------------------------------*/
2312
2313 static const
2314 struct usb_device_descriptor uhci_devd =
2315 {
2316 sizeof(struct usb_device_descriptor),
2317 UDESC_DEVICE, /* type */
2318 {0x00, 0x01}, /* USB version */
2319 UDCLASS_HUB, /* class */
2320 UDSUBCLASS_HUB, /* subclass */
2321 UDPROTO_FSHUB, /* protocol */
2322 64, /* max packet */
2323 {0}, {0}, {0x00, 0x01}, /* device id */
2324 1, 2, 0, /* string indexes */
2325 1 /* # of configurations */
2326 };
2327
2328 static const struct uhci_config_desc uhci_confd = {
2329 .confd = {
2330 .bLength = sizeof(struct usb_config_descriptor),
2331 .bDescriptorType = UDESC_CONFIG,
2332 .wTotalLength[0] = sizeof(uhci_confd),
2333 .bNumInterface = 1,
2334 .bConfigurationValue = 1,
2335 .iConfiguration = 0,
2336 .bmAttributes = UC_SELF_POWERED,
2337 .bMaxPower = 0 /* max power */
2338 },
2339 .ifcd = {
2340 .bLength = sizeof(struct usb_interface_descriptor),
2341 .bDescriptorType = UDESC_INTERFACE,
2342 .bNumEndpoints = 1,
2343 .bInterfaceClass = UICLASS_HUB,
2344 .bInterfaceSubClass = UISUBCLASS_HUB,
2345 .bInterfaceProtocol = UIPROTO_FSHUB,
2346 },
2347 .endpd = {
2348 .bLength = sizeof(struct usb_endpoint_descriptor),
2349 .bDescriptorType = UDESC_ENDPOINT,
2350 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT,
2351 .bmAttributes = UE_INTERRUPT,
2352 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2353 .bInterval = 255,
2354 },
2355 };
2356
2357 static const
2358 struct usb_hub_descriptor_min uhci_hubd_piix =
2359 {
2360 .bDescLength = sizeof(uhci_hubd_piix),
2361 .bDescriptorType = UDESC_HUB,
2362 .bNbrPorts = 2,
2363 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
2364 .bPwrOn2PwrGood = 50,
2365 };
2366
2367 /*
2368 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
2369 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
2370 * should not be used by the USB subsystem. As we cannot issue a
2371 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
2372 * will be enabled as part of the reset.
2373 *
2374 * On the VT83C572, the port cannot be successfully enabled until the
2375 * outstanding "port enable change" and "connection status change"
2376 * events have been reset.
2377 */
2378 static usb_error_t
uhci_portreset(uhci_softc_t * sc,uint16_t index)2379 uhci_portreset(uhci_softc_t *sc, uint16_t index)
2380 {
2381 uint16_t port;
2382 uint16_t x;
2383 uint8_t lim;
2384
2385 if (index == 1)
2386 port = UHCI_PORTSC1;
2387 else if (index == 2)
2388 port = UHCI_PORTSC2;
2389 else
2390 return (USB_ERR_IOERROR);
2391
2392 /*
2393 * Before we do anything, turn on SOF messages on the USB
2394 * BUS. Some USB devices do not cope without them!
2395 */
2396 uhci_restart(sc);
2397
2398 x = URWMASK(UREAD2(sc, port));
2399 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2400
2401 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2402 USB_MS_TO_TICKS(usb_port_root_reset_delay));
2403
2404 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2405 index, UREAD2(sc, port));
2406
2407 x = URWMASK(UREAD2(sc, port));
2408 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2409
2410
2411 mtx_unlock(&sc->sc_bus.bus_mtx);
2412
2413 /*
2414 * This delay needs to be exactly 100us, else some USB devices
2415 * fail to attach!
2416 */
2417 DELAY(100);
2418
2419 mtx_lock(&sc->sc_bus.bus_mtx);
2420
2421 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2422 index, UREAD2(sc, port));
2423
2424 x = URWMASK(UREAD2(sc, port));
2425 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2426
2427 for (lim = 0; lim < 12; lim++) {
2428
2429 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2430 USB_MS_TO_TICKS(usb_port_reset_delay));
2431
2432 x = UREAD2(sc, port);
2433
2434 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2435 index, lim, x);
2436
2437 if (!(x & UHCI_PORTSC_CCS)) {
2438 /*
2439 * No device is connected (or was disconnected
2440 * during reset). Consider the port reset.
2441 * The delay must be long enough to ensure on
2442 * the initial iteration that the device
2443 * connection will have been registered. 50ms
2444 * appears to be sufficient, but 20ms is not.
2445 */
2446 DPRINTFN(4, "uhci port %d loop %u, device detached\n",
2447 index, lim);
2448 goto done;
2449 }
2450 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
2451 /*
2452 * Port enabled changed and/or connection
2453 * status changed were set. Reset either or
2454 * both raised flags (by writing a 1 to that
2455 * bit), and wait again for state to settle.
2456 */
2457 UWRITE2(sc, port, URWMASK(x) |
2458 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
2459 continue;
2460 }
2461 if (x & UHCI_PORTSC_PE) {
2462 /* port is enabled */
2463 goto done;
2464 }
2465 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
2466 }
2467
2468 DPRINTFN(2, "uhci port %d reset timed out\n", index);
2469 return (USB_ERR_TIMEOUT);
2470
2471 done:
2472 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n",
2473 index, UREAD2(sc, port));
2474
2475 sc->sc_isreset = 1;
2476 return (USB_ERR_NORMAL_COMPLETION);
2477 }
2478
2479 static usb_error_t
uhci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)2480 uhci_roothub_exec(struct usb_device *udev,
2481 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2482 {
2483 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2484 const void *ptr;
2485 const char *str_ptr;
2486 uint16_t x;
2487 uint16_t port;
2488 uint16_t value;
2489 uint16_t index;
2490 uint16_t status;
2491 uint16_t change;
2492 uint16_t len;
2493 usb_error_t err;
2494
2495 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2496
2497 /* buffer reset */
2498 ptr = (const void *)&sc->sc_hub_desc.temp;
2499 len = 0;
2500 err = 0;
2501
2502 value = UGETW(req->wValue);
2503 index = UGETW(req->wIndex);
2504
2505 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2506 "wValue=0x%04x wIndex=0x%04x\n",
2507 req->bmRequestType, req->bRequest,
2508 UGETW(req->wLength), value, index);
2509
2510 #define C(x,y) ((x) | ((y) << 8))
2511 switch (C(req->bRequest, req->bmRequestType)) {
2512 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2513 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2514 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2515 /*
2516 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2517 * for the integrated root hub.
2518 */
2519 break;
2520 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2521 len = 1;
2522 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2523 break;
2524 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2525 switch (value >> 8) {
2526 case UDESC_DEVICE:
2527 if ((value & 0xff) != 0) {
2528 err = USB_ERR_IOERROR;
2529 goto done;
2530 }
2531 len = sizeof(uhci_devd);
2532 ptr = (const void *)&uhci_devd;
2533 break;
2534
2535 case UDESC_CONFIG:
2536 if ((value & 0xff) != 0) {
2537 err = USB_ERR_IOERROR;
2538 goto done;
2539 }
2540 len = sizeof(uhci_confd);
2541 ptr = (const void *)&uhci_confd;
2542 break;
2543
2544 case UDESC_STRING:
2545 switch (value & 0xff) {
2546 case 0: /* Language table */
2547 str_ptr = "\001";
2548 break;
2549
2550 case 1: /* Vendor */
2551 str_ptr = sc->sc_vendor;
2552 break;
2553
2554 case 2: /* Product */
2555 str_ptr = "UHCI root HUB";
2556 break;
2557
2558 default:
2559 str_ptr = "";
2560 break;
2561 }
2562
2563 len = usb_make_str_desc
2564 (sc->sc_hub_desc.temp,
2565 sizeof(sc->sc_hub_desc.temp),
2566 str_ptr);
2567 break;
2568
2569 default:
2570 err = USB_ERR_IOERROR;
2571 goto done;
2572 }
2573 break;
2574 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2575 len = 1;
2576 sc->sc_hub_desc.temp[0] = 0;
2577 break;
2578 case C(UR_GET_STATUS, UT_READ_DEVICE):
2579 len = 2;
2580 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2581 break;
2582 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2583 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2584 len = 2;
2585 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2586 break;
2587 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2588 if (value >= UHCI_MAX_DEVICES) {
2589 err = USB_ERR_IOERROR;
2590 goto done;
2591 }
2592 sc->sc_addr = value;
2593 break;
2594 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2595 if ((value != 0) && (value != 1)) {
2596 err = USB_ERR_IOERROR;
2597 goto done;
2598 }
2599 sc->sc_conf = value;
2600 break;
2601 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2602 break;
2603 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2604 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2605 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2606 err = USB_ERR_IOERROR;
2607 goto done;
2608 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2609 break;
2610 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2611 break;
2612 /* Hub requests */
2613 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2614 break;
2615 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2616 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
2617 "port=%d feature=%d\n",
2618 index, value);
2619 if (index == 1)
2620 port = UHCI_PORTSC1;
2621 else if (index == 2)
2622 port = UHCI_PORTSC2;
2623 else {
2624 err = USB_ERR_IOERROR;
2625 goto done;
2626 }
2627 switch (value) {
2628 case UHF_PORT_ENABLE:
2629 x = URWMASK(UREAD2(sc, port));
2630 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
2631 break;
2632 case UHF_PORT_SUSPEND:
2633 x = URWMASK(UREAD2(sc, port));
2634 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP));
2635 break;
2636 case UHF_PORT_RESET:
2637 x = URWMASK(UREAD2(sc, port));
2638 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2639 break;
2640 case UHF_C_PORT_CONNECTION:
2641 x = URWMASK(UREAD2(sc, port));
2642 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
2643 break;
2644 case UHF_C_PORT_ENABLE:
2645 x = URWMASK(UREAD2(sc, port));
2646 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
2647 break;
2648 case UHF_C_PORT_OVER_CURRENT:
2649 x = URWMASK(UREAD2(sc, port));
2650 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
2651 break;
2652 case UHF_C_PORT_RESET:
2653 sc->sc_isreset = 0;
2654 err = USB_ERR_NORMAL_COMPLETION;
2655 goto done;
2656 case UHF_C_PORT_SUSPEND:
2657 sc->sc_isresumed &= ~(1 << index);
2658 break;
2659 case UHF_PORT_CONNECTION:
2660 case UHF_PORT_OVER_CURRENT:
2661 case UHF_PORT_POWER:
2662 case UHF_PORT_LOW_SPEED:
2663 default:
2664 err = USB_ERR_IOERROR;
2665 goto done;
2666 }
2667 break;
2668 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
2669 if (index == 1)
2670 port = UHCI_PORTSC1;
2671 else if (index == 2)
2672 port = UHCI_PORTSC2;
2673 else {
2674 err = USB_ERR_IOERROR;
2675 goto done;
2676 }
2677 len = 1;
2678 sc->sc_hub_desc.temp[0] =
2679 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >>
2680 UHCI_PORTSC_LS_SHIFT);
2681 break;
2682 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2683 if ((value & 0xff) != 0) {
2684 err = USB_ERR_IOERROR;
2685 goto done;
2686 }
2687 len = sizeof(uhci_hubd_piix);
2688 ptr = (const void *)&uhci_hubd_piix;
2689 break;
2690 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2691 len = 16;
2692 memset(sc->sc_hub_desc.temp, 0, 16);
2693 break;
2694 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2695 if (index == 1)
2696 port = UHCI_PORTSC1;
2697 else if (index == 2)
2698 port = UHCI_PORTSC2;
2699 else {
2700 err = USB_ERR_IOERROR;
2701 goto done;
2702 }
2703 x = UREAD2(sc, port);
2704 status = change = 0;
2705 if (x & UHCI_PORTSC_CCS)
2706 status |= UPS_CURRENT_CONNECT_STATUS;
2707 if (x & UHCI_PORTSC_CSC)
2708 change |= UPS_C_CONNECT_STATUS;
2709 if (x & UHCI_PORTSC_PE)
2710 status |= UPS_PORT_ENABLED;
2711 if (x & UHCI_PORTSC_POEDC)
2712 change |= UPS_C_PORT_ENABLED;
2713 if (x & UHCI_PORTSC_OCI)
2714 status |= UPS_OVERCURRENT_INDICATOR;
2715 if (x & UHCI_PORTSC_OCIC)
2716 change |= UPS_C_OVERCURRENT_INDICATOR;
2717 if (x & UHCI_PORTSC_LSDA)
2718 status |= UPS_LOW_SPEED;
2719 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) {
2720 /* need to do a write back */
2721 UWRITE2(sc, port, URWMASK(x));
2722
2723 /* wait 20ms for resume sequence to complete */
2724 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2725
2726 /* clear suspend and resume detect */
2727 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD |
2728 UHCI_PORTSC_SUSP));
2729
2730 /* wait a little bit */
2731 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500);
2732
2733 sc->sc_isresumed |= (1 << index);
2734
2735 } else if (x & UHCI_PORTSC_SUSP) {
2736 status |= UPS_SUSPEND;
2737 }
2738 status |= UPS_PORT_POWER;
2739 if (sc->sc_isresumed & (1 << index))
2740 change |= UPS_C_SUSPEND;
2741 if (sc->sc_isreset)
2742 change |= UPS_C_PORT_RESET;
2743 USETW(sc->sc_hub_desc.ps.wPortStatus, status);
2744 USETW(sc->sc_hub_desc.ps.wPortChange, change);
2745 len = sizeof(sc->sc_hub_desc.ps);
2746 break;
2747 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2748 err = USB_ERR_IOERROR;
2749 goto done;
2750 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2751 break;
2752 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2753 if (index == 1)
2754 port = UHCI_PORTSC1;
2755 else if (index == 2)
2756 port = UHCI_PORTSC2;
2757 else {
2758 err = USB_ERR_IOERROR;
2759 goto done;
2760 }
2761 switch (value) {
2762 case UHF_PORT_ENABLE:
2763 x = URWMASK(UREAD2(sc, port));
2764 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2765 break;
2766 case UHF_PORT_SUSPEND:
2767 x = URWMASK(UREAD2(sc, port));
2768 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
2769 break;
2770 case UHF_PORT_RESET:
2771 err = uhci_portreset(sc, index);
2772 goto done;
2773 case UHF_PORT_POWER:
2774 /* pretend we turned on power */
2775 err = USB_ERR_NORMAL_COMPLETION;
2776 goto done;
2777 case UHF_C_PORT_CONNECTION:
2778 case UHF_C_PORT_ENABLE:
2779 case UHF_C_PORT_OVER_CURRENT:
2780 case UHF_PORT_CONNECTION:
2781 case UHF_PORT_OVER_CURRENT:
2782 case UHF_PORT_LOW_SPEED:
2783 case UHF_C_PORT_SUSPEND:
2784 case UHF_C_PORT_RESET:
2785 default:
2786 err = USB_ERR_IOERROR;
2787 goto done;
2788 }
2789 break;
2790 default:
2791 err = USB_ERR_IOERROR;
2792 goto done;
2793 }
2794 done:
2795 *plength = len;
2796 *pptr = ptr;
2797 return (err);
2798 }
2799
2800 /*
2801 * This routine is executed periodically and simulates interrupts from
2802 * the root controller interrupt pipe for port status change:
2803 */
2804 static void
uhci_root_intr(uhci_softc_t * sc)2805 uhci_root_intr(uhci_softc_t *sc)
2806 {
2807 DPRINTFN(21, "\n");
2808
2809 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2810
2811 sc->sc_hub_idata[0] = 0;
2812
2813 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC |
2814 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2815 sc->sc_hub_idata[0] |= 1 << 1;
2816 }
2817 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC |
2818 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2819 sc->sc_hub_idata[0] |= 1 << 2;
2820 }
2821
2822 /* restart timer */
2823 usb_callout_reset(&sc->sc_root_intr, hz,
2824 (void *)&uhci_root_intr, sc);
2825
2826 if (sc->sc_hub_idata[0] != 0) {
2827 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2828 sizeof(sc->sc_hub_idata));
2829 }
2830 }
2831
2832 static void
uhci_xfer_setup(struct usb_setup_params * parm)2833 uhci_xfer_setup(struct usb_setup_params *parm)
2834 {
2835 struct usb_page_search page_info;
2836 struct usb_page_cache *pc;
2837 uhci_softc_t *sc;
2838 struct usb_xfer *xfer;
2839 void *last_obj;
2840 uint32_t ntd;
2841 uint32_t nqh;
2842 uint32_t nfixup;
2843 uint32_t n;
2844 uint16_t align;
2845
2846 sc = UHCI_BUS2SC(parm->udev->bus);
2847 xfer = parm->curr_xfer;
2848
2849 parm->hc_max_packet_size = 0x500;
2850 parm->hc_max_packet_count = 1;
2851 parm->hc_max_frame_size = 0x500;
2852
2853 /*
2854 * compute ntd and nqh
2855 */
2856 if (parm->methods == &uhci_device_ctrl_methods) {
2857 xfer->flags_int.bdma_enable = 1;
2858 xfer->flags_int.bdma_no_post_sync = 1;
2859
2860 usbd_transfer_setup_sub(parm);
2861
2862 /* see EHCI HC driver for proof of "ntd" formula */
2863
2864 nqh = 1;
2865 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2866 + (xfer->max_data_length / xfer->max_frame_size));
2867
2868 } else if (parm->methods == &uhci_device_bulk_methods) {
2869 xfer->flags_int.bdma_enable = 1;
2870 xfer->flags_int.bdma_no_post_sync = 1;
2871
2872 usbd_transfer_setup_sub(parm);
2873
2874 nqh = 1;
2875 ntd = ((2 * xfer->nframes)
2876 + (xfer->max_data_length / xfer->max_frame_size));
2877
2878 } else if (parm->methods == &uhci_device_intr_methods) {
2879 xfer->flags_int.bdma_enable = 1;
2880 xfer->flags_int.bdma_no_post_sync = 1;
2881
2882 usbd_transfer_setup_sub(parm);
2883
2884 nqh = 1;
2885 ntd = ((2 * xfer->nframes)
2886 + (xfer->max_data_length / xfer->max_frame_size));
2887
2888 } else if (parm->methods == &uhci_device_isoc_methods) {
2889 xfer->flags_int.bdma_enable = 1;
2890 xfer->flags_int.bdma_no_post_sync = 1;
2891
2892 usbd_transfer_setup_sub(parm);
2893
2894 nqh = 0;
2895 ntd = xfer->nframes;
2896
2897 } else {
2898
2899 usbd_transfer_setup_sub(parm);
2900
2901 nqh = 0;
2902 ntd = 0;
2903 }
2904
2905 if (parm->err) {
2906 return;
2907 }
2908 /*
2909 * NOTE: the UHCI controller requires that
2910 * every packet must be contiguous on
2911 * the same USB memory page !
2912 */
2913 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1;
2914
2915 /*
2916 * Compute a suitable power of two alignment
2917 * for our "max_frame_size" fixup buffer(s):
2918 */
2919 align = xfer->max_frame_size;
2920 n = 0;
2921 while (align) {
2922 align >>= 1;
2923 n++;
2924 }
2925
2926 /* check for power of two */
2927 if (!(xfer->max_frame_size &
2928 (xfer->max_frame_size - 1))) {
2929 n--;
2930 }
2931 /*
2932 * We don't allow alignments of
2933 * less than 8 bytes:
2934 *
2935 * NOTE: Allocating using an aligment
2936 * of 1 byte has special meaning!
2937 */
2938 if (n < 3) {
2939 n = 3;
2940 }
2941 align = (1 << n);
2942
2943 if (usbd_transfer_setup_sub_malloc(
2944 parm, &pc, xfer->max_frame_size,
2945 align, nfixup)) {
2946 parm->err = USB_ERR_NOMEM;
2947 return;
2948 }
2949 xfer->buf_fixup = pc;
2950
2951 alloc_dma_set:
2952
2953 if (parm->err) {
2954 return;
2955 }
2956 last_obj = NULL;
2957
2958 if (usbd_transfer_setup_sub_malloc(
2959 parm, &pc, sizeof(uhci_td_t),
2960 UHCI_TD_ALIGN, ntd)) {
2961 parm->err = USB_ERR_NOMEM;
2962 return;
2963 }
2964 if (parm->buf) {
2965 for (n = 0; n != ntd; n++) {
2966 uhci_td_t *td;
2967
2968 usbd_get_page(pc + n, 0, &page_info);
2969
2970 td = page_info.buffer;
2971
2972 /* init TD */
2973 if ((parm->methods == &uhci_device_bulk_methods) ||
2974 (parm->methods == &uhci_device_ctrl_methods) ||
2975 (parm->methods == &uhci_device_intr_methods)) {
2976 /* set depth first bit */
2977 td->td_self = htole32(page_info.physaddr |
2978 UHCI_PTR_TD | UHCI_PTR_VF);
2979 } else {
2980 td->td_self = htole32(page_info.physaddr |
2981 UHCI_PTR_TD);
2982 }
2983
2984 td->obj_next = last_obj;
2985 td->page_cache = pc + n;
2986
2987 last_obj = td;
2988
2989 usb_pc_cpu_flush(pc + n);
2990 }
2991 }
2992 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2993
2994 last_obj = NULL;
2995
2996 if (usbd_transfer_setup_sub_malloc(
2997 parm, &pc, sizeof(uhci_qh_t),
2998 UHCI_QH_ALIGN, nqh)) {
2999 parm->err = USB_ERR_NOMEM;
3000 return;
3001 }
3002 if (parm->buf) {
3003 for (n = 0; n != nqh; n++) {
3004 uhci_qh_t *qh;
3005
3006 usbd_get_page(pc + n, 0, &page_info);
3007
3008 qh = page_info.buffer;
3009
3010 /* init QH */
3011 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH);
3012 qh->obj_next = last_obj;
3013 qh->page_cache = pc + n;
3014
3015 last_obj = qh;
3016
3017 usb_pc_cpu_flush(pc + n);
3018 }
3019 }
3020 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3021
3022 if (!xfer->flags_int.curr_dma_set) {
3023 xfer->flags_int.curr_dma_set = 1;
3024 goto alloc_dma_set;
3025 }
3026 }
3027
3028 static void
uhci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3029 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3030 struct usb_endpoint *ep)
3031 {
3032 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
3033
3034 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3035 ep, udev->address,
3036 edesc->bEndpointAddress, udev->flags.usb_mode,
3037 sc->sc_addr);
3038
3039 if (udev->device_index != sc->sc_addr) {
3040 switch (edesc->bmAttributes & UE_XFERTYPE) {
3041 case UE_CONTROL:
3042 ep->methods = &uhci_device_ctrl_methods;
3043 break;
3044 case UE_INTERRUPT:
3045 ep->methods = &uhci_device_intr_methods;
3046 break;
3047 case UE_ISOCHRONOUS:
3048 if (udev->speed == USB_SPEED_FULL) {
3049 ep->methods = &uhci_device_isoc_methods;
3050 }
3051 break;
3052 case UE_BULK:
3053 ep->methods = &uhci_device_bulk_methods;
3054 break;
3055 default:
3056 /* do nothing */
3057 break;
3058 }
3059 }
3060 }
3061
3062 static void
uhci_xfer_unsetup(struct usb_xfer * xfer)3063 uhci_xfer_unsetup(struct usb_xfer *xfer)
3064 {
3065 return;
3066 }
3067
3068 static void
uhci_get_dma_delay(struct usb_device * udev,uint32_t * pus)3069 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3070 {
3071 /*
3072 * Wait until hardware has finished any possible use of the
3073 * transfer descriptor(s) and QH
3074 */
3075 *pus = (1125); /* microseconds */
3076 }
3077
3078 static void
uhci_device_resume(struct usb_device * udev)3079 uhci_device_resume(struct usb_device *udev)
3080 {
3081 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3082 struct usb_xfer *xfer;
3083 const struct usb_pipe_methods *methods;
3084 uhci_qh_t *qh;
3085
3086 DPRINTF("\n");
3087
3088 USB_BUS_LOCK(udev->bus);
3089
3090 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3091
3092 if (xfer->xroot->udev == udev) {
3093
3094 methods = xfer->endpoint->methods;
3095 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3096
3097 if (methods == &uhci_device_bulk_methods) {
3098 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
3099 uhci_add_loop(sc);
3100 xfer->flags_int.bandwidth_reclaimed = 1;
3101 }
3102 if (methods == &uhci_device_ctrl_methods) {
3103 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3104 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
3105 } else {
3106 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
3107 }
3108 }
3109 if (methods == &uhci_device_intr_methods) {
3110 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3111 }
3112 }
3113 }
3114
3115 USB_BUS_UNLOCK(udev->bus);
3116
3117 return;
3118 }
3119
3120 static void
uhci_device_suspend(struct usb_device * udev)3121 uhci_device_suspend(struct usb_device *udev)
3122 {
3123 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3124 struct usb_xfer *xfer;
3125 const struct usb_pipe_methods *methods;
3126 uhci_qh_t *qh;
3127
3128 DPRINTF("\n");
3129
3130 USB_BUS_LOCK(udev->bus);
3131
3132 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3133
3134 if (xfer->xroot->udev == udev) {
3135
3136 methods = xfer->endpoint->methods;
3137 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3138
3139 if (xfer->flags_int.bandwidth_reclaimed) {
3140 xfer->flags_int.bandwidth_reclaimed = 0;
3141 uhci_rem_loop(sc);
3142 }
3143 if (methods == &uhci_device_bulk_methods) {
3144 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
3145 }
3146 if (methods == &uhci_device_ctrl_methods) {
3147 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3148 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
3149 } else {
3150 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
3151 }
3152 }
3153 if (methods == &uhci_device_intr_methods) {
3154 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3155 }
3156 }
3157 }
3158
3159 USB_BUS_UNLOCK(udev->bus);
3160
3161 return;
3162 }
3163
3164 static void
uhci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)3165 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3166 {
3167 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3168
3169 switch (state) {
3170 case USB_HW_POWER_SUSPEND:
3171 case USB_HW_POWER_SHUTDOWN:
3172 uhci_suspend(sc);
3173 break;
3174 case USB_HW_POWER_RESUME:
3175 uhci_resume(sc);
3176 break;
3177 default:
3178 break;
3179 }
3180 }
3181
3182 static void
uhci_set_hw_power(struct usb_bus * bus)3183 uhci_set_hw_power(struct usb_bus *bus)
3184 {
3185 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3186 uint32_t flags;
3187
3188 DPRINTF("\n");
3189
3190 USB_BUS_LOCK(bus);
3191
3192 flags = bus->hw_power_state;
3193
3194 /*
3195 * WARNING: Some FULL speed USB devices require periodic SOF
3196 * messages! If any USB devices are connected through the
3197 * UHCI, power save will be disabled!
3198 */
3199 if (flags & (USB_HW_POWER_CONTROL |
3200 USB_HW_POWER_NON_ROOT_HUB |
3201 USB_HW_POWER_BULK |
3202 USB_HW_POWER_INTERRUPT |
3203 USB_HW_POWER_ISOC)) {
3204 DPRINTF("Some USB transfer is "
3205 "active on unit %u.\n",
3206 device_get_unit(sc->sc_bus.bdev));
3207 uhci_restart(sc);
3208 } else {
3209 DPRINTF("Power save on unit %u.\n",
3210 device_get_unit(sc->sc_bus.bdev));
3211 UHCICMD(sc, UHCI_CMD_MAXP);
3212 }
3213
3214 USB_BUS_UNLOCK(bus);
3215
3216 return;
3217 }
3218
3219
3220 static const struct usb_bus_methods uhci_bus_methods =
3221 {
3222 .endpoint_init = uhci_ep_init,
3223 .xfer_setup = uhci_xfer_setup,
3224 .xfer_unsetup = uhci_xfer_unsetup,
3225 .get_dma_delay = uhci_get_dma_delay,
3226 .device_resume = uhci_device_resume,
3227 .device_suspend = uhci_device_suspend,
3228 .set_hw_power = uhci_set_hw_power,
3229 .set_hw_power_sleep = uhci_set_hw_power_sleep,
3230 .roothub_exec = uhci_roothub_exec,
3231 .xfer_poll = uhci_do_poll,
3232 };
3233