1 /* $OpenBSD: timerreg.h,v 1.4 2003/06/02 23:27:55 millert Exp $ */ 2 /* $NetBSD: timerreg.h,v 1.6 1996/10/28 00:20:32 abrown Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)timerreg.h 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* 45 * Sun-4c counter/timer registers. The timers are implemented within 46 * the cache chip (!). The counter and limit fields below could be 47 * defined as: 48 * 49 * struct { 50 * u_int t_limit:1, // limit reached 51 * t_usec:21, // counter value in microseconds 52 * t_mbz:10; // always zero 53 * }; 54 * 55 * but this is more trouble than it is worth. 56 * 57 * These timers work in a rather peculiar fashion. Most clock counters 58 * run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a 59 * large unsigned number). On the Sun-4c, it counts up to a limit. But 60 * for some reason, when it reaches the limit, it resets to 1, not 0. 61 * Thus, if the limit is set to 4, the counter counts like this: 62 * 63 * 1, 2, 3, 1, 2, 3, ... 64 * 65 * and if we want to divide by N we must set the limit register to N+1. 66 * 67 * Sun-4m counters/timer registers are similar, with these exceptions: 68 * 69 * - the limit and counter registers have changed positions.. 70 * - both limit and counter registers are 22 bits wide, but 71 * they count in 500ns increments (bit 9 being the least 72 * significant bit). 73 * 74 */ 75 #ifndef _LOCORE 76 struct timer_4 { 77 volatile int t_counter; /* counter reg */ 78 volatile int t_limit; /* limit reg */ 79 }; 80 81 struct timerreg_4 { 82 struct timer_4 t_c10; /* counter that interrupts at ipl 10 */ 83 struct timer_4 t_c14; /* counter that interrupts at ipl 14 */ 84 }; 85 86 struct timer_4m { /* counter that interrupts at ipl 10 */ 87 volatile int t_limit; /* limit register */ 88 volatile int t_counter; /* counter register */ 89 volatile int t_limit_nr; /* limit reg, non-resetting */ 90 volatile int t_reserved; 91 volatile int t_cfg; /* a configuration register */ 92 /* 93 * Note: The SparcClassic manual only defines this one bit 94 * I suspect there are more in multi-processor machines. 95 */ 96 #define TMR_CFG_USER 1 97 }; 98 99 struct counter_4m { /* counter that interrupts at ipl 14 */ 100 volatile int t_limit; /* limit register */ 101 volatile int t_counter; /* counter register */ 102 volatile int t_limit_nr; /* limit reg, non-resetting */ 103 volatile int t_ss; /* Start/Stop register */ 104 #define TMR_USER_RUN 1 105 }; 106 #endif /* _LOCORE */ 107 108 #define TMR_LIMIT 0x80000000 /* counter reached its limit */ 109 #define TMR_SHIFT 10 /* shift to obtain microseconds */ 110 #define TMR_MASK 0x1fffff /* 21 bits */ 111 112 /* 113 * Compute a limit that causes the timer to fire every n microseconds. 114 * The Sun4c requires that the timer register be initialized for n+1 115 * microseconds, while the Sun4m requires it be initialized for n. Thus 116 * the two versions of this function. 117 * 118 * Note that the manual for the chipset used in the Sun4m suggests that 119 * the timer be set at n+0.5 microseconds; in practice, this produces 120 * a 50 ppm clock skew, which means that the 0.5 should not be there... 121 */ 122 #define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT) 123 124 /*efine TMR_SHIFT4M 9 -* shift to obtain microseconds */ 125 /*efine tmr_ustolim4m(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/ 126 #define tmr_ustolim4m(n) ((n) << TMR_SHIFT) 127