1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
2 /*
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37
radeon_irq_set_state(struct drm_device * dev,u32 mask,int state)38 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
39 {
40 drm_radeon_private_t *dev_priv = dev->dev_private;
41
42 if (state)
43 dev_priv->irq_enable_reg |= mask;
44 else
45 dev_priv->irq_enable_reg &= ~mask;
46
47 if (dev->irq_enabled)
48 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
49 }
50
r500_vbl_irq_set_state(struct drm_device * dev,u32 mask,int state)51 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
52 {
53 drm_radeon_private_t *dev_priv = dev->dev_private;
54
55 if (state)
56 dev_priv->r500_disp_irq_reg |= mask;
57 else
58 dev_priv->r500_disp_irq_reg &= ~mask;
59
60 if (dev->irq_enabled)
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
62 }
63
radeon_enable_vblank(struct drm_device * dev,unsigned int crtc)64 int radeon_enable_vblank(struct drm_device *dev, unsigned int crtc)
65 {
66 drm_radeon_private_t *dev_priv = dev->dev_private;
67
68 if (!dev_priv->mmio)
69 return 0;
70
71 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
72 switch (crtc) {
73 case 0:
74 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
75 break;
76 case 1:
77 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
78 break;
79 default:
80 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
81 crtc);
82 return EINVAL;
83 }
84 } else {
85 switch (crtc) {
86 case 0:
87 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
88 break;
89 case 1:
90 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
91 break;
92 default:
93 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
94 crtc);
95 return EINVAL;
96 }
97 }
98
99 return 0;
100 }
101
radeon_disable_vblank(struct drm_device * dev,unsigned int crtc)102 void radeon_disable_vblank(struct drm_device *dev, unsigned int crtc)
103 {
104 drm_radeon_private_t *dev_priv = dev->dev_private;
105
106 if (!dev_priv->mmio)
107 return;
108
109 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
110 switch (crtc) {
111 case 0:
112 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
113 break;
114 case 1:
115 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
116 break;
117 default:
118 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
119 crtc);
120 break;
121 }
122 } else {
123 switch (crtc) {
124 case 0:
125 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
126 break;
127 case 1:
128 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
129 break;
130 default:
131 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
132 crtc);
133 break;
134 }
135 }
136 }
137
radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,u32 * r500_disp_int)138 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
139 {
140 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
141 u32 irq_mask = RADEON_SW_INT_TEST;
142
143 *r500_disp_int = 0;
144 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
145 /* vbl interrupts in a different place */
146
147 if (irqs & R500_DISPLAY_INT_STATUS) {
148 /* if a display interrupt */
149 u32 disp_irq;
150
151 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
152
153 *r500_disp_int = disp_irq;
154 if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
155 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
156 }
157 if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
158 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
159 }
160 }
161 irq_mask |= R500_DISPLAY_INT_STATUS;
162 } else
163 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
164
165 irqs &= irq_mask;
166
167 if (irqs)
168 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
169
170 return irqs;
171 }
172
173 /* Interrupts - Used for device synchronization and flushing in the
174 * following circumstances:
175 *
176 * - Exclusive FB access with hw idle:
177 * - Wait for GUI Idle (?) interrupt, then do normal flush.
178 *
179 * - Frame throttling, NV_fence:
180 * - Drop marker irq's into command stream ahead of time.
181 * - Wait on irq's with lock *not held*
182 * - Check each for termination condition
183 *
184 * - Internally in cp_getbuffer, etc:
185 * - as above, but wait with lock held???
186 *
187 * NOTE: These functions are misleadingly named -- the irq's aren't
188 * tied to dma at all, this is just a hangover from dri prehistory.
189 */
190
radeon_driver_irq_handler(DRM_IRQ_ARGS)191 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
192 {
193 struct drm_device *dev = (struct drm_device *) arg;
194 drm_radeon_private_t *dev_priv =
195 (drm_radeon_private_t *) dev->dev_private;
196 u32 stat;
197 u32 r500_disp_int;
198 u32 tmp;
199
200 /* Only consider the bits we're interested in - others could be used
201 * outside the DRM
202 */
203 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
204 if (!stat)
205 return IRQ_NONE;
206
207 stat &= dev_priv->irq_enable_reg;
208
209 /* SW interrupt */
210 if (stat & RADEON_SW_INT_TEST)
211 DRM_WAKEUP(&dev_priv->swi_queue);
212
213 /* VBLANK interrupt */
214 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
215 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
216 drm_handle_vblank(dev, 0);
217 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
218 drm_handle_vblank(dev, 1);
219 } else {
220 if (stat & RADEON_CRTC_VBLANK_STAT)
221 drm_handle_vblank(dev, 0);
222 if (stat & RADEON_CRTC2_VBLANK_STAT)
223 drm_handle_vblank(dev, 1);
224 }
225 if (dev->msi_enabled) {
226 switch(dev_priv->flags & RADEON_FAMILY_MASK) {
227 case CHIP_RS400:
228 case CHIP_RS480:
229 tmp = RADEON_READ(RADEON_AIC_CNTL) &
230 ~RS400_MSI_REARM;
231 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
232 RADEON_WRITE(RADEON_AIC_CNTL,
233 tmp | RS400_MSI_REARM);
234 break;
235 case CHIP_RS690:
236 case CHIP_RS740:
237 tmp = RADEON_READ(RADEON_BUS_CNTL) &
238 ~RS600_MSI_REARM;
239 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
240 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
241 RS600_MSI_REARM);
242 break;
243 default:
244 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
245 ~RV370_MSI_REARM_EN;
246 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
247 RADEON_WRITE(RADEON_MSI_REARM_EN,
248 tmp | RV370_MSI_REARM_EN);
249 break;
250 }
251 }
252 return IRQ_HANDLED;
253 }
254
radeon_emit_irq(struct drm_device * dev)255 static int radeon_emit_irq(struct drm_device * dev)
256 {
257 drm_radeon_private_t *dev_priv = dev->dev_private;
258 unsigned int ret;
259 RING_LOCALS;
260
261 atomic_inc(&dev_priv->swi_emitted);
262 ret = atomic_read(&dev_priv->swi_emitted);
263
264 BEGIN_RING(4);
265 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
266 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
267 ADVANCE_RING();
268 COMMIT_RING();
269
270 return ret;
271 }
272
radeon_wait_irq(struct drm_device * dev,int swi_nr)273 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
274 {
275 drm_radeon_private_t *dev_priv =
276 (drm_radeon_private_t *) dev->dev_private;
277 int ret = 0;
278
279 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
280 return 0;
281
282 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
283
284 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
285 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
286
287 return ret;
288 }
289
radeon_get_vblank_counter(struct drm_device * dev,unsigned int crtc)290 u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int crtc)
291 {
292 drm_radeon_private_t *dev_priv = dev->dev_private;
293
294 if (!dev_priv) {
295 DRM_ERROR("called with no initialization\n");
296 return -EINVAL;
297 }
298 if (!dev_priv->mmio)
299 return 0;
300
301 if (crtc > 1) {
302 DRM_ERROR("Invalid crtc %d\n", crtc);
303 return -EINVAL;
304 }
305
306 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
307 if (crtc == 0)
308 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
309 else
310 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
311 } else {
312 if (crtc == 0)
313 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
314 else
315 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
316 }
317 }
318
319 /* Needs the lock as it touches the ring.
320 */
radeon_irq_emit(struct drm_device * dev,void * data,struct drm_file * file_priv)321 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
322 {
323 drm_radeon_private_t *dev_priv = dev->dev_private;
324 drm_radeon_irq_emit_t *emit = data;
325 int result;
326
327 LOCK_TEST_WITH_RETURN(dev, file_priv);
328
329 if (!dev_priv) {
330 DRM_ERROR("called with no initialization\n");
331 return -EINVAL;
332 }
333 if (!dev_priv->mmio)
334 return 0;
335
336 result = radeon_emit_irq(dev);
337
338 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
339 DRM_ERROR("copy_to_user\n");
340 return -EFAULT;
341 }
342
343 return 0;
344 }
345
346 /* Doesn't need the hardware lock.
347 */
radeon_irq_wait(struct drm_device * dev,void * data,struct drm_file * file_priv)348 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
349 {
350 drm_radeon_private_t *dev_priv = dev->dev_private;
351 drm_radeon_irq_wait_t *irqwait = data;
352
353 if (!dev_priv) {
354 DRM_ERROR("called with no initialization\n");
355 return -EINVAL;
356 }
357 if (!dev_priv->mmio)
358 return 0;
359
360 return radeon_wait_irq(dev, irqwait->irq_seq);
361 }
362
363 /* drm_dma.h hooks
364 */
radeon_driver_irq_preinstall(struct drm_device * dev)365 void radeon_driver_irq_preinstall(struct drm_device * dev)
366 {
367 drm_radeon_private_t *dev_priv =
368 (drm_radeon_private_t *) dev->dev_private;
369 u32 dummy;
370
371 /* Disable *all* interrupts */
372 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
373 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
374 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
375
376 /* Clear bits if they're already high */
377 radeon_acknowledge_irqs(dev_priv, &dummy);
378 }
379
radeon_driver_irq_postinstall(struct drm_device * dev)380 int radeon_driver_irq_postinstall(struct drm_device * dev)
381 {
382 drm_radeon_private_t *dev_priv =
383 (drm_radeon_private_t *) dev->dev_private;
384
385 atomic_set(&dev_priv->swi_emitted, 0);
386 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
387
388 dev->max_vblank_count = 0x001fffff;
389
390 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
391
392 return 0;
393 }
394
radeon_driver_irq_uninstall(struct drm_device * dev)395 void radeon_driver_irq_uninstall(struct drm_device * dev)
396 {
397 drm_radeon_private_t *dev_priv =
398 (drm_radeon_private_t *) dev->dev_private;
399 if (!dev_priv)
400 return;
401
402 dev_priv->irq_enabled = 0;
403
404 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
405 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
406 /* Disable *all* interrupts */
407 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
408 }
409
410
radeon_vblank_crtc_get(struct drm_device * dev)411 int radeon_vblank_crtc_get(struct drm_device *dev)
412 {
413 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
414
415 return dev_priv->vblank_crtc;
416 }
417
radeon_vblank_crtc_set(struct drm_device * dev,int64_t value)418 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
419 {
420 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
421 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
422 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
423 return -EINVAL;
424 }
425 dev_priv->vblank_crtc = (unsigned int)value;
426 return 0;
427 }
428