1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_psp.h"
29 #include "amdgpu_ucode.h"
30 #include "soc15_common.h"
31 #include "psp_v10_0.h"
32
33 #include "mp/mp_10_0_offset.h"
34 #include "gc/gc_9_1_offset.h"
35 #include "sdma0/sdma0_4_1_offset.h"
36
37 MODULE_FIRMWARE("amdgpufw_raven_asd");
38
39 static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)40 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
41 {
42 switch(ucode->ucode_id) {
43 case AMDGPU_UCODE_ID_SDMA0:
44 *type = GFX_FW_TYPE_SDMA0;
45 break;
46 case AMDGPU_UCODE_ID_SDMA1:
47 *type = GFX_FW_TYPE_SDMA1;
48 break;
49 case AMDGPU_UCODE_ID_CP_CE:
50 *type = GFX_FW_TYPE_CP_CE;
51 break;
52 case AMDGPU_UCODE_ID_CP_PFP:
53 *type = GFX_FW_TYPE_CP_PFP;
54 break;
55 case AMDGPU_UCODE_ID_CP_ME:
56 *type = GFX_FW_TYPE_CP_ME;
57 break;
58 case AMDGPU_UCODE_ID_CP_MEC1:
59 *type = GFX_FW_TYPE_CP_MEC;
60 break;
61 case AMDGPU_UCODE_ID_CP_MEC1_JT:
62 *type = GFX_FW_TYPE_CP_MEC_ME1;
63 break;
64 case AMDGPU_UCODE_ID_CP_MEC2:
65 *type = GFX_FW_TYPE_CP_MEC;
66 break;
67 case AMDGPU_UCODE_ID_CP_MEC2_JT:
68 *type = GFX_FW_TYPE_CP_MEC_ME2;
69 break;
70 case AMDGPU_UCODE_ID_RLC_G:
71 *type = GFX_FW_TYPE_RLC_G;
72 break;
73 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
74 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
75 break;
76 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
77 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
78 break;
79 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
80 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
81 break;
82 case AMDGPU_UCODE_ID_SMC:
83 *type = GFX_FW_TYPE_SMU;
84 break;
85 case AMDGPU_UCODE_ID_UVD:
86 *type = GFX_FW_TYPE_UVD;
87 break;
88 case AMDGPU_UCODE_ID_VCE:
89 *type = GFX_FW_TYPE_VCE;
90 break;
91 case AMDGPU_UCODE_ID_VCN:
92 *type = GFX_FW_TYPE_VCN;
93 break;
94 case AMDGPU_UCODE_ID_MAXIMUM:
95 default:
96 return -EINVAL;
97 }
98
99 return 0;
100 }
101
psp_v10_0_init_microcode(struct psp_context * psp)102 static int psp_v10_0_init_microcode(struct psp_context *psp)
103 {
104 struct amdgpu_device *adev = psp->adev;
105 const char *chip_name;
106 char fw_name[30];
107 int err = 0;
108 const struct psp_firmware_header_v1_0 *hdr;
109
110 DRM_DEBUG("\n");
111
112 switch (adev->asic_type) {
113 case CHIP_RAVEN:
114 chip_name = "raven";
115 break;
116 default: BUG();
117 }
118
119 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_asd", chip_name);
120 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
121 if (err)
122 goto out;
123
124 err = amdgpu_ucode_validate(adev->psp.asd_fw);
125 if (err)
126 goto out;
127
128 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
129 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
130 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
131 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
132 adev->psp.asd_start_addr = (uint8_t *)hdr +
133 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
134
135 return 0;
136 out:
137 if (err) {
138 dev_err(adev->dev,
139 "psp v10.0: Failed to load firmware \"%s\"\n",
140 fw_name);
141 release_firmware(adev->psp.asd_fw);
142 adev->psp.asd_fw = NULL;
143 }
144
145 return err;
146 }
147
psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)148 static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
149 struct psp_gfx_cmd_resp *cmd)
150 {
151 int ret;
152 uint64_t fw_mem_mc_addr = ucode->mc_addr;
153
154 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
155
156 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
157 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
158 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
159 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
160
161 ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
162 if (ret)
163 DRM_ERROR("Unknown firmware type\n");
164
165 return ret;
166 }
167
psp_v10_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)168 static int psp_v10_0_ring_init(struct psp_context *psp,
169 enum psp_ring_type ring_type)
170 {
171 int ret = 0;
172 struct psp_ring *ring;
173 struct amdgpu_device *adev = psp->adev;
174
175 ring = &psp->km_ring;
176
177 ring->ring_type = ring_type;
178
179 /* allocate 4k Page of Local Frame Buffer memory for ring */
180 ring->ring_size = 0x1000;
181 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
182 AMDGPU_GEM_DOMAIN_VRAM,
183 &adev->firmware.rbuf,
184 (u64 *)&ring->ring_mem_mc_addr,
185 (void **)&ring->ring_mem);
186 if (ret) {
187 ring->ring_size = 0;
188 return ret;
189 }
190
191 return 0;
192 }
193
psp_v10_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)194 static int psp_v10_0_ring_create(struct psp_context *psp,
195 enum psp_ring_type ring_type)
196 {
197 int ret = 0;
198 unsigned int psp_ring_reg = 0;
199 struct psp_ring *ring = &psp->km_ring;
200 struct amdgpu_device *adev = psp->adev;
201
202 /* Write low address of the ring to C2PMSG_69 */
203 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
204 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
205 /* Write high address of the ring to C2PMSG_70 */
206 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
207 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
208 /* Write size of ring to C2PMSG_71 */
209 psp_ring_reg = ring->ring_size;
210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
211 /* Write the ring initialization command to C2PMSG_64 */
212 psp_ring_reg = ring_type;
213 psp_ring_reg = psp_ring_reg << 16;
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
215
216 /* There might be handshake issue with hardware which needs delay */
217 mdelay(20);
218
219 /* Wait for response flag (bit 31) in C2PMSG_64 */
220 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
221 0x80000000, 0x8000FFFF, false);
222
223 return ret;
224 }
225
psp_v10_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)226 static int psp_v10_0_ring_stop(struct psp_context *psp,
227 enum psp_ring_type ring_type)
228 {
229 int ret = 0;
230 struct psp_ring *ring;
231 unsigned int psp_ring_reg = 0;
232 struct amdgpu_device *adev = psp->adev;
233
234 ring = &psp->km_ring;
235
236 /* Write the ring destroy command to C2PMSG_64 */
237 psp_ring_reg = 3 << 16;
238 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
239
240 /* There might be handshake issue with hardware which needs delay */
241 mdelay(20);
242
243 /* Wait for response flag (bit 31) in C2PMSG_64 */
244 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
245 0x80000000, 0x80000000, false);
246
247 return ret;
248 }
249
psp_v10_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)250 static int psp_v10_0_ring_destroy(struct psp_context *psp,
251 enum psp_ring_type ring_type)
252 {
253 int ret = 0;
254 struct psp_ring *ring = &psp->km_ring;
255 struct amdgpu_device *adev = psp->adev;
256
257 ret = psp_v10_0_ring_stop(psp, ring_type);
258 if (ret)
259 DRM_ERROR("Fail to stop psp ring\n");
260
261 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
262 (u64 *)&ring->ring_mem_mc_addr,
263 (void **)&ring->ring_mem);
264
265 return ret;
266 }
267
psp_v10_0_cmd_submit(struct psp_context * psp,struct amdgpu_firmware_info * ucode,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)268 static int psp_v10_0_cmd_submit(struct psp_context *psp,
269 struct amdgpu_firmware_info *ucode,
270 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
271 int index)
272 {
273 unsigned int psp_write_ptr_reg = 0;
274 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
275 struct psp_ring *ring = &psp->km_ring;
276 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
277 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
278 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
279 struct amdgpu_device *adev = psp->adev;
280 uint32_t ring_size_dw = ring->ring_size / 4;
281 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
282
283 /* KM (GPCOM) prepare write pointer */
284 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
285
286 /* Update KM RB frame pointer to new frame */
287 if ((psp_write_ptr_reg % ring_size_dw) == 0)
288 write_frame = ring_buffer_start;
289 else
290 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
291 /* Check invalid write_frame ptr address */
292 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
293 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
294 ring_buffer_start, ring_buffer_end, write_frame);
295 DRM_ERROR("write_frame is pointing to address out of bounds\n");
296 return -EINVAL;
297 }
298
299 /* Initialize KM RB frame */
300 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
301
302 /* Update KM RB frame */
303 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
304 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
305 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
306 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
307 write_frame->fence_value = index;
308
309 /* Update the write Pointer in DWORDs */
310 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
312
313 return 0;
314 }
315
316 static int
psp_v10_0_sram_map(struct amdgpu_device * adev,unsigned int * sram_offset,unsigned int * sram_addr_reg_offset,unsigned int * sram_data_reg_offset,enum AMDGPU_UCODE_ID ucode_id)317 psp_v10_0_sram_map(struct amdgpu_device *adev,
318 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
319 unsigned int *sram_data_reg_offset,
320 enum AMDGPU_UCODE_ID ucode_id)
321 {
322 int ret = 0;
323
324 switch(ucode_id) {
325 /* TODO: needs to confirm */
326 #if 0
327 case AMDGPU_UCODE_ID_SMC:
328 *sram_offset = 0;
329 *sram_addr_reg_offset = 0;
330 *sram_data_reg_offset = 0;
331 break;
332 #endif
333
334 case AMDGPU_UCODE_ID_CP_CE:
335 *sram_offset = 0x0;
336 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
337 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
338 break;
339
340 case AMDGPU_UCODE_ID_CP_PFP:
341 *sram_offset = 0x0;
342 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
343 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
344 break;
345
346 case AMDGPU_UCODE_ID_CP_ME:
347 *sram_offset = 0x0;
348 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
349 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
350 break;
351
352 case AMDGPU_UCODE_ID_CP_MEC1:
353 *sram_offset = 0x10000;
354 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
355 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
356 break;
357
358 case AMDGPU_UCODE_ID_CP_MEC2:
359 *sram_offset = 0x10000;
360 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
361 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
362 break;
363
364 case AMDGPU_UCODE_ID_RLC_G:
365 *sram_offset = 0x2000;
366 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
367 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
368 break;
369
370 case AMDGPU_UCODE_ID_SDMA0:
371 *sram_offset = 0x0;
372 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
373 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
374 break;
375
376 /* TODO: needs to confirm */
377 #if 0
378 case AMDGPU_UCODE_ID_SDMA1:
379 *sram_offset = ;
380 *sram_addr_reg_offset = ;
381 break;
382
383 case AMDGPU_UCODE_ID_UVD:
384 *sram_offset = ;
385 *sram_addr_reg_offset = ;
386 break;
387
388 case AMDGPU_UCODE_ID_VCE:
389 *sram_offset = ;
390 *sram_addr_reg_offset = ;
391 break;
392 #endif
393
394 case AMDGPU_UCODE_ID_MAXIMUM:
395 default:
396 ret = -EINVAL;
397 break;
398 }
399
400 return ret;
401 }
402
psp_v10_0_compare_sram_data(struct psp_context * psp,struct amdgpu_firmware_info * ucode,enum AMDGPU_UCODE_ID ucode_type)403 static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
404 struct amdgpu_firmware_info *ucode,
405 enum AMDGPU_UCODE_ID ucode_type)
406 {
407 int err = 0;
408 unsigned int fw_sram_reg_val = 0;
409 unsigned int fw_sram_addr_reg_offset = 0;
410 unsigned int fw_sram_data_reg_offset = 0;
411 unsigned int ucode_size;
412 uint32_t *ucode_mem = NULL;
413 struct amdgpu_device *adev = psp->adev;
414
415 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
416 &fw_sram_data_reg_offset, ucode_type);
417 if (err)
418 return false;
419
420 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
421
422 ucode_size = ucode->ucode_size;
423 ucode_mem = (uint32_t *)ucode->kaddr;
424 while (!ucode_size) {
425 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
426
427 if (*ucode_mem != fw_sram_reg_val)
428 return false;
429
430 ucode_mem++;
431 /* 4 bytes */
432 ucode_size -= 4;
433 }
434
435 return true;
436 }
437
438
psp_v10_0_mode1_reset(struct psp_context * psp)439 static int psp_v10_0_mode1_reset(struct psp_context *psp)
440 {
441 DRM_INFO("psp mode 1 reset not supported now! \n");
442 return -EINVAL;
443 }
444
445 static const struct psp_funcs psp_v10_0_funcs = {
446 .init_microcode = psp_v10_0_init_microcode,
447 .prep_cmd_buf = psp_v10_0_prep_cmd_buf,
448 .ring_init = psp_v10_0_ring_init,
449 .ring_create = psp_v10_0_ring_create,
450 .ring_stop = psp_v10_0_ring_stop,
451 .ring_destroy = psp_v10_0_ring_destroy,
452 .cmd_submit = psp_v10_0_cmd_submit,
453 .compare_sram_data = psp_v10_0_compare_sram_data,
454 .mode1_reset = psp_v10_0_mode1_reset,
455 };
456
psp_v10_0_set_psp_funcs(struct psp_context * psp)457 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
458 {
459 psp->funcs = &psp_v10_0_funcs;
460 }
461