1.\" Copyright (c) 2010 George Neville-Neil. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd March 24, 2012 25.Dt PMC.OCTEON 3 26.Os 27.Sh NAME 28.Nm pmc.octeon 29.Nd measurement events for 30.Tn Octeon 31family CPUs 32.Sh LIBRARY 33.Lb libpmc 34.Sh SYNOPSIS 35.In pmc.h 36.Sh DESCRIPTION 37There are two counters per core supported by the hardware and each is 64 bits 38wide. 39.Ss Event Specifiers (Programmable PMCs) 40MIPS programmable PMCs support the following events: 41.Bl -tag -width indent 42.It Li CLK 43.Pq Event 1 44Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) 45.It Li ISSUE 46.Pq Event 2 47Instructions issued but not retired 48.It Li RET 49.Pq Event 3 50Instructions retired 51.It Li NISSUE 52.Pq Event 4 53Cycles no issue 54.It Li SISSUE 55.Pq Event 5 56Cycles single issue 57.It Li DISSUE 58.Pq Event 6 59Cycles dual issue 60.It Li IFI 61.Pq Event 7 62Cycle ifetch issued (but not necessarily commit to pp_mem) 63.It Li BR 64.Pq Event 8 65Branches retired 66.It Li BRMIS 67.Pq Event 9 68Branch mispredicts 69.It Li J 70.Pq Event 10 71Jumps retired 72.It Li JMIS 73.Pq Event 11 74Jumps mispredicted 75.It Li REPLAY 76.Pq Event 12 77Mem Replays 78.It Li IUNA 79.Pq Event 13 80Cycles idle due to unaligned_replays 81.It Li TRAP 82.Pq Event 14 83trap_6a signal 84.It Li UULOAD 85.Pq Event 16 86Unexpected unaligned loads (REPUN=1) 87.It Li UUSTORE 88.Pq Event 17 89Unexpected unaligned store (REPUN=1) 90.It Li ULOAD 91.Pq Event 18 92Unaligned loads (REPUN=1 or USEUN=1) 93.It Li USTORE 94.Pq Event 19 95Unaligned store (REPUN=1 or USEUN=1) 96.It Li EC 97.Pq Event 20 98Exec clocks(must set CvmCtl[DISCE] for accurate timing) 99.It Li MC 100.Pq Event 21 101Mul clocks(must set CvmCtl[DISCE] for accurate timing) 102.It Li CC 103.Pq Event 22 104Crypto clocks(must set CvmCtl[DISCE] for accurate timing) 105.It Li CSRC 106.Pq Event 23 107Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) 108.It Li CFETCH 109.Pq Event 24 110Icache committed fetches (demand+prefetch) 111.It Li CPREF 112.Pq Event 25 113Icache committed prefetches 114.It Li ICA 115.Pq Event 26 116Icache aliases 117.It Li II 118.Pq Event 27 119Icache invalidates 120.It Li IP 121.Pq Event 28 122Icache parity error 123.It Li CIMISS 124.Pq Event 29 125Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) 126.It Li WBUF 127.Pq Event 32 128Number of write buffer entries created 129.It Li WDAT 130.Pq Event 33 131Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) 132.It Li WBUFLD 133.Pq Event 34 134Number of write buffer entries forced out by loads 135.It Li WBUFFL 136.Pq Event 35 137Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) 138.It Li WBUFTR 139.Pq Event 36 140Number of stores that found no available write buffer entries 141.It Li BADD 142.Pq Event 37 143Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) 144.It Li BADDL2 145.Pq Event 38 146Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) 147.It Li BFILL 148.Pq Event 39 149Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) 150.It Li DDIDS 151.Pq Event 40 152Number of Dstream DIDs created 153.It Li IDIDS 154.Pq Event 41 155Number of Istream DIDs created 156.It Li DIDNA 157.Pq Event 42 158Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) 159.It Li LDS 160.Pq Event 43 161Number of load issues 162.It Li LMLDS 163.Pq Event 44 164Number of local memory load 165.It Li IOLDS 166.Pq Event 45 167Number of I/O load issues 168.It Li DMLDS 169.Pq Event 46 170Number of loads that were not prefetches and missed in the cache 171.It Li STS 172.Pq Event 48 173Number of store issues 174.It Li LMSTS 175.Pq Event 49 176Number of local memory store issues 177.It Li IOSTS 178.Pq Event 50 179Number of I/O store issues 180.It Li IOBDMA 181.Pq Event 51 182Number of IOBDMAs 183.It Li DTLB 184.Pq Event 53 185Number of dstream TLB refill, invalid, or modified exceptions 186.It Li DTLBAD 187.Pq Event 54 188Number of dstream TLB address errors 189.It Li ITLB 190.Pq Event 55 191Number of istream TLB refill, invalid, or address error exceptions 192.It Li SYNC 193.Pq Event 56 194Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) 195.It Li SYNCIOB 196.Pq Event 57 197Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) 198.It Li SYNCW 199.Pq Event 58 200Number of SYNCWs 201.It Li ERETMIS 202.Pq Event 64 203D/eret mispredicts (CN63XX specific) 204.It Li LIKMIS 205.Pq Event 65 206Branch likely mispredicts (CN63XX specific) 207.It Li HAZTR 208.Pq Event 66 209Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific) 210.El 211.Ss Event Name Aliases 212The following table shows the mapping between the PMC-independent 213aliases supported by 214.Lb libpmc 215and the underlying hardware events used. 216.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" 217.It Em Alias Ta Em Event 218.It Li instructions Ta Li RET 219.It Li branches Ta Li BR 220.It Li branch-mispredicts Ta Li BS 221.El 222.Sh SEE ALSO 223.Xr pmc 3 , 224.Xr pmc.atom 3 , 225.Xr pmc.core 3 , 226.Xr pmc.iaf 3 , 227.Xr pmc.k7 3 , 228.Xr pmc.k8 3 , 229.Xr pmc.mips24k 3 , 230.Xr pmc.soft 3 , 231.Xr pmc.tsc 3 , 232.Xr pmc_cpuinfo 3 , 233.Xr pmclog 3 , 234.Xr hwpmc 4 235.Sh HISTORY 236The 237.Nm pmc 238library first appeared in 239.Fx 6.0 . 240.Sh AUTHORS 241.An -nosplit 242The 243.Lb libpmc 244library was written by 245.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 246MIPS support was added by 247.An George Neville-Neil Aq Mt gnn@FreeBSD.org . 248