1.\" Copyright (c) 2010 George Neville-Neil. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd March 24, 2012 25.Dt PMC.MIPS24K 3 26.Os 27.Sh NAME 28.Nm pmc.mips24k 29.Nd measurement events for 30.Tn MIPS24K 31family CPUs 32.Sh LIBRARY 33.Lb libpmc 34.Sh SYNOPSIS 35.In pmc.h 36.Sh DESCRIPTION 37MIPS PMCs are present in MIPS 38.Tn "24k" 39and other processors in the MIPS family. 40.Pp 41There are two counters supported by the hardware and each is 32 bits 42wide. 43.Pp 44MIPS PMCs are documented in 45.Rs 46.%B "MIPS32 24K Processor Core Family Software User's Manual" 47.%D December 2008 48.%Q "MIPS Technologies Inc." 49.Re 50.Ss Event Specifiers (Programmable PMCs) 51MIPS programmable PMCs support the following events: 52.Bl -tag -width indent 53.It Li CYCLE 54.Pq Event 0, Counter 0/1 55Total number of cycles. 56The performance counters are clocked by the 57top-level gated clock. 58If the core is built with that clock gater 59present, none of the counters will increment while the clock is 60stopped - due to a WAIT instruction. 61.It Li INSTR_EXECUTED 62.Pq Event 1, Counter 0/1 63Total number of instructions completed. 64.It Li BRANCH_COMPLETED 65.Pq Event 2, Counter 0 66Total number of branch instructions completed. 67.It Li BRANCH_MISPRED 68.Pq Event 2, Counter 1 69Counts all branch instructions which completed, but were mispredicted. 70.It Li RETURN 71.Pq Event 3, Counter 0 72Counts all JR R31 instructions completed. 73.It Li RETURN_MISPRED 74.Pq Event 3, Counter 1 75Counts all JR $31 instructions which completed, used the RPS for a prediction, but were mispredicted. 76.It Li RETURN_NOT_31 77.Pq Event 4, Counter 0 78Counts all JR $xx (not $31) and JALR instructions (indirect jumps). 79.It Li RETURN_NOTPRED 80.Pq Event 4, Counter 1 81If RPS use is disabled, JR $31 will not be predicted. 82.It Li ITLB_ACCESS 83.Pq Event 5, Counter 0 84Counts ITLB accesses that are due to fetches showing up in the 85instruction fetch stage of the pipeline and which do not use a fixed 86mapping or are not in unmapped space. 87If an address is fetched twice from the pipe (as in the case of a 88cache miss), that instruction willcount as 2 ITLB accesses. 89Since each fetch gets us 2 instructions,there is one access marked per double 90word. 91.It Li ITLB_MISS 92.Pq Event 5, Counter 1 93Counts all misses in the ITLB except ones that are on the back of another 94miss. 95We cannot process back to back misses and thus those are 96ignored. 97They are also ignored if there is some form of address error. 98.It Li DTLB_ACCESS 99.Pq Event 6, Counter 0 100Counts DTLB access including those in unmapped address spaces. 101.It Li DTLB_MISS 102.Pq Event 6, Counter 1 103Counts DTLB misses. 104Back to back misses that result in only one DTLB 105entry getting refilled are counted as a single miss. 106.It Li JTLB_IACCESS 107.Pq Event 7, Counter 0 108Instruction JTLB accesses are counted exactly the same as ITLB misses. 109.It Li JTLB_IMISS 110.Pq Event 7, Counter 1 111Counts instruction JTLB accesses that result in no match or a match on 112an invalid translation. 113.It Li JTLB_DACCESS 114.Pq Event 8, Counter 0 115Data JTLB accesses. 116.It Li JTLB_DMISS 117.Pq Event 8, Counter 1 118Counts data JTLB accesses that result in no match or a match on an invalid translation. 119.It Li IC_FETCH 120.Pq Event 9, Counter 0 121Counts every time the instruction cache is accessed. 122All replays, 123wasted fetches etc. are counted. 124For example, following a branch, even though the prediction is taken, 125the fall through access is counted. 126.It Li IC_MISS 127.Pq Event 9, Counter 1 128Counts all instruction cache misses that result in a bus request. 129.It Li DC_LOADSTORE 130.Pq Event 10, Counter 0 131Counts cached loads and stores. 132.It Li DC_WRITEBACK 133.Pq Event 10, Counter 1 134Counts cache lines written back to memory due to replacement or cacheops. 135.It Li DC_MISS 136.Pq Event 11, Counter 0/1 137Counts loads and stores that miss in the cache 138.It Li LOAD_MISS 139.Pq Event 13, Counter 0 140Counts number of cacheable loads that miss in the cache. 141.It Li STORE_MISS 142.Pq Event 13, Counter 1 143Counts number of cacheable stores that miss in the cache. 144.It Li INTEGER_COMPLETED 145.Pq Event 14, Counter 0 146Non-floating point, non-Coprocessor 2 instructions. 147.It Li FP_COMPLETED 148.Pq Event 14, Counter 1 149Floating point instructions completed. 150.It Li LOAD_COMPLETED 151.Pq Event 15, Counter 0 152Integer and co-processor loads completed. 153.It Li STORE_COMPLETED 154.Pq Event 15, Counter 1 155Integer and co-processor stores completed. 156.It Li BARRIER_COMPLETED 157.Pq Event 16, Counter 0 158Direct jump (and link) instructions completed. 159.It Li MIPS16_COMPLETED 160.Pq Event 16, Counter 1 161MIPS16c instructions completed. 162.It Li NOP_COMPLETED 163.Pq Event 17, Counter 0 164NOPs completed. 165This includes all instructions that normally write to a general 166purpose register, but where the destination register was set to r0. 167.It Li INTEGER_MULDIV_COMPLETED 168.Pq Event 17, Counter 1 169Integer multiply and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx). 170.It Li RF_STALL 171.Pq Event 18, Counter 0 172Counts the total number of cycles where no instructions are issued 173from the IFU to ALU (the RF stage does not advance) which includes 174both of the previous two events. 175The RT_STALL is different than the sum of them though because cycles 176when both stalls are active will only be counted once. 177.It Li INSTR_REFETCH 178.Pq Event 18, Counter 1 179replay traps (other than uTLB) 180.It Li STORE_COND_COMPLETED 181.Pq Event 19, Counter 0 182Conditional stores completed. 183Counts all events, including failed stores. 184.It Li STORE_COND_FAILED 185.Pq Event 19, Counter 1 186Conditional store instruction that did not update memory. 187Note: While this event and the SC instruction count event can be configured to 188count in specific operating modes, the timing of the events is much 189different and the observed operating mode could change between them, 190causing some inaccuracy in the measured ratio. 191.It Li ICACHE_REQUESTS 192.Pq Event 20, Counter 0 193Note that this only counts PREFs that are actually attempted. 194PREFs to uncached addresses or ones with translation errors are not counted 195.It Li ICACHE_HIT 196.Pq Event 20, Counter 1 197Counts PREF instructions that hit in the cache 198.It Li L2_WRITEBACK 199.Pq Event 21, Counter 0 200Counts cache lines written back to memory due to replacement or cacheops. 201.It Li L2_ACCESS 202.Pq Event 21, Counter 1 203Number of accesses to L2 Cache. 204.It Li L2_MISS 205.Pq Event 22, Counter 0 206Number of accesses that missed in the L2 cache. 207.It Li L2_ERR_CORRECTED 208.Pq Event 22, Counter 1 209Single bit errors in L2 Cache that were detected and corrected. 210.It Li EXCEPTIONS 211.Pq Event 23, Counter 0 212Any type of exception taken. 213.It Li RF_CYCLES_STALLED 214.Pq Event 24, Counter 0 215Counts cycles where the LSU is in fixup and cannot accept a new 216instruction from the ALU. 217Fixups are replays within the LSU that occur when an instruction needs 218to re-access the cache or the DTLB. 219.It Li IFU_CYCLES_STALLED 220.Pq Event 25, Counter 0 221Counts the number of cycles where the fetch unit is not providing a 222valid instruction to the ALU. 223.It Li ALU_CYCLES_STALLED 224.Pq Event 25, Counter 1 225Counts the number of cycles where the ALU pipeline cannot advance. 226.It Li UNCACHED_LOAD 227.Pq Event 33, Counter 0 228Counts uncached and uncached accelerated loads. 229.It Li UNCACHED_STORE 230.Pq Event 33, Counter 1 231Counts uncached and uncached accelerated stores. 232.It Li CP2_REG_TO_REG_COMPLETED 233.Pq Event 35, Counter 0 234Co-processor 2 register to register instructions completed. 235.It Li MFTC_COMPLETED 236.Pq Event 35, Counter 1 237Co-processor 2 move to and from instructions as well as loads and stores. 238.It Li IC_BLOCKED_CYCLES 239.Pq Event 37, Counter 0 240Cycles when IFU stalls because an instruction miss caused the IFU not 241to have any runnable instructions. 242Ignores the stalls due to ITLB misses as well as the 4 cycles 243following a redirect. 244.It Li DC_BLOCKED_CYCLES 245.Pq Event 37, Counter 1 246Counts all cycles where integer pipeline waits on Load return data due 247to a D-cache miss. 248The LSU can signal a "long stall" on a D-cache misses, in which case 249the waiting TC might be rescheduled so other TCs can execute 250instructions till the data returns. 251.It Li L2_IMISS_STALL_CYCLES 252.Pq Event 38, Counter 0 253Cycles where the main pipeline is stalled waiting for a SYNC to complete. 254.It Li L2_DMISS_STALL_CYCLES 255.Pq Event 38, Counter 1 256Cycles where the main pipeline is stalled because of an index conflict 257in the Fill Store Buffer. 258.It Li DMISS_CYCLES 259.Pq Event 39, Counter 0 260Data miss is outstanding, but not necessarily stalling the pipeline. 261The difference between this and D$ miss stall cycles can show the gain 262from non-blocking cache misses. 263.It Li L2_MISS_CYCLES 264.Pq Event 39, Counter 1 265L2 miss is outstanding, but not necessarily stalling the pipeline. 266.It Li UNCACHED_BLOCK_CYCLES 267.Pq Event 40, Counter 0 268Cycles where the processor is stalled on an uncached fetch, load, or store. 269.It Li MDU_STALL_CYCLES 270.Pq Event 41, Counter 0 271Cycles where the processor is stalled on an uncached fetch, load, or store. 272.It Li FPU_STALL_CYCLES 273.Pq Event 41, Counter 1 274Counts all cycles where integer pipeline waits on FPU return data. 275.It Li CP2_STALL_CYCLES 276.Pq Event 42, Counter 0 277Counts all cycles where integer pipeline waits on CP2 return data. 278.It Li COREXTEND_STALL_CYCLES 279.Pq Event 42, Counter 1 280Counts all cycles where integer pipeline waits on CorExtend return data. 281.It Li ISPRAM_STALL_CYCLES 282.Pq Event 43, Counter 0 283Count all pipeline bubbles that are a result of multicycle ISPRAM 284access. 285Pipeline bubbles are defined as all cycles that IFU doesn't present an 286instruction to ALU. 287The four cycles after a redirect are not counted. 288.It Li DSPRAM_STALL_CYCLES 289.Pq Event 43, Counter 1 290Counts stall cycles created by an instruction waiting for access to DSPRAM. 291.It Li CACHE_STALL_CYCLES 292.Pq Event 44, Counter 0 293Counts all cycles the where pipeline is stalled due to CACHE 294instructions. 295Includes cycles where CACHE instructions themselves are 296stalled in the ALU, and cycles where CACHE instructions cause 297subsequent instructions to be stalled. 298.It Li LOAD_TO_USE_STALLS 299.Pq Event 45, Counter 0 300Counts all cycles where integer pipeline waits on Load return data. 301.It Li BASE_MISPRED_STALLS 302.Pq Event 45, Counter 1 303Counts stall cycles due to skewed ALU where the bypass to the address 304generation takes an extra cycle. 305.It Li CPO_READ_STALLS 306.Pq Event 46, Counter 0 307Counts all cycles where integer pipeline waits on return data from 308MFC0, RDHWR instructions. 309.It Li BRANCH_MISPRED_CYCLES 310.Pq Event 46, Counter 1 311This counts the number of cycles from a mispredicted branch until the 312next non-delay slot instruction executes. 313.It Li IFETCH_BUFFER_FULL 314.Pq Event 48, Counter 0 315Counts the number of times an instruction cache miss was detected, but 316both fill buffers were already allocated. 317.It Li FETCH_BUFFER_ALLOCATED 318.Pq Event 48, Counter 1 319Number of cycles where at least one of the IFU fill buffers is 320allocated (miss pending). 321.It Li EJTAG_ITRIGGER 322.Pq Event 49, Counter 0 323Number of times an EJTAG Instruction Trigger Point condition matched. 324.It Li EJTAG_DTRIGGER 325.Pq Event 49, Counter 1 326Number of times an EJTAG Data Trigger Point condition matched. 327.It Li FSB_LT_QUARTER 328.Pq Event 50, Counter 0 329Fill store buffer less than one quarter full. 330.It Li FSB_QUARTER_TO_HALF 331.Pq Event 50, Counter 1 332Fill store buffer between one quarter and one half full. 333.It Li FSB_GT_HALF 334.Pq Event 51, Counter 0 335Fill store buffer more than half full. 336.It Li FSB_FULL_PIPELINE_STALLS 337.Pq Event 51, Counter 1 338Cycles where the pipeline is stalled because the Fill-Store Buffer in LSU is full. 339.It Li LDQ_LT_QUARTER 340.Pq Event 52, Counter 0 341Load data queue less than one quarter full. 342.It Li LDQ_QUARTER_TO_HALF 343.Pq Event 52, Counter 1 344Load data queue between one quarter and one half full. 345.It Li LDQ_GT_HALF 346.Pq Event 53, Counter 0 347Load data queue more than one half full. 348.It Li LDQ_FULL_PIPELINE_STALLS 349.Pq Event 53, Counter 1 350Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full. 351.It Li WBB_LT_QUARTER 352.Pq Event 54, Counter 0 353Write back buffer less than one quarter full. 354.It Li WBB_QUARTER_TO_HALF 355.Pq Event 54, Counter 1 356Write back buffer between one quarter and one half full. 357.It Li WBB_GT_HALF 358.Pq Event 55, Counter 0 359Write back buffer more than one half full. 360.It Li WBB_FULL_PIPELINE_STALLS 361.Pq Event 55 Counter 1 362Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full. 363.It Li REQUEST_LATENCY 364.Pq Event 61, Counter 0 365Measures latency from miss detection until critical dword of response 366is returned, Only counts for cacheable reads. 367.It Li REQUEST_COUNT 368.Pq Event 61, Counter 1 369Counts number of cacheable read requests used for previous latency counter. 370.El 371.Ss Event Name Aliases 372The following table shows the mapping between the PMC-independent 373aliases supported by 374.Lb libpmc 375and the underlying hardware events used. 376.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" 377.It Em Alias Ta Em Event 378.It Li instructions Ta Li INSTR_EXECUTED 379.It Li branches Ta Li BRANCH_COMPLETED 380.It Li branch-mispredicts Ta Li BRANCH_MISPRED 381.El 382.Sh SEE ALSO 383.Xr pmc 3 , 384.Xr pmc.atom 3 , 385.Xr pmc.core 3 , 386.Xr pmc.iaf 3 , 387.Xr pmc.k7 3 , 388.Xr pmc.k8 3 , 389.Xr pmc.octeon 3 , 390.Xr pmc.soft 3 , 391.Xr pmc.tsc 3 , 392.Xr pmc_cpuinfo 3 , 393.Xr pmclog 3 , 394.Xr hwpmc 4 395.Sh HISTORY 396The 397.Nm pmc 398library first appeared in 399.Fx 6.0 . 400.Sh AUTHORS 401.An -nosplit 402The 403.Lb libpmc 404library was written by 405.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 406MIPS support was added by 407.An George Neville-Neil Aq Mt gnn@FreeBSD.org . 408