1 /* $NetBSD: mvsata_mv.c,v 1.8 2017/01/07 14:24:27 kiyohara Exp $ */
2 /*
3 * Copyright (c) 2008 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: mvsata_mv.c,v 1.8 2017/01/07 14:24:27 kiyohara Exp $");
30
31 #include <sys/param.h>
32 #include <sys/bus.h>
33 #include <sys/device.h>
34 #include <sys/errno.h>
35
36 #include <dev/ata/atareg.h>
37 #include <dev/ata/atavar.h>
38 #include <dev/ic/wdcvar.h>
39
40 #include <dev/ic/mvsatareg.h>
41 #include <dev/ic/mvsatavar.h>
42
43 #include <dev/marvell/marvellreg.h>
44 #include <dev/marvell/marvellvar.h>
45
46 #include "locators.h"
47
48
49 #define MVSATAHC_SIZE 0x8000
50
51 #define MVSATAHC_NWINDOW 4
52
53 #define MVSATAHC_MICR 0x20 /* Main Interrupt Cause */
54 #define MVSATAHC_MIMR 0x24 /* Main Interrupt Mask */
55 #define MVSATAHC_MI_SATAERR(p) (1 << ((p) * 2))
56 #define MVSATAHC_MI_SATADONE(p) (1 << (((p) * 2) + 1))
57 #define MVSATAHC_MI_SATADMADONE(p) (1 << ((p) + 4))
58 #define MVSATAHC_MI_SATACOALDONE (1 << 8)
59 #define MVSATAHC_WCR(n) (0x30 + (n) * 0x10) /* WinN Control */
60 #define MVSATAHC_WCR_WINEN (1 << 0)
61 #define MVSATAHC_WCR_TARGET(t) (((t) & 0xf) << 4)
62 #define MVSATAHC_WCR_ATTR(a) (((a) & 0xff) << 8)
63 #define MVSATAHC_WCR_SIZE(s) (((s) - 1) & 0xffff0000)
64 #define MVSATAHC_WBR(n) (0x34 + (n) * 0x10) /* WinN Base */
65 #define MVSATAHC_WBR_BASE(b) ((b) & 0xffff0000)
66
67
68 static int mvsatahc_match(device_t, cfdata_t, void *);
69 static void mvsatahc_attach(device_t, device_t, void *);
70
71 static int mvsatahc_intr(void *);
72
73 static void mvsatahc_enable_intr(struct mvsata_port *, int);
74 static void mvsatahc_wininit(struct mvsata_softc *, enum marvell_tags *);
75
76 CFATTACH_DECL_NEW(mvsata_gt, sizeof(struct mvsata_softc),
77 mvsatahc_match, mvsatahc_attach, NULL, NULL);
78 CFATTACH_DECL_NEW(mvsata_mbus, sizeof(struct mvsata_softc),
79 mvsatahc_match, mvsatahc_attach, NULL, NULL);
80
81
82 struct mvsata_product mvsata_products[] = {
83 #if 0
84 /* Discovery VI */
85 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV64660, ?, ?, gen2?, 0 },
86 #endif
87
88 /* Orion */
89 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5082, 1, 1, gen2e, 0 },
90 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5182, 1, 2, gen2e, 0 },
91 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6082, 1, 1, gen2e, 0 },
92
93 /* Kirkwood */
94 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6192, 1, 2, gen2e, 0 },
95 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6281, 1, 2, gen2e, 0 },
96 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6282, 1, 2, gen2e, 0 },
97
98 /* Discovery Innovation */
99 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78100, 1, 2, gen2e, 0 },
100 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78200, 1, 2, gen2e, 0 },
101
102 /* Dove */
103 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88AP510, 1, 1, gen2e, 0 },
104
105 /* Armada XP */
106 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78130, 1, 2, gen2e, 0 },
107 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78160, 1, 2, gen2e, 0 },
108 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78230, 1, 2, gen2e, 0 },
109 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78260, 1, 2, gen2e, 0 },
110 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78460, 1, 2, gen2e, 0 },
111
112 /* Armada 370 */
113 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV6707, 1, 2, gen2e, 0 },
114 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV6710, 1, 2, gen2e, 0 },
115 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV6W11, 1, 2, gen2e, 0 },
116 };
117
118
119 /* ARGSUSED */
120 static int
mvsatahc_match(device_t parent,cfdata_t match,void * aux)121 mvsatahc_match(device_t parent, cfdata_t match, void *aux)
122 {
123 struct marvell_attach_args *mva = aux;
124 int i;
125
126 if (strcmp(mva->mva_name, match->cf_name) != 0)
127 return 0;
128 if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
129 mva->mva_irq == MVA_IRQ_DEFAULT)
130 return 0;
131
132 for (i = 0; i < __arraycount(mvsata_products); i++)
133 if (mva->mva_model == mvsata_products[i].model) {
134 mva->mva_size = MVSATAHC_SIZE;
135 return 1;
136 }
137 return 0;
138 }
139
140 /* ARGSUSED */
141 static void
mvsatahc_attach(device_t parent,device_t self,void * aux)142 mvsatahc_attach(device_t parent, device_t self, void *aux)
143 {
144 struct mvsata_softc *sc = device_private(self);
145 struct marvell_attach_args *mva = aux;
146 uint32_t mask;
147 int port, i;
148
149 aprint_normal(": Marvell Serial-ATA Host Controller (SATAHC)\n");
150 aprint_naive("\n");
151
152 sc->sc_wdcdev.sc_atac.atac_dev = self;
153 sc->sc_model = mva->mva_model;
154 sc->sc_iot = mva->mva_iot;
155 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
156 mva->mva_size, &sc->sc_ioh)) {
157 aprint_error_dev(self, "can't map registers\n");
158 return;
159 }
160 sc->sc_dmat = mva->mva_dmat;
161 sc->sc_enable_intr = mvsatahc_enable_intr;
162
163 mvsatahc_wininit(sc, mva->mva_tags);
164
165 for (i = 0; i < __arraycount(mvsata_products); i++)
166 if (mva->mva_model == mvsata_products[i].model)
167 break;
168 KASSERT(i < __arraycount(mvsata_products));
169
170 if (mvsata_attach(sc, &mvsata_products[i], NULL, NULL, 0) != 0)
171 return;
172
173 marvell_intr_establish(mva->mva_irq, IPL_BIO, mvsatahc_intr, sc);
174 mask = 0;
175 for (port = 0; port < sc->sc_port; port++)
176 mask |=
177 MVSATAHC_MI_SATAERR(port) |
178 MVSATAHC_MI_SATADONE(port);
179 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR, mask);
180 }
181
182 static int
mvsatahc_intr(void * arg)183 mvsatahc_intr(void *arg)
184 {
185 struct mvsata_softc *sc = (struct mvsata_softc *)arg;
186 struct mvsata_hc *mvhc = &sc->sc_hcs[0];
187 uint32_t cause, handled = 0;
188
189 cause = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MICR);
190 if (cause & MVSATAHC_MI_SATAERR(0))
191 handled |= mvsata_error(mvhc->hc_ports[0]);
192 if (cause & MVSATAHC_MI_SATAERR(1))
193 handled |= mvsata_error(mvhc->hc_ports[1]);
194 if (cause & (MVSATAHC_MI_SATADONE(0) | MVSATAHC_MI_SATADONE(1)))
195 handled |= mvsata_intr(mvhc);
196
197 return handled;
198 }
199
200
201 static void
mvsatahc_enable_intr(struct mvsata_port * mvport,int on)202 mvsatahc_enable_intr(struct mvsata_port *mvport, int on)
203 {
204 struct mvsata_softc *sc =
205 device_private(mvport->port_ata_channel.ch_atac->atac_dev);
206 uint32_t mask;
207
208 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR);
209 if (on)
210 mask |= MVSATAHC_MI_SATADONE(mvport->port);
211 else
212 mask &= ~MVSATAHC_MI_SATADONE(mvport->port);
213 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR, mask);
214 }
215
216 static void
mvsatahc_wininit(struct mvsata_softc * sc,enum marvell_tags * tags)217 mvsatahc_wininit(struct mvsata_softc *sc, enum marvell_tags *tags)
218 {
219 device_t pdev = device_parent(sc->sc_wdcdev.sc_atac.atac_dev);
220 uint64_t base;
221 uint32_t size;
222 int window, target, attr, rv, i;
223
224 for (window = 0, i = 0;
225 tags[i] != MARVELL_TAG_UNDEFINED && window < MVSATAHC_NWINDOW;
226 i++) {
227 rv = marvell_winparams_by_tag(pdev, tags[i],
228 &target, &attr, &base, &size);
229 if (rv != 0 || size == 0)
230 continue;
231 if (base > 0xffffffffULL) {
232 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
233 "tag %d address 0x%llx not support\n",
234 tags[i], base);
235 continue;
236 }
237
238 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
239 MVSATAHC_WCR(window),
240 MVSATAHC_WCR_WINEN |
241 MVSATAHC_WCR_TARGET(target) |
242 MVSATAHC_WCR_ATTR(attr) |
243 MVSATAHC_WCR_SIZE(size));
244 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
245 MVSATAHC_WBR(window), MVSATAHC_WBR_BASE(base));
246 window++;
247 }
248 for (; window < MVSATAHC_NWINDOW; window++)
249 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
250 MVSATAHC_WCR(window), 0);
251 }
252