1 /*-
2 * Copyright (c) 2006-2007 Bruce M. Simpson.
3 * Copyright (c) 2003-2004 Juli Mallett.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /*
29 * Simple driver for the 32-bit interval counter built in to all
30 * MIPS32 CPUs.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/rman.h>
43 #include <sys/power.h>
44 #include <sys/smp.h>
45 #include <sys/time.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
48
49 #include <machine/hwfunc.h>
50 #include <machine/clock.h>
51 #include <machine/locore.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <mips/rmi/interrupt.h>
55
56 uint64_t counter_freq;
57
58 struct timecounter *platform_timecounter;
59
60 static DPCPU_DEFINE(uint32_t, cycles_per_tick);
61 static uint32_t cycles_per_usec;
62
63 static DPCPU_DEFINE(volatile uint32_t, counter_upper);
64 static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
65 static DPCPU_DEFINE(uint32_t, compare_ticks);
66 static DPCPU_DEFINE(uint32_t, lost_ticks);
67
68 struct clock_softc {
69 int intr_rid;
70 struct resource *intr_res;
71 void *intr_handler;
72 struct timecounter tc;
73 struct eventtimer et;
74 };
75 static struct clock_softc *softc;
76
77 /*
78 * Device methods
79 */
80 static int clock_probe(device_t);
81 static void clock_identify(driver_t *, device_t);
82 static int clock_attach(device_t);
83 static unsigned counter_get_timecount(struct timecounter *tc);
84
85 void
mips_timer_early_init(uint64_t clock_hz)86 mips_timer_early_init(uint64_t clock_hz)
87 {
88 /* Initialize clock early so that we can use DELAY sooner */
89 counter_freq = clock_hz;
90 cycles_per_usec = (clock_hz / (1000 * 1000));
91 }
92
93 void
platform_initclocks(void)94 platform_initclocks(void)
95 {
96
97 if (platform_timecounter != NULL)
98 tc_init(platform_timecounter);
99 }
100
101 static uint64_t
tick_ticker(void)102 tick_ticker(void)
103 {
104 uint64_t ret;
105 uint32_t ticktock;
106 uint32_t t_lower_last, t_upper;
107
108 /*
109 * Disable preemption because we are working with cpu specific data.
110 */
111 critical_enter();
112
113 /*
114 * Note that even though preemption is disabled, interrupts are
115 * still enabled. In particular there is a race with clock_intr()
116 * reading the values of 'counter_upper' and 'counter_lower_last'.
117 *
118 * XXX this depends on clock_intr() being executed periodically
119 * so that 'counter_upper' and 'counter_lower_last' are not stale.
120 */
121 do {
122 t_upper = DPCPU_GET(counter_upper);
123 t_lower_last = DPCPU_GET(counter_lower_last);
124 } while (t_upper != DPCPU_GET(counter_upper));
125
126 ticktock = mips_rd_count();
127
128 critical_exit();
129
130 /* COUNT register wrapped around */
131 if (ticktock < t_lower_last)
132 t_upper++;
133
134 ret = ((uint64_t)t_upper << 32) | ticktock;
135 return (ret);
136 }
137
138 void
mips_timer_init_params(uint64_t platform_counter_freq,int double_count)139 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
140 {
141
142 /*
143 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
144 * function should be called before cninit.
145 */
146 counter_freq = platform_counter_freq;
147 /*
148 * XXX: Some MIPS32 cores update the Count register only every two
149 * pipeline cycles.
150 * We know this because of status registers in CP0, make it automatic.
151 */
152 if (double_count != 0)
153 counter_freq /= 2;
154
155 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
156 set_cputicker(tick_ticker, counter_freq, 1);
157 }
158
159 static int
sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)160 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
161 {
162 int error;
163 uint64_t freq;
164
165 if (softc == NULL)
166 return (EOPNOTSUPP);
167 freq = counter_freq;
168 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
169 if (error == 0 && req->newptr != NULL) {
170 counter_freq = freq;
171 softc->et.et_frequency = counter_freq;
172 softc->tc.tc_frequency = counter_freq;
173 }
174 return (error);
175 }
176
177 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
178 NULL, 0, sysctl_machdep_counter_freq, "QU",
179 "Timecounter frequency in Hz");
180
181 static unsigned
counter_get_timecount(struct timecounter * tc)182 counter_get_timecount(struct timecounter *tc)
183 {
184
185 return (mips_rd_count());
186 }
187
188 /*
189 * Wait for about n microseconds (at least!).
190 */
191 void
DELAY(int n)192 DELAY(int n)
193 {
194 uint32_t cur, last, delta, usecs;
195
196 /*
197 * This works by polling the timer and counting the number of
198 * microseconds that go by.
199 */
200 last = mips_rd_count();
201 delta = usecs = 0;
202
203 while (n > usecs) {
204 cur = mips_rd_count();
205
206 /* Check to see if the timer has wrapped around. */
207 if (cur < last)
208 delta += cur + (0xffffffff - last) + 1;
209 else
210 delta += cur - last;
211
212 last = cur;
213
214 if (delta >= cycles_per_usec) {
215 usecs += delta / cycles_per_usec;
216 delta %= cycles_per_usec;
217 }
218 }
219 }
220
221 static int
clock_start(struct eventtimer * et,sbintime_t first,sbintime_t period)222 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
223 {
224 uint32_t fdiv, div, next;
225
226 if (period != 0)
227 div = (et->et_frequency * period) >> 32;
228 else
229 div = 0;
230 if (first != 0)
231 fdiv = (et->et_frequency * first) >> 32;
232 else
233 fdiv = div;
234 DPCPU_SET(cycles_per_tick, div);
235 next = mips_rd_count() + fdiv;
236 DPCPU_SET(compare_ticks, next);
237 mips_wr_compare(next);
238 return (0);
239 }
240
241 static int
clock_stop(struct eventtimer * et)242 clock_stop(struct eventtimer *et)
243 {
244
245 DPCPU_SET(cycles_per_tick, 0);
246 mips_wr_compare(0xffffffff);
247 return (0);
248 }
249
250 /*
251 * Device section of file below
252 */
253 static int
clock_intr(void * arg)254 clock_intr(void *arg)
255 {
256 struct clock_softc *sc = (struct clock_softc *)arg;
257 uint32_t cycles_per_tick;
258 uint32_t count, compare_last, compare_next, lost_ticks;
259
260 cycles_per_tick = DPCPU_GET(cycles_per_tick);
261 /*
262 * Set next clock edge.
263 */
264 count = mips_rd_count();
265 compare_last = DPCPU_GET(compare_ticks);
266 if (cycles_per_tick > 0) {
267 compare_next = count + cycles_per_tick;
268 DPCPU_SET(compare_ticks, compare_next);
269 mips_wr_compare(compare_next);
270 } else /* In one-shot mode timer should be stopped after the event. */
271 mips_wr_compare(0xffffffff);
272
273 /* COUNT register wrapped around */
274 if (count < DPCPU_GET(counter_lower_last)) {
275 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
276 }
277 DPCPU_SET(counter_lower_last, count);
278
279 if (cycles_per_tick > 0) {
280
281 /*
282 * Account for the "lost time" between when the timer interrupt
283 * fired and when 'clock_intr' actually started executing.
284 */
285 lost_ticks = DPCPU_GET(lost_ticks);
286 lost_ticks += count - compare_last;
287
288 /*
289 * If the COUNT and COMPARE registers are no longer in sync
290 * then make up some reasonable value for the 'lost_ticks'.
291 *
292 * This could happen, for e.g., after we resume normal
293 * operations after exiting the debugger.
294 */
295 if (lost_ticks > 2 * cycles_per_tick)
296 lost_ticks = cycles_per_tick;
297
298 while (lost_ticks >= cycles_per_tick) {
299 if (sc->et.et_active)
300 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
301 lost_ticks -= cycles_per_tick;
302 }
303 DPCPU_SET(lost_ticks, lost_ticks);
304 }
305 if (sc->et.et_active)
306 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
307 return (FILTER_HANDLED);
308 }
309
310 static int
clock_probe(device_t dev)311 clock_probe(device_t dev)
312 {
313
314 if (device_get_unit(dev) != 0)
315 panic("can't attach more clocks");
316
317 device_set_desc(dev, "Generic MIPS32 ticker");
318 return (BUS_PROBE_NOWILDCARD);
319 }
320
321 static void
clock_identify(driver_t * drv,device_t parent)322 clock_identify(driver_t * drv, device_t parent)
323 {
324
325 BUS_ADD_CHILD(parent, 0, "clock", 0);
326 }
327
328 static int
clock_attach(device_t dev)329 clock_attach(device_t dev)
330 {
331 struct clock_softc *sc;
332
333 softc = sc = device_get_softc(dev);
334 cpu_establish_hardintr("compare", clock_intr, NULL,
335 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
336
337 sc->tc.tc_get_timecount = counter_get_timecount;
338 sc->tc.tc_counter_mask = 0xffffffff;
339 sc->tc.tc_frequency = counter_freq;
340 sc->tc.tc_name = "MIPS32";
341 sc->tc.tc_quality = 800;
342 sc->tc.tc_priv = sc;
343 tc_init(&sc->tc);
344 sc->et.et_name = "MIPS32";
345 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
346 ET_FLAGS_PERCPU;
347 sc->et.et_quality = 800;
348 sc->et.et_frequency = counter_freq;
349 sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
350 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
351 sc->et.et_start = clock_start;
352 sc->et.et_stop = clock_stop;
353 sc->et.et_priv = sc;
354 et_register(&sc->et);
355 return (0);
356 }
357
358 static device_method_t clock_methods[] = {
359 /* Device interface */
360 DEVMETHOD(device_probe, clock_probe),
361 DEVMETHOD(device_identify, clock_identify),
362 DEVMETHOD(device_attach, clock_attach),
363 DEVMETHOD(device_detach, bus_generic_detach),
364 DEVMETHOD(device_shutdown, bus_generic_shutdown),
365
366 {0, 0}
367 };
368
369 static driver_t clock_driver = {
370 "clock",
371 clock_methods,
372 sizeof(struct clock_softc),
373 };
374
375 static devclass_t clock_devclass;
376
377 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
378