1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2022 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #define IN_TARGET_CODE 1
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "backend.h"
26 #include "target.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "df.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "stringpool.h"
33 #include "attribs.h"
34 #include "insn-config.h"
35 #include "emit-rtl.h"
36 #include "recog.h"
37 #include "diagnostic-core.h"
38 #include "alias.h"
39 #include "stor-layout.h"
40 #include "varasm.h"
41 #include "calls.h"
42 #include "output.h"
43 #include "insn-attr.h"
44 #include "explow.h"
45 #include "expr.h"
46 #include "tm-constrs.h"
47 #include "builtins.h"
48 #include "opts.h"
49
50 /* This file should be included last. */
51 #include "target-def.h"
52
53 /* Array of valid operand punctuation characters. */
54 static char m32r_punct_chars[256];
55
56 /* Machine-specific symbol_ref flags. */
57 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
58 #define SYMBOL_REF_MODEL(X) \
59 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
60
61 /* For string literals, etc. */
62 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
63
64 /* Forward declaration. */
65 static void m32r_option_override (void);
66 static void init_reg_tables (void);
67 static void block_move_call (rtx, rtx, rtx);
68 static int m32r_is_insn (rtx);
69 static bool m32r_legitimate_address_p (machine_mode, rtx, bool);
70 static rtx m32r_legitimize_address (rtx, rtx, machine_mode);
71 static bool m32r_mode_dependent_address_p (const_rtx, addr_space_t);
72 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
73 static void m32r_print_operand (FILE *, rtx, int);
74 static void m32r_print_operand_address (FILE *, machine_mode, rtx);
75 static bool m32r_print_operand_punct_valid_p (unsigned char code);
76 static void m32r_output_function_prologue (FILE *);
77 static void m32r_output_function_epilogue (FILE *);
78
79 static void m32r_file_start (void);
80
81 static int m32r_adjust_priority (rtx_insn *, int);
82 static int m32r_issue_rate (void);
83
84 static void m32r_encode_section_info (tree, rtx, int);
85 static bool m32r_in_small_data_p (const_tree);
86 static bool m32r_return_in_memory (const_tree, const_tree);
87 static rtx m32r_function_value (const_tree, const_tree, bool);
88 static rtx m32r_libcall_value (machine_mode, const_rtx);
89 static bool m32r_function_value_regno_p (const unsigned int);
90 static void m32r_setup_incoming_varargs (cumulative_args_t,
91 const function_arg_info &,
92 int *, int);
93 static void init_idents (void);
94 static bool m32r_rtx_costs (rtx, machine_mode, int, int, int *, bool speed);
95 static int m32r_memory_move_cost (machine_mode, reg_class_t, bool);
96 static bool m32r_pass_by_reference (cumulative_args_t,
97 const function_arg_info &arg);
98 static int m32r_arg_partial_bytes (cumulative_args_t,
99 const function_arg_info &);
100 static rtx m32r_function_arg (cumulative_args_t, const function_arg_info &);
101 static void m32r_function_arg_advance (cumulative_args_t,
102 const function_arg_info &);
103 static bool m32r_can_eliminate (const int, const int);
104 static void m32r_conditional_register_usage (void);
105 static void m32r_trampoline_init (rtx, tree, rtx);
106 static bool m32r_legitimate_constant_p (machine_mode, rtx);
107 static bool m32r_attribute_identifier (const_tree);
108 static bool m32r_hard_regno_mode_ok (unsigned int, machine_mode);
109 static bool m32r_modes_tieable_p (machine_mode, machine_mode);
110 static HOST_WIDE_INT m32r_starting_frame_offset (void);
111
112 /* M32R specific attributes. */
113
114 static const struct attribute_spec m32r_attribute_table[] =
115 {
116 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
117 affects_type_identity, handler, exclude } */
118 { "interrupt", 0, 0, true, false, false, false, NULL, NULL },
119 { "model", 1, 1, true, false, false, false, m32r_handle_model_attribute,
120 NULL },
121 { NULL, 0, 0, false, false, false, false, NULL, NULL }
122 };
123
124 /* Initialize the GCC target structure. */
125 #undef TARGET_ATTRIBUTE_TABLE
126 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
127 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
128 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P m32r_attribute_identifier
129
130 #undef TARGET_LRA_P
131 #define TARGET_LRA_P hook_bool_void_false
132
133 #undef TARGET_LEGITIMATE_ADDRESS_P
134 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
135 #undef TARGET_LEGITIMIZE_ADDRESS
136 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
137 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
138 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
139
140 #undef TARGET_ASM_ALIGNED_HI_OP
141 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
142 #undef TARGET_ASM_ALIGNED_SI_OP
143 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
144
145 #undef TARGET_PRINT_OPERAND
146 #define TARGET_PRINT_OPERAND m32r_print_operand
147 #undef TARGET_PRINT_OPERAND_ADDRESS
148 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
149 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
150 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
151
152 #undef TARGET_ASM_FUNCTION_PROLOGUE
153 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
154 #undef TARGET_ASM_FUNCTION_EPILOGUE
155 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
156
157 #undef TARGET_ASM_FILE_START
158 #define TARGET_ASM_FILE_START m32r_file_start
159
160 #undef TARGET_SCHED_ADJUST_PRIORITY
161 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
162 #undef TARGET_SCHED_ISSUE_RATE
163 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
164
165 #undef TARGET_OPTION_OVERRIDE
166 #define TARGET_OPTION_OVERRIDE m32r_option_override
167
168 #undef TARGET_ENCODE_SECTION_INFO
169 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
170 #undef TARGET_IN_SMALL_DATA_P
171 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
172
173
174 #undef TARGET_MEMORY_MOVE_COST
175 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
176 #undef TARGET_RTX_COSTS
177 #define TARGET_RTX_COSTS m32r_rtx_costs
178 #undef TARGET_ADDRESS_COST
179 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
180
181 #undef TARGET_PROMOTE_PROTOTYPES
182 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
183 #undef TARGET_RETURN_IN_MEMORY
184 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
185
186 #undef TARGET_FUNCTION_VALUE
187 #define TARGET_FUNCTION_VALUE m32r_function_value
188 #undef TARGET_LIBCALL_VALUE
189 #define TARGET_LIBCALL_VALUE m32r_libcall_value
190 #undef TARGET_FUNCTION_VALUE_REGNO_P
191 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
192
193 #undef TARGET_SETUP_INCOMING_VARARGS
194 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
195 #undef TARGET_MUST_PASS_IN_STACK
196 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
197 #undef TARGET_PASS_BY_REFERENCE
198 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
199 #undef TARGET_ARG_PARTIAL_BYTES
200 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
201 #undef TARGET_FUNCTION_ARG
202 #define TARGET_FUNCTION_ARG m32r_function_arg
203 #undef TARGET_FUNCTION_ARG_ADVANCE
204 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
205
206 #undef TARGET_CAN_ELIMINATE
207 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
208
209 #undef TARGET_CONDITIONAL_REGISTER_USAGE
210 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
211
212 #undef TARGET_TRAMPOLINE_INIT
213 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
214
215 #undef TARGET_LEGITIMATE_CONSTANT_P
216 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
217
218 #undef TARGET_HARD_REGNO_MODE_OK
219 #define TARGET_HARD_REGNO_MODE_OK m32r_hard_regno_mode_ok
220
221 #undef TARGET_MODES_TIEABLE_P
222 #define TARGET_MODES_TIEABLE_P m32r_modes_tieable_p
223
224 #undef TARGET_CONSTANT_ALIGNMENT
225 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
226
227 #undef TARGET_STARTING_FRAME_OFFSET
228 #define TARGET_STARTING_FRAME_OFFSET m32r_starting_frame_offset
229
230 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
231 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
232
233 struct gcc_target targetm = TARGET_INITIALIZER;
234
235 /* Called by m32r_option_override to initialize various things. */
236
237 void
m32r_init(void)238 m32r_init (void)
239 {
240 init_reg_tables ();
241
242 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
243 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
244 m32r_punct_chars['#'] = 1;
245 m32r_punct_chars['@'] = 1; /* ??? no longer used */
246
247 /* Provide default value if not specified. */
248 if (!OPTION_SET_P (g_switch_value))
249 g_switch_value = SDATA_DEFAULT_SIZE;
250 }
251
252 static void
m32r_option_override(void)253 m32r_option_override (void)
254 {
255 /* These need to be done at start up.
256 It's convenient to do them here. */
257 m32r_init ();
258 SUBTARGET_OVERRIDE_OPTIONS;
259 }
260
261 /* Vectors to keep interesting information about registers where it can easily
262 be got. We use to use the actual mode value as the bit number, but there
263 is (or may be) more than 32 modes now. Instead we use two tables: one
264 indexed by hard register number, and one indexed by mode. */
265
266 /* The purpose of m32r_mode_class is to shrink the range of modes so that
267 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
268 mapped into one m32r_mode_class mode. */
269
270 enum m32r_mode_class
271 {
272 C_MODE,
273 S_MODE, D_MODE, T_MODE, O_MODE,
274 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
275 };
276
277 /* Modes for condition codes. */
278 #define C_MODES (1 << (int) C_MODE)
279
280 /* Modes for single-word and smaller quantities. */
281 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
282
283 /* Modes for double-word and smaller quantities. */
284 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
285
286 /* Modes for quad-word and smaller quantities. */
287 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
288
289 /* Modes for accumulators. */
290 #define A_MODES (1 << (int) A_MODE)
291
292 /* Value is 1 if register/mode pair is acceptable on arc. */
293
294 static const unsigned int m32r_hard_regno_modes[FIRST_PSEUDO_REGISTER] =
295 {
296 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
297 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
298 S_MODES, C_MODES, A_MODES, A_MODES
299 };
300
301 static unsigned int m32r_mode_class [NUM_MACHINE_MODES];
302
303 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
304
305 static void
init_reg_tables(void)306 init_reg_tables (void)
307 {
308 int i;
309
310 for (i = 0; i < NUM_MACHINE_MODES; i++)
311 {
312 machine_mode m = (machine_mode) i;
313
314 switch (GET_MODE_CLASS (m))
315 {
316 case MODE_INT:
317 case MODE_PARTIAL_INT:
318 case MODE_COMPLEX_INT:
319 if (GET_MODE_SIZE (m) <= 4)
320 m32r_mode_class[i] = 1 << (int) S_MODE;
321 else if (GET_MODE_SIZE (m) == 8)
322 m32r_mode_class[i] = 1 << (int) D_MODE;
323 else if (GET_MODE_SIZE (m) == 16)
324 m32r_mode_class[i] = 1 << (int) T_MODE;
325 else if (GET_MODE_SIZE (m) == 32)
326 m32r_mode_class[i] = 1 << (int) O_MODE;
327 else
328 m32r_mode_class[i] = 0;
329 break;
330 case MODE_FLOAT:
331 case MODE_COMPLEX_FLOAT:
332 if (GET_MODE_SIZE (m) <= 4)
333 m32r_mode_class[i] = 1 << (int) SF_MODE;
334 else if (GET_MODE_SIZE (m) == 8)
335 m32r_mode_class[i] = 1 << (int) DF_MODE;
336 else if (GET_MODE_SIZE (m) == 16)
337 m32r_mode_class[i] = 1 << (int) TF_MODE;
338 else if (GET_MODE_SIZE (m) == 32)
339 m32r_mode_class[i] = 1 << (int) OF_MODE;
340 else
341 m32r_mode_class[i] = 0;
342 break;
343 case MODE_CC:
344 m32r_mode_class[i] = 1 << (int) C_MODE;
345 break;
346 default:
347 m32r_mode_class[i] = 0;
348 break;
349 }
350 }
351
352 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
353 {
354 if (GPR_P (i))
355 m32r_regno_reg_class[i] = GENERAL_REGS;
356 else if (i == ARG_POINTER_REGNUM)
357 m32r_regno_reg_class[i] = GENERAL_REGS;
358 else
359 m32r_regno_reg_class[i] = NO_REGS;
360 }
361 }
362
363 /* M32R specific attribute support.
364
365 interrupt - for interrupt functions
366
367 model - select code model used to access object
368
369 small: addresses use 24 bits, use bl to make calls
370 medium: addresses use 32 bits, use bl to make calls
371 large: addresses use 32 bits, use seth/add3/jl to make calls
372
373 Grep for MODEL in m32r.h for more info. */
374
375 static tree small_ident1;
376 static tree small_ident2;
377 static tree medium_ident1;
378 static tree medium_ident2;
379 static tree large_ident1;
380 static tree large_ident2;
381
382 static void
init_idents(void)383 init_idents (void)
384 {
385 if (small_ident1 == 0)
386 {
387 small_ident1 = get_identifier ("small");
388 small_ident2 = get_identifier ("__small__");
389 medium_ident1 = get_identifier ("medium");
390 medium_ident2 = get_identifier ("__medium__");
391 large_ident1 = get_identifier ("large");
392 large_ident2 = get_identifier ("__large__");
393 }
394 }
395
396 /* Handle an "model" attribute; arguments as in
397 struct attribute_spec.handler. */
398 static tree
m32r_handle_model_attribute(tree * node ATTRIBUTE_UNUSED,tree name,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)399 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
400 tree args, int flags ATTRIBUTE_UNUSED,
401 bool *no_add_attrs)
402 {
403 tree arg;
404
405 init_idents ();
406 arg = TREE_VALUE (args);
407
408 if (arg != small_ident1
409 && arg != small_ident2
410 && arg != medium_ident1
411 && arg != medium_ident2
412 && arg != large_ident1
413 && arg != large_ident2)
414 {
415 warning (OPT_Wattributes, "invalid argument of %qs attribute",
416 IDENTIFIER_POINTER (name));
417 *no_add_attrs = true;
418 }
419
420 return NULL_TREE;
421 }
422
423 static bool
m32r_attribute_identifier(const_tree name)424 m32r_attribute_identifier (const_tree name)
425 {
426 return strcmp (IDENTIFIER_POINTER (name), "model") == 0
427 || strcmp (IDENTIFIER_POINTER (name), "__model__") == 0;
428 }
429
430 /* Encode section information of DECL, which is either a VAR_DECL,
431 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
432
433 For the M32R we want to record:
434
435 - whether the object lives in .sdata/.sbss.
436 - what code model should be used to access the object
437 */
438
439 static void
m32r_encode_section_info(tree decl,rtx rtl,int first)440 m32r_encode_section_info (tree decl, rtx rtl, int first)
441 {
442 int extra_flags = 0;
443 tree model_attr;
444 enum m32r_model model;
445
446 default_encode_section_info (decl, rtl, first);
447
448 if (!DECL_P (decl))
449 return;
450
451 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
452 if (model_attr)
453 {
454 tree id;
455
456 init_idents ();
457
458 id = TREE_VALUE (TREE_VALUE (model_attr));
459
460 if (id == small_ident1 || id == small_ident2)
461 model = M32R_MODEL_SMALL;
462 else if (id == medium_ident1 || id == medium_ident2)
463 model = M32R_MODEL_MEDIUM;
464 else if (id == large_ident1 || id == large_ident2)
465 model = M32R_MODEL_LARGE;
466 else
467 gcc_unreachable (); /* shouldn't happen */
468 }
469 else
470 {
471 if (TARGET_MODEL_SMALL)
472 model = M32R_MODEL_SMALL;
473 else if (TARGET_MODEL_MEDIUM)
474 model = M32R_MODEL_MEDIUM;
475 else if (TARGET_MODEL_LARGE)
476 model = M32R_MODEL_LARGE;
477 else
478 gcc_unreachable (); /* shouldn't happen */
479 }
480 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
481
482 if (extra_flags)
483 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
484 }
485
486 /* Only mark the object as being small data area addressable if
487 it hasn't been explicitly marked with a code model.
488
489 The user can explicitly put an object in the small data area with the
490 section attribute. If the object is in sdata/sbss and marked with a
491 code model do both [put the object in .sdata and mark it as being
492 addressed with a specific code model - don't mark it as being addressed
493 with an SDA reloc though]. This is ok and might be useful at times. If
494 the object doesn't fit the linker will give an error. */
495
496 static bool
m32r_in_small_data_p(const_tree decl)497 m32r_in_small_data_p (const_tree decl)
498 {
499 const char *section;
500
501 if (TREE_CODE (decl) != VAR_DECL)
502 return false;
503
504 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
505 return false;
506
507 section = DECL_SECTION_NAME (decl);
508 if (section)
509 {
510 if (strcmp (section, ".sdata") == 0 || strcmp (section, ".sbss") == 0)
511 return true;
512 }
513 else
514 {
515 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
516 {
517 int size = int_size_in_bytes (TREE_TYPE (decl));
518
519 if (size > 0 && size <= g_switch_value)
520 return true;
521 }
522 }
523
524 return false;
525 }
526
527 /* Do anything needed before RTL is emitted for each function. */
528
529 void
m32r_init_expanders(void)530 m32r_init_expanders (void)
531 {
532 /* ??? At one point there was code here. The function is left in
533 to make it easy to experiment. */
534 }
535
536 bool
call_operand(rtx op,machine_mode mode)537 call_operand (rtx op, machine_mode mode)
538 {
539 if (!MEM_P (op))
540 return 0;
541 op = XEXP (op, 0);
542 return call_address_operand (op, mode);
543 }
544
545 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
546
547 bool
small_data_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)548 small_data_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
549 {
550 if (! TARGET_SDATA_USE)
551 return 0;
552
553 if (GET_CODE (op) == SYMBOL_REF)
554 return SYMBOL_REF_SMALL_P (op);
555
556 if (GET_CODE (op) == CONST
557 && GET_CODE (XEXP (op, 0)) == PLUS
558 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
559 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
560 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
561
562 return 0;
563 }
564
565 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
566
567 int
addr24_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)568 addr24_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
569 {
570 rtx sym;
571
572 if (flag_pic)
573 return 0;
574
575 if (GET_CODE (op) == LABEL_REF)
576 return TARGET_ADDR24;
577
578 if (GET_CODE (op) == SYMBOL_REF)
579 sym = op;
580 else if (GET_CODE (op) == CONST
581 && GET_CODE (XEXP (op, 0)) == PLUS
582 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
583 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
584 sym = XEXP (XEXP (op, 0), 0);
585 else
586 return 0;
587
588 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
589 return 1;
590
591 if (TARGET_ADDR24
592 && (CONSTANT_POOL_ADDRESS_P (sym)
593 || LIT_NAME_P (XSTR (sym, 0))))
594 return 1;
595
596 return 0;
597 }
598
599 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
600
601 int
addr32_operand(rtx op,machine_mode mode)602 addr32_operand (rtx op, machine_mode mode)
603 {
604 rtx sym;
605
606 if (GET_CODE (op) == LABEL_REF)
607 return TARGET_ADDR32;
608
609 if (GET_CODE (op) == SYMBOL_REF)
610 sym = op;
611 else if (GET_CODE (op) == CONST
612 && GET_CODE (XEXP (op, 0)) == PLUS
613 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
614 && CONST_INT_P (XEXP (XEXP (op, 0), 1))
615 && ! flag_pic)
616 sym = XEXP (XEXP (op, 0), 0);
617 else
618 return 0;
619
620 return (! addr24_operand (sym, mode)
621 && ! small_data_operand (sym, mode));
622 }
623
624 /* Return 1 if OP is a function that can be called with the `bl' insn. */
625
626 int
call26_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)627 call26_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
628 {
629 if (flag_pic)
630 return 1;
631
632 if (GET_CODE (op) == SYMBOL_REF)
633 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
634
635 return TARGET_CALL26;
636 }
637
638 /* Return 1 if OP is a DImode const we want to handle inline.
639 This must match the code in the movdi pattern.
640 It is used by the 'G' constraint. */
641
642 int
easy_di_const(rtx op)643 easy_di_const (rtx op)
644 {
645 rtx high_rtx, low_rtx;
646 HOST_WIDE_INT high, low;
647
648 split_double (op, &high_rtx, &low_rtx);
649 high = INTVAL (high_rtx);
650 low = INTVAL (low_rtx);
651 /* Pick constants loadable with 2 16-bit `ldi' insns. */
652 if (high >= -128 && high <= 127
653 && low >= -128 && low <= 127)
654 return 1;
655 return 0;
656 }
657
658 /* Return 1 if OP is a DFmode const we want to handle inline.
659 This must match the code in the movdf pattern.
660 It is used by the 'H' constraint. */
661
662 int
easy_df_const(rtx op)663 easy_df_const (rtx op)
664 {
665 long l[2];
666
667 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
668 if (l[0] == 0 && l[1] == 0)
669 return 1;
670 if ((l[0] & 0xffff) == 0 && l[1] == 0)
671 return 1;
672 return 0;
673 }
674
675 /* Return 1 if OP is (mem (reg ...)).
676 This is used in insn length calcs. */
677
678 bool
memreg_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)679 memreg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
680 {
681 return MEM_P (op) && REG_P (XEXP (op, 0));
682 }
683
684 /* Return nonzero if ARG must be passed by indirect reference. */
685
686 static bool
m32r_pass_by_reference(cumulative_args_t,const function_arg_info & arg)687 m32r_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
688 {
689 int size = arg.type_size_in_bytes ();
690 return (size < 0 || size > 8);
691 }
692
693 /* Comparisons. */
694
695 /* X and Y are two things to compare using CODE. Emit the compare insn and
696 return the rtx for compare [arg0 of the if_then_else].
697 If need_compare is true then the comparison insn must be generated, rather
698 than being subsumed into the following branch instruction. */
699
700 rtx
gen_compare(enum rtx_code code,rtx x,rtx y,int need_compare)701 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
702 {
703 enum rtx_code compare_code;
704 enum rtx_code branch_code;
705 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
706 int must_swap = 0;
707
708 switch (code)
709 {
710 case EQ: compare_code = EQ; branch_code = NE; break;
711 case NE: compare_code = EQ; branch_code = EQ; break;
712 case LT: compare_code = LT; branch_code = NE; break;
713 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
714 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
715 case GE: compare_code = LT; branch_code = EQ; break;
716 case LTU: compare_code = LTU; branch_code = NE; break;
717 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
718 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
719 case GEU: compare_code = LTU; branch_code = EQ; break;
720
721 default:
722 gcc_unreachable ();
723 }
724
725 if (need_compare)
726 {
727 switch (compare_code)
728 {
729 case EQ:
730 if (satisfies_constraint_P (y) /* Reg equal to small const. */
731 && y != const0_rtx)
732 {
733 rtx tmp = gen_reg_rtx (SImode);
734
735 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
736 x = tmp;
737 y = const0_rtx;
738 }
739 else if (CONSTANT_P (y)) /* Reg equal to const. */
740 {
741 rtx tmp = force_reg (GET_MODE (x), y);
742 y = tmp;
743 }
744
745 if (register_operand (y, SImode) /* Reg equal to reg. */
746 || y == const0_rtx) /* Reg equal to zero. */
747 {
748 emit_insn (gen_cmp_eqsi_insn (x, y));
749
750 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
751 }
752 break;
753
754 case LT:
755 if (register_operand (y, SImode)
756 || satisfies_constraint_P (y))
757 {
758 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
759
760 switch (code)
761 {
762 case LT:
763 emit_insn (gen_cmp_ltsi_insn (x, y));
764 code = EQ;
765 break;
766 case LE:
767 if (y == const0_rtx)
768 tmp = const1_rtx;
769 else
770 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
771 emit_insn (gen_cmp_ltsi_insn (x, tmp));
772 code = EQ;
773 break;
774 case GT:
775 if (CONST_INT_P (y))
776 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
777 else
778 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
779 emit_insn (gen_cmp_ltsi_insn (x, tmp));
780 code = NE;
781 break;
782 case GE:
783 emit_insn (gen_cmp_ltsi_insn (x, y));
784 code = NE;
785 break;
786 default:
787 gcc_unreachable ();
788 }
789
790 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
791 }
792 break;
793
794 case LTU:
795 if (register_operand (y, SImode)
796 || satisfies_constraint_P (y))
797 {
798 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
799
800 switch (code)
801 {
802 case LTU:
803 emit_insn (gen_cmp_ltusi_insn (x, y));
804 code = EQ;
805 break;
806 case LEU:
807 if (y == const0_rtx)
808 tmp = const1_rtx;
809 else
810 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
811 emit_insn (gen_cmp_ltusi_insn (x, tmp));
812 code = EQ;
813 break;
814 case GTU:
815 if (CONST_INT_P (y))
816 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
817 else
818 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
819 emit_insn (gen_cmp_ltusi_insn (x, tmp));
820 code = NE;
821 break;
822 case GEU:
823 emit_insn (gen_cmp_ltusi_insn (x, y));
824 code = NE;
825 break;
826 default:
827 gcc_unreachable ();
828 }
829
830 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
831 }
832 break;
833
834 default:
835 gcc_unreachable ();
836 }
837 }
838 else
839 {
840 /* Reg/reg equal comparison. */
841 if (compare_code == EQ
842 && register_operand (y, SImode))
843 return gen_rtx_fmt_ee (code, CCmode, x, y);
844
845 /* Reg/zero signed comparison. */
846 if ((compare_code == EQ || compare_code == LT)
847 && y == const0_rtx)
848 return gen_rtx_fmt_ee (code, CCmode, x, y);
849
850 /* Reg/smallconst equal comparison. */
851 if (compare_code == EQ
852 && satisfies_constraint_P (y))
853 {
854 rtx tmp = gen_reg_rtx (SImode);
855
856 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
857 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
858 }
859
860 /* Reg/const equal comparison. */
861 if (compare_code == EQ
862 && CONSTANT_P (y))
863 {
864 rtx tmp = force_reg (GET_MODE (x), y);
865
866 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
867 }
868 }
869
870 if (CONSTANT_P (y))
871 {
872 if (must_swap)
873 y = force_reg (GET_MODE (x), y);
874 else
875 {
876 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
877
878 if (! ok_const)
879 y = force_reg (GET_MODE (x), y);
880 }
881 }
882
883 switch (compare_code)
884 {
885 case EQ :
886 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
887 break;
888 case LT :
889 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
890 break;
891 case LTU :
892 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
893 break;
894
895 default:
896 gcc_unreachable ();
897 }
898
899 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
900 }
901
902 bool
gen_cond_store(enum rtx_code code,rtx op0,rtx op1,rtx op2)903 gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
904 {
905 machine_mode mode = GET_MODE (op0);
906
907 gcc_assert (mode == SImode);
908 switch (code)
909 {
910 case EQ:
911 if (!register_operand (op1, mode))
912 op1 = force_reg (mode, op1);
913
914 if (TARGET_M32RX || TARGET_M32R2)
915 {
916 if (!reg_or_zero_operand (op2, mode))
917 op2 = force_reg (mode, op2);
918
919 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
920 return true;
921 }
922 if (CONST_INT_P (op2) && INTVAL (op2) == 0)
923 {
924 emit_insn (gen_seq_zero_insn (op0, op1));
925 return true;
926 }
927
928 if (!reg_or_eq_int16_operand (op2, mode))
929 op2 = force_reg (mode, op2);
930
931 emit_insn (gen_seq_insn (op0, op1, op2));
932 return true;
933
934 case NE:
935 if (!CONST_INT_P (op2)
936 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
937 {
938 rtx reg;
939
940 if (reload_completed || reload_in_progress)
941 return false;
942
943 reg = gen_reg_rtx (SImode);
944 emit_insn (gen_xorsi3 (reg, op1, op2));
945 op1 = reg;
946
947 if (!register_operand (op1, mode))
948 op1 = force_reg (mode, op1);
949
950 emit_insn (gen_sne_zero_insn (op0, op1));
951 return true;
952 }
953 return false;
954
955 case LT:
956 case GT:
957 if (code == GT)
958 {
959 rtx tmp = op2;
960 op2 = op1;
961 op1 = tmp;
962 code = LT;
963 }
964
965 if (!register_operand (op1, mode))
966 op1 = force_reg (mode, op1);
967
968 if (!reg_or_int16_operand (op2, mode))
969 op2 = force_reg (mode, op2);
970
971 emit_insn (gen_slt_insn (op0, op1, op2));
972 return true;
973
974 case LTU:
975 case GTU:
976 if (code == GTU)
977 {
978 rtx tmp = op2;
979 op2 = op1;
980 op1 = tmp;
981 code = LTU;
982 }
983
984 if (!register_operand (op1, mode))
985 op1 = force_reg (mode, op1);
986
987 if (!reg_or_int16_operand (op2, mode))
988 op2 = force_reg (mode, op2);
989
990 emit_insn (gen_sltu_insn (op0, op1, op2));
991 return true;
992
993 case GE:
994 case GEU:
995 if (!register_operand (op1, mode))
996 op1 = force_reg (mode, op1);
997
998 if (!reg_or_int16_operand (op2, mode))
999 op2 = force_reg (mode, op2);
1000
1001 if (code == GE)
1002 emit_insn (gen_sge_insn (op0, op1, op2));
1003 else
1004 emit_insn (gen_sgeu_insn (op0, op1, op2));
1005 return true;
1006
1007 case LE:
1008 case LEU:
1009 if (!register_operand (op1, mode))
1010 op1 = force_reg (mode, op1);
1011
1012 if (CONST_INT_P (op2))
1013 {
1014 HOST_WIDE_INT value = INTVAL (op2);
1015 if (value >= 2147483647)
1016 {
1017 emit_move_insn (op0, const1_rtx);
1018 return true;
1019 }
1020
1021 op2 = GEN_INT (value + 1);
1022 if (value < -32768 || value >= 32767)
1023 op2 = force_reg (mode, op2);
1024
1025 if (code == LEU)
1026 emit_insn (gen_sltu_insn (op0, op1, op2));
1027 else
1028 emit_insn (gen_slt_insn (op0, op1, op2));
1029 return true;
1030 }
1031
1032 if (!register_operand (op2, mode))
1033 op2 = force_reg (mode, op2);
1034
1035 if (code == LEU)
1036 emit_insn (gen_sleu_insn (op0, op1, op2));
1037 else
1038 emit_insn (gen_sle_insn (op0, op1, op2));
1039 return true;
1040
1041 default:
1042 gcc_unreachable ();
1043 }
1044 }
1045
1046
1047 /* Split a 2 word move (DI or DF) into component parts. */
1048
1049 rtx
gen_split_move_double(rtx operands[])1050 gen_split_move_double (rtx operands[])
1051 {
1052 machine_mode mode = GET_MODE (operands[0]);
1053 rtx dest = operands[0];
1054 rtx src = operands[1];
1055 rtx val;
1056
1057 /* We might have (SUBREG (MEM)) here, so just get rid of the
1058 subregs to make this code simpler. It is safe to call
1059 alter_subreg any time after reload. */
1060 if (GET_CODE (dest) == SUBREG)
1061 alter_subreg (&dest, true);
1062 if (GET_CODE (src) == SUBREG)
1063 alter_subreg (&src, true);
1064
1065 start_sequence ();
1066 if (REG_P (dest))
1067 {
1068 int dregno = REGNO (dest);
1069
1070 /* Reg = reg. */
1071 if (REG_P (src))
1072 {
1073 int sregno = REGNO (src);
1074
1075 int reverse = (dregno == sregno + 1);
1076
1077 /* We normally copy the low-numbered register first. However, if
1078 the first register operand 0 is the same as the second register of
1079 operand 1, we must copy in the opposite order. */
1080 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode),
1081 operand_subword (src, reverse, TRUE, mode)));
1082
1083 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode),
1084 operand_subword (src, !reverse, TRUE, mode)));
1085 }
1086
1087 /* Reg = constant. */
1088 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
1089 {
1090 rtx words[2];
1091 split_double (src, &words[0], &words[1]);
1092 emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode),
1093 words[0]));
1094
1095 emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode),
1096 words[1]));
1097 }
1098
1099 /* Reg = mem. */
1100 else if (MEM_P (src))
1101 {
1102 /* If the high-address word is used in the address, we must load it
1103 last. Otherwise, load it first. */
1104 int reverse = refers_to_regno_p (dregno, XEXP (src, 0));
1105
1106 /* We used to optimize loads from single registers as
1107
1108 ld r1,r3+; ld r2,r3
1109
1110 if r3 were not used subsequently. However, the REG_NOTES aren't
1111 propagated correctly by the reload phase, and it can cause bad
1112 code to be generated. We could still try:
1113
1114 ld r1,r3+; ld r2,r3; addi r3,-4
1115
1116 which saves 2 bytes and doesn't force longword alignment. */
1117 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode),
1118 adjust_address (src, SImode,
1119 reverse * UNITS_PER_WORD)));
1120
1121 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode),
1122 adjust_address (src, SImode,
1123 !reverse * UNITS_PER_WORD)));
1124 }
1125 else
1126 gcc_unreachable ();
1127 }
1128
1129 /* Mem = reg. */
1130 /* We used to optimize loads from single registers as
1131
1132 st r1,r3; st r2,+r3
1133
1134 if r3 were not used subsequently. However, the REG_NOTES aren't
1135 propagated correctly by the reload phase, and it can cause bad
1136 code to be generated. We could still try:
1137
1138 st r1,r3; st r2,+r3; addi r3,-4
1139
1140 which saves 2 bytes and doesn't force longword alignment. */
1141 else if (MEM_P (dest) && REG_P (src))
1142 {
1143 emit_insn (gen_rtx_SET (adjust_address (dest, SImode, 0),
1144 operand_subword (src, 0, TRUE, mode)));
1145
1146 emit_insn (gen_rtx_SET (adjust_address (dest, SImode, UNITS_PER_WORD),
1147 operand_subword (src, 1, TRUE, mode)));
1148 }
1149
1150 else
1151 gcc_unreachable ();
1152
1153 val = get_insns ();
1154 end_sequence ();
1155 return val;
1156 }
1157
1158
1159 static int
m32r_arg_partial_bytes(cumulative_args_t cum_v,const function_arg_info & arg)1160 m32r_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg)
1161 {
1162 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1163
1164 int words;
1165 unsigned int size =
1166 (arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1167
1168 if (*cum >= M32R_MAX_PARM_REGS)
1169 words = 0;
1170 else if (*cum + size > M32R_MAX_PARM_REGS)
1171 words = (*cum + size) - M32R_MAX_PARM_REGS;
1172 else
1173 words = 0;
1174
1175 return words * UNITS_PER_WORD;
1176 }
1177
1178 /* The ROUND_ADVANCE* macros are local to this file. */
1179 /* Round SIZE up to a word boundary. */
1180 #define ROUND_ADVANCE(SIZE) \
1181 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1182
1183 /* Round arg MODE/TYPE up to the next word boundary. */
1184 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1185 ((MODE) == BLKmode \
1186 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1187 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1188
1189 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1190 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1191
1192 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1193 a reg. This includes arguments that have to be passed by reference as the
1194 pointer to them is passed in a reg if one is available (and that is what
1195 we're given).
1196 This macro is only used in this file. */
1197 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1198 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1199
1200 /* Determine where to put an argument to a function.
1201 Value is zero to push the argument on the stack,
1202 or a hard register in which to store the argument.
1203
1204 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1205 the preceding args and about the function being called.
1206 ARG is a description of the argument. */
1207 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1208 and the rest are pushed. */
1209
1210 static rtx
m32r_function_arg(cumulative_args_t cum_v,const function_arg_info & arg)1211 m32r_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1212 {
1213 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1214
1215 return (PASS_IN_REG_P (*cum, arg.mode, arg.type)
1216 ? gen_rtx_REG (arg.mode,
1217 ROUND_ADVANCE_CUM (*cum, arg.mode, arg.type))
1218 : NULL_RTX);
1219 }
1220
1221 /* Update the data in CUM to advance over argument ARG. */
1222
1223 static void
m32r_function_arg_advance(cumulative_args_t cum_v,const function_arg_info & arg)1224 m32r_function_arg_advance (cumulative_args_t cum_v,
1225 const function_arg_info &arg)
1226 {
1227 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1228
1229 *cum = (ROUND_ADVANCE_CUM (*cum, arg.mode, arg.type)
1230 + ROUND_ADVANCE_ARG (arg.mode, arg.type));
1231 }
1232
1233 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1234
1235 static bool
m32r_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)1236 m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1237 {
1238 cumulative_args_t dummy = pack_cumulative_args (NULL);
1239 function_arg_info arg (const_cast<tree> (type), /*named=*/false);
1240 return m32r_pass_by_reference (dummy, arg);
1241 }
1242
1243 /* Worker function for TARGET_FUNCTION_VALUE. */
1244
1245 static rtx
m32r_function_value(const_tree valtype,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)1246 m32r_function_value (const_tree valtype,
1247 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1248 bool outgoing ATTRIBUTE_UNUSED)
1249 {
1250 return gen_rtx_REG (TYPE_MODE (valtype), 0);
1251 }
1252
1253 /* Worker function for TARGET_LIBCALL_VALUE. */
1254
1255 static rtx
m32r_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)1256 m32r_libcall_value (machine_mode mode,
1257 const_rtx fun ATTRIBUTE_UNUSED)
1258 {
1259 return gen_rtx_REG (mode, 0);
1260 }
1261
1262 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1263
1264 ??? What about r1 in DI/DF values. */
1265
1266 static bool
m32r_function_value_regno_p(const unsigned int regno)1267 m32r_function_value_regno_p (const unsigned int regno)
1268 {
1269 return (regno == 0);
1270 }
1271
1272 /* Do any needed setup for a variadic function. For the M32R, we must
1273 create a register parameter block, and then copy any anonymous arguments
1274 in registers to memory.
1275
1276 CUM has not been updated for the last named argument (which is given
1277 by ARG), and we rely on this fact. */
1278
1279 static void
m32r_setup_incoming_varargs(cumulative_args_t cum,const function_arg_info & arg,int * pretend_size,int no_rtl)1280 m32r_setup_incoming_varargs (cumulative_args_t cum,
1281 const function_arg_info &arg,
1282 int *pretend_size, int no_rtl)
1283 {
1284 int first_anon_arg;
1285
1286 if (no_rtl)
1287 return;
1288
1289 /* All BLKmode values are passed by reference. */
1290 gcc_assert (arg.mode != BLKmode);
1291
1292 first_anon_arg = (ROUND_ADVANCE_CUM (*get_cumulative_args (cum),
1293 arg.mode, arg.type)
1294 + ROUND_ADVANCE_ARG (arg.mode, arg.type));
1295
1296 if (first_anon_arg < M32R_MAX_PARM_REGS)
1297 {
1298 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1299 int first_reg_offset = first_anon_arg;
1300 /* Size in words to "pretend" allocate. */
1301 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1302 rtx regblock;
1303
1304 regblock = gen_frame_mem (BLKmode,
1305 plus_constant (Pmode, arg_pointer_rtx,
1306 FIRST_PARM_OFFSET (0)));
1307 set_mem_alias_set (regblock, get_varargs_alias_set ());
1308 move_block_from_reg (first_reg_offset, regblock, size);
1309
1310 *pretend_size = (size * UNITS_PER_WORD);
1311 }
1312 }
1313
1314
1315 /* Return true if INSN is real instruction bearing insn. */
1316
1317 static int
m32r_is_insn(rtx insn)1318 m32r_is_insn (rtx insn)
1319 {
1320 return (NONDEBUG_INSN_P (insn)
1321 && GET_CODE (PATTERN (insn)) != USE
1322 && GET_CODE (PATTERN (insn)) != CLOBBER);
1323 }
1324
1325 /* Increase the priority of long instructions so that the
1326 short instructions are scheduled ahead of the long ones. */
1327
1328 static int
m32r_adjust_priority(rtx_insn * insn,int priority)1329 m32r_adjust_priority (rtx_insn *insn, int priority)
1330 {
1331 if (m32r_is_insn (insn)
1332 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1333 priority <<= 3;
1334
1335 return priority;
1336 }
1337
1338
1339 /* Indicate how many instructions can be issued at the same time.
1340 This is sort of a lie. The m32r can issue only 1 long insn at
1341 once, but it can issue 2 short insns. The default therefore is
1342 set at 2, but this can be overridden by the command line option
1343 -missue-rate=1. */
1344
1345 static int
m32r_issue_rate(void)1346 m32r_issue_rate (void)
1347 {
1348 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1349 }
1350
1351 /* Cost functions. */
1352 /* Memory is 3 times as expensive as registers.
1353 ??? Is that the right way to look at it? */
1354
1355 static int
m32r_memory_move_cost(machine_mode mode,reg_class_t rclass ATTRIBUTE_UNUSED,bool in ATTRIBUTE_UNUSED)1356 m32r_memory_move_cost (machine_mode mode,
1357 reg_class_t rclass ATTRIBUTE_UNUSED,
1358 bool in ATTRIBUTE_UNUSED)
1359 {
1360 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
1361 return 6;
1362 else
1363 return 12;
1364 }
1365
1366 static bool
m32r_rtx_costs(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int outer_code ATTRIBUTE_UNUSED,int opno ATTRIBUTE_UNUSED,int * total,bool speed ATTRIBUTE_UNUSED)1367 m32r_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
1368 int outer_code ATTRIBUTE_UNUSED,
1369 int opno ATTRIBUTE_UNUSED, int *total,
1370 bool speed ATTRIBUTE_UNUSED)
1371 {
1372 int code = GET_CODE (x);
1373
1374 switch (code)
1375 {
1376 /* Small integers are as cheap as registers. 4 byte values can be
1377 fetched as immediate constants - let's give that the cost of an
1378 extra insn. */
1379 case CONST_INT:
1380 if (INT16_P (INTVAL (x)))
1381 {
1382 *total = 0;
1383 return true;
1384 }
1385 /* FALLTHRU */
1386
1387 case CONST:
1388 case LABEL_REF:
1389 case SYMBOL_REF:
1390 *total = COSTS_N_INSNS (1);
1391 return true;
1392
1393 case CONST_DOUBLE:
1394 {
1395 rtx high, low;
1396
1397 split_double (x, &high, &low);
1398 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1399 + !INT16_P (INTVAL (low)));
1400 return true;
1401 }
1402
1403 case MULT:
1404 *total = COSTS_N_INSNS (3);
1405 return true;
1406
1407 case DIV:
1408 case UDIV:
1409 case MOD:
1410 case UMOD:
1411 *total = COSTS_N_INSNS (10);
1412 return true;
1413
1414 default:
1415 return false;
1416 }
1417 }
1418
1419 /* Type of function DECL.
1420
1421 The result is cached. To reset the cache at the end of a function,
1422 call with DECL = NULL_TREE. */
1423
1424 enum m32r_function_type
m32r_compute_function_type(tree decl)1425 m32r_compute_function_type (tree decl)
1426 {
1427 /* Cached value. */
1428 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1429 /* Last function we were called for. */
1430 static tree last_fn = NULL_TREE;
1431
1432 /* Resetting the cached value? */
1433 if (decl == NULL_TREE)
1434 {
1435 fn_type = M32R_FUNCTION_UNKNOWN;
1436 last_fn = NULL_TREE;
1437 return fn_type;
1438 }
1439
1440 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1441 return fn_type;
1442
1443 /* Compute function type. */
1444 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1445 ? M32R_FUNCTION_INTERRUPT
1446 : M32R_FUNCTION_NORMAL);
1447
1448 last_fn = decl;
1449 return fn_type;
1450 }
1451 /* Function prologue/epilogue handlers. */
1452
1453 /* M32R stack frames look like:
1454
1455 Before call After call
1456 +-----------------------+ +-----------------------+
1457 | | | |
1458 high | local variables, | | local variables, |
1459 mem | reg save area, etc. | | reg save area, etc. |
1460 | | | |
1461 +-----------------------+ +-----------------------+
1462 | | | |
1463 | arguments on stack. | | arguments on stack. |
1464 | | | |
1465 SP+0->+-----------------------+ +-----------------------+
1466 | reg parm save area, |
1467 | only created for |
1468 | variable argument |
1469 | functions |
1470 +-----------------------+
1471 | previous frame ptr |
1472 +-----------------------+
1473 | |
1474 | register save area |
1475 | |
1476 +-----------------------+
1477 | return address |
1478 +-----------------------+
1479 | |
1480 | local variables |
1481 | |
1482 +-----------------------+
1483 | |
1484 | alloca allocations |
1485 | |
1486 +-----------------------+
1487 | |
1488 low | arguments on stack |
1489 memory | |
1490 SP+0->+-----------------------+
1491
1492 Notes:
1493 1) The "reg parm save area" does not exist for non variable argument fns.
1494 2) The "reg parm save area" can be eliminated completely if we saved regs
1495 containing anonymous args separately but that complicates things too
1496 much (so it's not done).
1497 3) The return address is saved after the register save area so as to have as
1498 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1499
1500 /* Structure to be filled in by m32r_compute_frame_size with register
1501 save masks, and offsets for the current function. */
1502 struct m32r_frame_info
1503 {
1504 unsigned int total_size; /* # bytes that the entire frame takes up. */
1505 unsigned int extra_size; /* # bytes of extra stuff. */
1506 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1507 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1508 unsigned int reg_size; /* # bytes needed to store regs. */
1509 unsigned int var_size; /* # bytes that variables take up. */
1510 unsigned int gmask; /* Mask of saved gp registers. */
1511 unsigned int save_fp; /* Nonzero if fp must be saved. */
1512 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1513 int initialized; /* Nonzero if frame size already calculated. */
1514 };
1515
1516 /* Current frame information calculated by m32r_compute_frame_size. */
1517 static struct m32r_frame_info current_frame_info;
1518
1519 /* Zero structure to initialize current_frame_info. */
1520 static struct m32r_frame_info zero_frame_info;
1521
1522 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1523 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1524
1525 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1526 The return address and frame pointer are treated separately.
1527 Don't consider them here. */
1528 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1529 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1530 && (df_regs_ever_live_p (regno) && (!call_used_regs[regno] || interrupt_p)))
1531
1532 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1533 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1534
1535 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1536 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1537
1538 /* Return the bytes needed to compute the frame pointer from the current
1539 stack pointer.
1540
1541 SIZE is the size needed for local variables. */
1542
1543 unsigned int
m32r_compute_frame_size(poly_int64 size)1544 m32r_compute_frame_size (poly_int64 size) /* # of var. bytes allocated. */
1545 {
1546 unsigned int regno;
1547 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1548 unsigned int reg_size;
1549 unsigned int gmask;
1550 enum m32r_function_type fn_type;
1551 int interrupt_p;
1552 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1553 | crtl->profile);
1554
1555 var_size = M32R_STACK_ALIGN (size);
1556 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size);
1557 pretend_size = crtl->args.pretend_args_size;
1558 extra_size = FIRST_PARM_OFFSET (0);
1559 total_size = extra_size + pretend_size + args_size + var_size;
1560 reg_size = 0;
1561 gmask = 0;
1562
1563 /* See if this is an interrupt handler. Call used registers must be saved
1564 for them too. */
1565 fn_type = m32r_compute_function_type (current_function_decl);
1566 interrupt_p = M32R_INTERRUPT_P (fn_type);
1567
1568 /* Calculate space needed for registers. */
1569 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1570 {
1571 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1572 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1573 {
1574 reg_size += UNITS_PER_WORD;
1575 gmask |= 1 << regno;
1576 }
1577 }
1578
1579 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1580 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1581
1582 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1583 * UNITS_PER_WORD);
1584 total_size += reg_size;
1585
1586 /* ??? Not sure this is necessary, and I don't think the epilogue
1587 handler will do the right thing if this changes total_size. */
1588 total_size = M32R_STACK_ALIGN (total_size);
1589
1590 /* frame_size = total_size - (pretend_size + reg_size); */
1591
1592 /* Save computed information. */
1593 current_frame_info.total_size = total_size;
1594 current_frame_info.extra_size = extra_size;
1595 current_frame_info.pretend_size = pretend_size;
1596 current_frame_info.var_size = var_size;
1597 current_frame_info.args_size = args_size;
1598 current_frame_info.reg_size = reg_size;
1599 current_frame_info.gmask = gmask;
1600 current_frame_info.initialized = reload_completed;
1601
1602 /* Ok, we're done. */
1603 return total_size;
1604 }
1605
1606 /* Worker function for TARGET_CAN_ELIMINATE. */
1607
1608 bool
m32r_can_eliminate(const int from,const int to)1609 m32r_can_eliminate (const int from, const int to)
1610 {
1611 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
1612 ? ! frame_pointer_needed
1613 : true);
1614 }
1615
1616
1617 /* The table we use to reference PIC data. */
1618 static rtx global_offset_table;
1619
1620 static void
m32r_reload_lr(rtx sp,int size)1621 m32r_reload_lr (rtx sp, int size)
1622 {
1623 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1624
1625 if (size == 0)
1626 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp)));
1627 else if (size < 32768)
1628 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode,
1629 gen_rtx_PLUS (Pmode, sp,
1630 GEN_INT (size)))));
1631 else
1632 {
1633 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1634
1635 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1636 emit_insn (gen_addsi3 (tmp, tmp, sp));
1637 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp)));
1638 }
1639
1640 emit_use (lr);
1641 }
1642
1643 void
m32r_load_pic_register(void)1644 m32r_load_pic_register (void)
1645 {
1646 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1647 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1648 GEN_INT (TARGET_MODEL_SMALL)));
1649
1650 /* Need to emit this whether or not we obey regdecls,
1651 since setjmp/longjmp can cause life info to screw up. */
1652 emit_use (pic_offset_table_rtx);
1653 }
1654
1655 /* Expand the m32r prologue as a series of insns. */
1656
1657 void
m32r_expand_prologue(void)1658 m32r_expand_prologue (void)
1659 {
1660 int regno;
1661 int frame_size;
1662 unsigned int gmask;
1663 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1664 | crtl->profile);
1665
1666 if (! current_frame_info.initialized)
1667 m32r_compute_frame_size (get_frame_size ());
1668
1669 if (flag_stack_usage_info)
1670 current_function_static_stack_size = current_frame_info.total_size;
1671
1672 gmask = current_frame_info.gmask;
1673
1674 /* These cases shouldn't happen. Catch them now. */
1675 gcc_assert (current_frame_info.total_size || !gmask);
1676
1677 /* Allocate space for register arguments if this is a variadic function. */
1678 if (current_frame_info.pretend_size != 0)
1679 {
1680 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1681 the wrong result on a 64-bit host. */
1682 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1683 emit_insn (gen_addsi3 (stack_pointer_rtx,
1684 stack_pointer_rtx,
1685 GEN_INT (-pretend_size)));
1686 }
1687
1688 /* Save any registers we need to and set up fp. */
1689 if (current_frame_info.save_fp)
1690 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1691
1692 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1693
1694 /* Save any needed call-saved regs (and call-used if this is an
1695 interrupt handler). */
1696 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1697 {
1698 if ((gmask & (1 << regno)) != 0)
1699 emit_insn (gen_movsi_push (stack_pointer_rtx,
1700 gen_rtx_REG (Pmode, regno)));
1701 }
1702
1703 if (current_frame_info.save_lr)
1704 emit_insn (gen_movsi_push (stack_pointer_rtx,
1705 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1706
1707 /* Allocate the stack frame. */
1708 frame_size = (current_frame_info.total_size
1709 - (current_frame_info.pretend_size
1710 + current_frame_info.reg_size));
1711
1712 if (frame_size == 0)
1713 ; /* Nothing to do. */
1714 else if (frame_size <= 32768)
1715 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1716 GEN_INT (-frame_size)));
1717 else
1718 {
1719 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1720
1721 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1722 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1723 }
1724
1725 if (frame_pointer_needed)
1726 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1727
1728 if (crtl->profile)
1729 /* Push lr for mcount (form_pc, x). */
1730 emit_insn (gen_movsi_push (stack_pointer_rtx,
1731 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1732
1733 if (pic_reg_used)
1734 {
1735 m32r_load_pic_register ();
1736 m32r_reload_lr (stack_pointer_rtx,
1737 (crtl->profile ? 0 : frame_size));
1738 }
1739
1740 if (crtl->profile && !pic_reg_used)
1741 emit_insn (gen_blockage ());
1742 }
1743
1744
1745 /* Set up the stack and frame pointer (if desired) for the function.
1746 Note, if this is changed, you need to mirror the changes in
1747 m32r_compute_frame_size which calculates the prolog size. */
1748
1749 static void
m32r_output_function_prologue(FILE * file)1750 m32r_output_function_prologue (FILE * file)
1751 {
1752 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1753
1754 /* If this is an interrupt handler, mark it as such. */
1755 if (M32R_INTERRUPT_P (fn_type))
1756 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1757
1758 if (! current_frame_info.initialized)
1759 m32r_compute_frame_size (get_frame_size ());
1760
1761 /* This is only for the human reader. */
1762 fprintf (file,
1763 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1764 ASM_COMMENT_START,
1765 current_frame_info.var_size,
1766 current_frame_info.reg_size / 4,
1767 current_frame_info.args_size,
1768 current_frame_info.extra_size);
1769 }
1770
1771 /* Output RTL to pop register REGNO from the stack. */
1772
1773 static void
pop(int regno)1774 pop (int regno)
1775 {
1776 rtx x;
1777
1778 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno),
1779 stack_pointer_rtx));
1780 add_reg_note (x, REG_INC, stack_pointer_rtx);
1781 }
1782
1783 /* Expand the m32r epilogue as a series of insns. */
1784
1785 void
m32r_expand_epilogue(void)1786 m32r_expand_epilogue (void)
1787 {
1788 int regno;
1789 int noepilogue = FALSE;
1790 int total_size;
1791
1792 gcc_assert (current_frame_info.initialized);
1793 total_size = current_frame_info.total_size;
1794
1795 if (total_size == 0)
1796 {
1797 rtx_insn *insn = get_last_insn ();
1798
1799 /* If the last insn was a BARRIER, we don't have to write any code
1800 because a jump (aka return) was put there. */
1801 if (insn && NOTE_P (insn))
1802 insn = prev_nonnote_insn (insn);
1803 if (insn && BARRIER_P (insn))
1804 noepilogue = TRUE;
1805 }
1806
1807 if (!noepilogue)
1808 {
1809 unsigned int var_size = current_frame_info.var_size;
1810 unsigned int args_size = current_frame_info.args_size;
1811 unsigned int gmask = current_frame_info.gmask;
1812 int can_trust_sp_p = !cfun->calls_alloca;
1813
1814 if (flag_exceptions)
1815 emit_insn (gen_blockage ());
1816
1817 /* The first thing to do is point the sp at the bottom of the register
1818 save area. */
1819 if (can_trust_sp_p)
1820 {
1821 unsigned int reg_offset = var_size + args_size;
1822
1823 if (reg_offset == 0)
1824 ; /* Nothing to do. */
1825 else if (reg_offset < 32768)
1826 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1827 GEN_INT (reg_offset)));
1828 else
1829 {
1830 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1831
1832 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1833 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1834 tmp));
1835 }
1836 }
1837 else if (frame_pointer_needed)
1838 {
1839 unsigned int reg_offset = var_size + args_size;
1840
1841 if (reg_offset == 0)
1842 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1843 else if (reg_offset < 32768)
1844 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1845 GEN_INT (reg_offset)));
1846 else
1847 {
1848 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1849
1850 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1851 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1852 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1853 tmp));
1854 }
1855 }
1856 else
1857 gcc_unreachable ();
1858
1859 if (current_frame_info.save_lr)
1860 pop (RETURN_ADDR_REGNUM);
1861
1862 /* Restore any saved registers, in reverse order of course. */
1863 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1864 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1865 {
1866 if ((gmask & (1L << regno)) != 0)
1867 pop (regno);
1868 }
1869
1870 if (current_frame_info.save_fp)
1871 pop (FRAME_POINTER_REGNUM);
1872
1873 /* Remove varargs area if present. */
1874 if (current_frame_info.pretend_size != 0)
1875 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1876 GEN_INT (current_frame_info.pretend_size)));
1877
1878 emit_insn (gen_blockage ());
1879 }
1880 }
1881
1882 /* Do any necessary cleanup after a function to restore stack, frame,
1883 and regs. */
1884
1885 static void
m32r_output_function_epilogue(FILE *)1886 m32r_output_function_epilogue (FILE *)
1887 {
1888 /* Reset state info for each function. */
1889 current_frame_info = zero_frame_info;
1890 m32r_compute_function_type (NULL_TREE);
1891 }
1892
1893 /* Return nonzero if this function is known to have a null or 1 instruction
1894 epilogue. */
1895
1896 int
direct_return(void)1897 direct_return (void)
1898 {
1899 if (!reload_completed)
1900 return FALSE;
1901
1902 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl)))
1903 return FALSE;
1904
1905 if (! current_frame_info.initialized)
1906 m32r_compute_frame_size (get_frame_size ());
1907
1908 return current_frame_info.total_size == 0;
1909 }
1910
1911
1912 /* PIC. */
1913
1914 int
m32r_legitimate_pic_operand_p(rtx x)1915 m32r_legitimate_pic_operand_p (rtx x)
1916 {
1917 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1918 return 0;
1919
1920 if (GET_CODE (x) == CONST
1921 && GET_CODE (XEXP (x, 0)) == PLUS
1922 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1923 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1924 && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
1925 return 0;
1926
1927 return 1;
1928 }
1929
1930 rtx
m32r_legitimize_pic_address(rtx orig,rtx reg)1931 m32r_legitimize_pic_address (rtx orig, rtx reg)
1932 {
1933 #ifdef DEBUG_PIC
1934 printf("m32r_legitimize_pic_address()\n");
1935 #endif
1936
1937 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1938 {
1939 rtx pic_ref, address;
1940 int subregs = 0;
1941
1942 if (reg == 0)
1943 {
1944 gcc_assert (!reload_in_progress && !reload_completed);
1945 reg = gen_reg_rtx (Pmode);
1946
1947 subregs = 1;
1948 }
1949
1950 if (subregs)
1951 address = gen_reg_rtx (Pmode);
1952 else
1953 address = reg;
1954
1955 crtl->uses_pic_offset_table = 1;
1956
1957 if (GET_CODE (orig) == LABEL_REF
1958 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1959 {
1960 emit_insn (gen_gotoff_load_addr (reg, orig));
1961 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1962 return reg;
1963 }
1964
1965 emit_insn (gen_pic_load_addr (address, orig));
1966
1967 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1968 pic_ref = gen_const_mem (Pmode, address);
1969 emit_move_insn (reg, pic_ref);
1970 return reg;
1971 }
1972 else if (GET_CODE (orig) == CONST)
1973 {
1974 rtx base, offset;
1975
1976 if (GET_CODE (XEXP (orig, 0)) == PLUS
1977 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1978 return orig;
1979
1980 if (reg == 0)
1981 {
1982 gcc_assert (!reload_in_progress && !reload_completed);
1983 reg = gen_reg_rtx (Pmode);
1984 }
1985
1986 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1987 {
1988 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1989 if (base == reg)
1990 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1991 else
1992 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1993 }
1994 else
1995 return orig;
1996
1997 if (CONST_INT_P (offset))
1998 {
1999 if (INT16_P (INTVAL (offset)))
2000 return plus_constant (Pmode, base, INTVAL (offset));
2001 else
2002 {
2003 gcc_assert (! reload_in_progress && ! reload_completed);
2004 offset = force_reg (Pmode, offset);
2005 }
2006 }
2007
2008 return gen_rtx_PLUS (Pmode, base, offset);
2009 }
2010
2011 return orig;
2012 }
2013
2014 static rtx
m32r_legitimize_address(rtx x,rtx orig_x ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)2015 m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED,
2016 machine_mode mode ATTRIBUTE_UNUSED)
2017 {
2018 if (flag_pic)
2019 return m32r_legitimize_pic_address (x, NULL_RTX);
2020 else
2021 return x;
2022 }
2023
2024 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2025
2026 static bool
m32r_mode_dependent_address_p(const_rtx addr,addr_space_t as ATTRIBUTE_UNUSED)2027 m32r_mode_dependent_address_p (const_rtx addr, addr_space_t as ATTRIBUTE_UNUSED)
2028 {
2029 if (GET_CODE (addr) == LO_SUM)
2030 return true;
2031
2032 return false;
2033 }
2034
2035 /* Nested function support. */
2036
2037 /* Emit RTL insns to initialize the variable parts of a trampoline.
2038 FNADDR is an RTX for the address of the function's pure code.
2039 CXT is an RTX for the static chain value for the function. */
2040
2041 void
m32r_initialize_trampoline(rtx tramp ATTRIBUTE_UNUSED,rtx fnaddr ATTRIBUTE_UNUSED,rtx cxt ATTRIBUTE_UNUSED)2042 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2043 rtx fnaddr ATTRIBUTE_UNUSED,
2044 rtx cxt ATTRIBUTE_UNUSED)
2045 {
2046 }
2047
2048 static void
m32r_file_start(void)2049 m32r_file_start (void)
2050 {
2051 default_file_start ();
2052
2053 if (flag_verbose_asm)
2054 fprintf (asm_out_file,
2055 "%s M32R/D special options: -G %d\n",
2056 ASM_COMMENT_START, g_switch_value);
2057
2058 if (TARGET_LITTLE_ENDIAN)
2059 fprintf (asm_out_file, "\t.little\n");
2060 }
2061
2062 /* Print operand X (an rtx) in assembler syntax to file FILE.
2063 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2064 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2065
2066 static void
m32r_print_operand(FILE * file,rtx x,int code)2067 m32r_print_operand (FILE * file, rtx x, int code)
2068 {
2069 rtx addr;
2070
2071 switch (code)
2072 {
2073 /* The 's' and 'p' codes are used by output_block_move() to
2074 indicate post-increment 's'tores and 'p're-increment loads. */
2075 case 's':
2076 if (REG_P (x))
2077 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2078 else
2079 output_operand_lossage ("invalid operand to %%s code");
2080 return;
2081
2082 case 'p':
2083 if (REG_P (x))
2084 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2085 else
2086 output_operand_lossage ("invalid operand to %%p code");
2087 return;
2088
2089 case 'R' :
2090 /* Write second word of DImode or DFmode reference,
2091 register or memory. */
2092 if (REG_P (x))
2093 fputs (reg_names[REGNO (x)+1], file);
2094 else if (MEM_P (x))
2095 {
2096 machine_mode mode = GET_MODE (x);
2097
2098 fprintf (file, "@(");
2099 /* Handle possible auto-increment. Since it is pre-increment and
2100 we have already done it, we can just use an offset of four. */
2101 /* ??? This is taken from rs6000.cc I think. I don't think it is
2102 currently necessary, but keep it around. */
2103 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2104 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2105 output_address (mode, plus_constant (Pmode,
2106 XEXP (XEXP (x, 0), 0), 4));
2107 else
2108 output_address (mode, plus_constant (Pmode, XEXP (x, 0), 4));
2109 fputc (')', file);
2110 }
2111 else
2112 output_operand_lossage ("invalid operand to %%R code");
2113 return;
2114
2115 case 'H' : /* High word. */
2116 case 'L' : /* Low word. */
2117 if (REG_P (x))
2118 {
2119 /* L = least significant word, H = most significant word. */
2120 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2121 fputs (reg_names[REGNO (x)], file);
2122 else
2123 fputs (reg_names[REGNO (x)+1], file);
2124 }
2125 else if (CONST_INT_P (x)
2126 || GET_CODE (x) == CONST_DOUBLE)
2127 {
2128 rtx first, second;
2129
2130 split_double (x, &first, &second);
2131 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2132 code == 'L' ? INTVAL (first) : INTVAL (second));
2133 }
2134 else
2135 output_operand_lossage ("invalid operand to %%H/%%L code");
2136 return;
2137
2138 case 'A' :
2139 {
2140 char str[30];
2141
2142 if (GET_CODE (x) != CONST_DOUBLE
2143 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2144 fatal_insn ("bad insn for 'A'", x);
2145
2146 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2147 fprintf (file, "%s", str);
2148 return;
2149 }
2150
2151 case 'B' : /* Bottom half. */
2152 case 'T' : /* Top half. */
2153 /* Output the argument to a `seth' insn (sets the Top half-word).
2154 For constants output arguments to a seth/or3 pair to set Top and
2155 Bottom halves. For symbols output arguments to a seth/add3 pair to
2156 set Top and Bottom halves. The difference exists because for
2157 constants seth/or3 is more readable but for symbols we need to use
2158 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2159 switch (GET_CODE (x))
2160 {
2161 case CONST_INT :
2162 case CONST_DOUBLE :
2163 {
2164 rtx first, second;
2165
2166 split_double (x, &first, &second);
2167 x = WORDS_BIG_ENDIAN ? second : first;
2168 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2169 (code == 'B'
2170 ? INTVAL (x) & 0xffff
2171 : (INTVAL (x) >> 16) & 0xffff));
2172 }
2173 return;
2174 case CONST :
2175 case SYMBOL_REF :
2176 if (code == 'B'
2177 && small_data_operand (x, VOIDmode))
2178 {
2179 fputs ("sda(", file);
2180 output_addr_const (file, x);
2181 fputc (')', file);
2182 return;
2183 }
2184 /* fall through */
2185 case LABEL_REF :
2186 fputs (code == 'T' ? "shigh(" : "low(", file);
2187 output_addr_const (file, x);
2188 fputc (')', file);
2189 return;
2190 default :
2191 output_operand_lossage ("invalid operand to %%T/%%B code");
2192 return;
2193 }
2194 break;
2195
2196 case 'U' :
2197 /* ??? wip */
2198 /* Output a load/store with update indicator if appropriate. */
2199 if (MEM_P (x))
2200 {
2201 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2202 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2203 fputs (".a", file);
2204 }
2205 else
2206 output_operand_lossage ("invalid operand to %%U code");
2207 return;
2208
2209 case 'N' :
2210 /* Print a constant value negated. */
2211 if (CONST_INT_P (x))
2212 output_addr_const (file, GEN_INT (- INTVAL (x)));
2213 else
2214 output_operand_lossage ("invalid operand to %%N code");
2215 return;
2216
2217 case 'X' :
2218 /* Print a const_int in hex. Used in comments. */
2219 if (CONST_INT_P (x))
2220 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2221 return;
2222
2223 case '#' :
2224 fputs (IMMEDIATE_PREFIX, file);
2225 return;
2226
2227 case 0 :
2228 /* Do nothing special. */
2229 break;
2230
2231 default :
2232 /* Unknown flag. */
2233 output_operand_lossage ("invalid operand output code");
2234 }
2235
2236 switch (GET_CODE (x))
2237 {
2238 case REG :
2239 fputs (reg_names[REGNO (x)], file);
2240 break;
2241
2242 case MEM :
2243 addr = XEXP (x, 0);
2244 if (GET_CODE (addr) == PRE_INC)
2245 {
2246 if (!REG_P (XEXP (addr, 0)))
2247 fatal_insn ("pre-increment address is not a register", x);
2248
2249 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2250 }
2251 else if (GET_CODE (addr) == PRE_DEC)
2252 {
2253 if (!REG_P (XEXP (addr, 0)))
2254 fatal_insn ("pre-decrement address is not a register", x);
2255
2256 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2257 }
2258 else if (GET_CODE (addr) == POST_INC)
2259 {
2260 if (!REG_P (XEXP (addr, 0)))
2261 fatal_insn ("post-increment address is not a register", x);
2262
2263 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2264 }
2265 else
2266 {
2267 fputs ("@(", file);
2268 output_address (GET_MODE (x), addr);
2269 fputc (')', file);
2270 }
2271 break;
2272
2273 case CONST_DOUBLE :
2274 /* We handle SFmode constants here as output_addr_const doesn't. */
2275 if (GET_MODE (x) == SFmode)
2276 {
2277 long l;
2278
2279 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
2280 fprintf (file, "0x%08lx", l);
2281 break;
2282 }
2283
2284 /* FALLTHRU */
2285 /* Let output_addr_const deal with it. */
2286
2287 default :
2288 output_addr_const (file, x);
2289 break;
2290 }
2291 }
2292
2293 /* Print a memory address as an operand to reference that memory location. */
2294
2295 static void
m32r_print_operand_address(FILE * file,machine_mode,rtx addr)2296 m32r_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
2297 {
2298 rtx base;
2299 rtx index = 0;
2300 int offset = 0;
2301
2302 switch (GET_CODE (addr))
2303 {
2304 case REG :
2305 fputs (reg_names[REGNO (addr)], file);
2306 break;
2307
2308 case PLUS :
2309 if (CONST_INT_P (XEXP (addr, 0)))
2310 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2311 else if (CONST_INT_P (XEXP (addr, 1)))
2312 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2313 else
2314 base = XEXP (addr, 0), index = XEXP (addr, 1);
2315 if (REG_P (base))
2316 {
2317 /* Print the offset first (if present) to conform to the manual. */
2318 if (index == 0)
2319 {
2320 if (offset != 0)
2321 fprintf (file, "%d,", offset);
2322 fputs (reg_names[REGNO (base)], file);
2323 }
2324 /* The chip doesn't support this, but left in for generality. */
2325 else if (REG_P (index))
2326 fprintf (file, "%s,%s",
2327 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2328 /* Not sure this can happen, but leave in for now. */
2329 else if (GET_CODE (index) == SYMBOL_REF)
2330 {
2331 output_addr_const (file, index);
2332 fputc (',', file);
2333 fputs (reg_names[REGNO (base)], file);
2334 }
2335 else
2336 fatal_insn ("bad address", addr);
2337 }
2338 else if (GET_CODE (base) == LO_SUM)
2339 {
2340 gcc_assert (!index && REG_P (XEXP (base, 0)));
2341 if (small_data_operand (XEXP (base, 1), VOIDmode))
2342 fputs ("sda(", file);
2343 else
2344 fputs ("low(", file);
2345 output_addr_const (file, plus_constant (Pmode, XEXP (base, 1),
2346 offset));
2347 fputs ("),", file);
2348 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2349 }
2350 else
2351 fatal_insn ("bad address", addr);
2352 break;
2353
2354 case LO_SUM :
2355 if (!REG_P (XEXP (addr, 0)))
2356 fatal_insn ("lo_sum not of register", addr);
2357 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2358 fputs ("sda(", file);
2359 else
2360 fputs ("low(", file);
2361 output_addr_const (file, XEXP (addr, 1));
2362 fputs ("),", file);
2363 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2364 break;
2365
2366 case PRE_INC : /* Assume SImode. */
2367 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2368 break;
2369
2370 case PRE_DEC : /* Assume SImode. */
2371 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2372 break;
2373
2374 case POST_INC : /* Assume SImode. */
2375 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2376 break;
2377
2378 default :
2379 output_addr_const (file, addr);
2380 break;
2381 }
2382 }
2383
2384 static bool
m32r_print_operand_punct_valid_p(unsigned char code)2385 m32r_print_operand_punct_valid_p (unsigned char code)
2386 {
2387 return m32r_punct_chars[code];
2388 }
2389
2390 /* Return true if the operands are the constants 0 and 1. */
2391
2392 int
zero_and_one(rtx operand1,rtx operand2)2393 zero_and_one (rtx operand1, rtx operand2)
2394 {
2395 return
2396 CONST_INT_P (operand1)
2397 && CONST_INT_P (operand2)
2398 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2399 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2400 }
2401
2402 /* Generate the correct assembler code to handle the conditional loading of a
2403 value into a register. It is known that the operands satisfy the
2404 conditional_move_operand() function above. The destination is operand[0].
2405 The condition is operand [1]. The 'true' value is operand [2] and the
2406 'false' value is operand [3]. */
2407
2408 char *
emit_cond_move(rtx * operands,rtx insn ATTRIBUTE_UNUSED)2409 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2410 {
2411 static char buffer [100];
2412 const char * dest = reg_names [REGNO (operands [0])];
2413
2414 buffer [0] = 0;
2415
2416 /* Destination must be a register. */
2417 gcc_assert (REG_P (operands [0]));
2418 gcc_assert (conditional_move_operand (operands [2], SImode));
2419 gcc_assert (conditional_move_operand (operands [3], SImode));
2420
2421 /* Check to see if the test is reversed. */
2422 if (GET_CODE (operands [1]) == NE)
2423 {
2424 rtx tmp = operands [2];
2425 operands [2] = operands [3];
2426 operands [3] = tmp;
2427 }
2428
2429 sprintf (buffer, "mvfc %s, cbr", dest);
2430
2431 /* If the true value was '0' then we need to invert the results of the move. */
2432 if (INTVAL (operands [2]) == 0)
2433 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2434 dest, dest);
2435
2436 return buffer;
2437 }
2438
2439 /* Returns true if the registers contained in the two
2440 rtl expressions are different. */
2441
2442 int
m32r_not_same_reg(rtx a,rtx b)2443 m32r_not_same_reg (rtx a, rtx b)
2444 {
2445 int reg_a = -1;
2446 int reg_b = -2;
2447
2448 while (GET_CODE (a) == SUBREG)
2449 a = SUBREG_REG (a);
2450
2451 if (REG_P (a))
2452 reg_a = REGNO (a);
2453
2454 while (GET_CODE (b) == SUBREG)
2455 b = SUBREG_REG (b);
2456
2457 if (REG_P (b))
2458 reg_b = REGNO (b);
2459
2460 return reg_a != reg_b;
2461 }
2462
2463
2464 rtx
m32r_function_symbol(const char * name)2465 m32r_function_symbol (const char *name)
2466 {
2467 int extra_flags = 0;
2468 enum m32r_model model;
2469 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2470
2471 if (TARGET_MODEL_SMALL)
2472 model = M32R_MODEL_SMALL;
2473 else if (TARGET_MODEL_MEDIUM)
2474 model = M32R_MODEL_MEDIUM;
2475 else if (TARGET_MODEL_LARGE)
2476 model = M32R_MODEL_LARGE;
2477 else
2478 gcc_unreachable (); /* Shouldn't happen. */
2479 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2480
2481 if (extra_flags)
2482 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2483
2484 return sym;
2485 }
2486
2487 /* Use a library function to move some bytes. */
2488
2489 static void
block_move_call(rtx dest_reg,rtx src_reg,rtx bytes_rtx)2490 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2491 {
2492 /* We want to pass the size as Pmode, which will normally be SImode
2493 but will be DImode if we are using 64-bit longs and pointers. */
2494 if (GET_MODE (bytes_rtx) != VOIDmode
2495 && GET_MODE (bytes_rtx) != Pmode)
2496 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2497
2498 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL,
2499 VOIDmode, dest_reg, Pmode, src_reg, Pmode,
2500 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2501 TYPE_UNSIGNED (sizetype)),
2502 TYPE_MODE (sizetype));
2503 }
2504
2505 /* Expand string/block move operations.
2506
2507 operands[0] is the pointer to the destination.
2508 operands[1] is the pointer to the source.
2509 operands[2] is the number of bytes to move.
2510 operands[3] is the alignment.
2511
2512 Returns 1 upon success, 0 otherwise. */
2513
2514 int
m32r_expand_block_move(rtx operands[])2515 m32r_expand_block_move (rtx operands[])
2516 {
2517 rtx orig_dst = operands[0];
2518 rtx orig_src = operands[1];
2519 rtx bytes_rtx = operands[2];
2520 rtx align_rtx = operands[3];
2521 int constp = CONST_INT_P (bytes_rtx);
2522 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2523 int align = INTVAL (align_rtx);
2524 int leftover;
2525 rtx src_reg;
2526 rtx dst_reg;
2527
2528 if (constp && bytes <= 0)
2529 return 1;
2530
2531 /* Move the address into scratch registers. */
2532 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2533 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2534
2535 if (align > UNITS_PER_WORD)
2536 align = UNITS_PER_WORD;
2537
2538 /* If we prefer size over speed, always use a function call.
2539 If we do not know the size, use a function call.
2540 If the blocks are not word aligned, use a function call. */
2541 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2542 {
2543 block_move_call (dst_reg, src_reg, bytes_rtx);
2544 return 0;
2545 }
2546
2547 leftover = bytes % MAX_MOVE_BYTES;
2548 bytes -= leftover;
2549
2550 /* If necessary, generate a loop to handle the bulk of the copy. */
2551 if (bytes)
2552 {
2553 rtx_code_label *label = NULL;
2554 rtx final_src = NULL_RTX;
2555 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2556 rtx rounded_total = GEN_INT (bytes);
2557 rtx new_dst_reg = gen_reg_rtx (SImode);
2558 rtx new_src_reg = gen_reg_rtx (SImode);
2559
2560 /* If we are going to have to perform this loop more than
2561 once, then generate a label and compute the address the
2562 source register will contain upon completion of the final
2563 iteration. */
2564 if (bytes > MAX_MOVE_BYTES)
2565 {
2566 final_src = gen_reg_rtx (Pmode);
2567
2568 if (INT16_P(bytes))
2569 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2570 else
2571 {
2572 emit_insn (gen_movsi (final_src, rounded_total));
2573 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2574 }
2575
2576 label = gen_label_rtx ();
2577 emit_label (label);
2578 }
2579
2580 /* It is known that output_block_move() will update src_reg to point
2581 to the word after the end of the source block, and dst_reg to point
2582 to the last word of the destination block, provided that the block
2583 is MAX_MOVE_BYTES long. */
2584 emit_insn (gen_cpymemsi_internal (dst_reg, src_reg, at_a_time,
2585 new_dst_reg, new_src_reg));
2586 emit_move_insn (dst_reg, new_dst_reg);
2587 emit_move_insn (src_reg, new_src_reg);
2588 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2589
2590 if (bytes > MAX_MOVE_BYTES)
2591 {
2592 rtx test = gen_rtx_NE (VOIDmode, src_reg, final_src);
2593 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
2594 }
2595 }
2596
2597 if (leftover)
2598 emit_insn (gen_cpymemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2599 gen_reg_rtx (SImode),
2600 gen_reg_rtx (SImode)));
2601 return 1;
2602 }
2603
2604
2605 /* Emit load/stores for a small constant word aligned block_move.
2606
2607 operands[0] is the memory address of the destination.
2608 operands[1] is the memory address of the source.
2609 operands[2] is the number of bytes to move.
2610 operands[3] is a temp register.
2611 operands[4] is a temp register. */
2612
2613 void
m32r_output_block_move(rtx insn ATTRIBUTE_UNUSED,rtx operands[])2614 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2615 {
2616 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2617 int first_time;
2618 int got_extra = 0;
2619
2620 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2621
2622 /* We do not have a post-increment store available, so the first set of
2623 stores are done without any increment, then the remaining ones can use
2624 the pre-increment addressing mode.
2625
2626 Note: expand_block_move() also relies upon this behavior when building
2627 loops to copy large blocks. */
2628 first_time = 1;
2629
2630 while (bytes > 0)
2631 {
2632 if (bytes >= 8)
2633 {
2634 if (first_time)
2635 {
2636 output_asm_insn ("ld\t%5, %p1", operands);
2637 output_asm_insn ("ld\t%6, %p1", operands);
2638 output_asm_insn ("st\t%5, @%0", operands);
2639 output_asm_insn ("st\t%6, %s0", operands);
2640 }
2641 else
2642 {
2643 output_asm_insn ("ld\t%5, %p1", operands);
2644 output_asm_insn ("ld\t%6, %p1", operands);
2645 output_asm_insn ("st\t%5, %s0", operands);
2646 output_asm_insn ("st\t%6, %s0", operands);
2647 }
2648
2649 bytes -= 8;
2650 }
2651 else if (bytes >= 4)
2652 {
2653 if (bytes > 4)
2654 got_extra = 1;
2655
2656 output_asm_insn ("ld\t%5, %p1", operands);
2657
2658 if (got_extra)
2659 output_asm_insn ("ld\t%6, %p1", operands);
2660
2661 if (first_time)
2662 output_asm_insn ("st\t%5, @%0", operands);
2663 else
2664 output_asm_insn ("st\t%5, %s0", operands);
2665
2666 bytes -= 4;
2667 }
2668 else
2669 {
2670 /* Get the entire next word, even though we do not want all of it.
2671 The saves us from doing several smaller loads, and we assume that
2672 we cannot cause a page fault when at least part of the word is in
2673 valid memory [since we don't get called if things aren't properly
2674 aligned]. */
2675 int dst_offset = first_time ? 0 : 4;
2676 /* The amount of increment we have to make to the
2677 destination pointer. */
2678 int dst_inc_amount = dst_offset + bytes - 4;
2679 /* The same for the source pointer. */
2680 int src_inc_amount = bytes - (got_extra ? 4 : 0);
2681 int last_shift;
2682 rtx my_operands[3];
2683
2684 /* If got_extra is true then we have already loaded
2685 the next word as part of loading and storing the previous word. */
2686 if (! got_extra)
2687 output_asm_insn ("ld\t%6, @%1", operands);
2688
2689 if (bytes >= 2)
2690 {
2691 bytes -= 2;
2692
2693 output_asm_insn ("sra3\t%5, %6, #16", operands);
2694 my_operands[0] = operands[5];
2695 my_operands[1] = GEN_INT (dst_offset);
2696 my_operands[2] = operands[0];
2697 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2698
2699 /* If there is a byte left to store then increment the
2700 destination address and shift the contents of the source
2701 register down by 8 bits. We could not do the address
2702 increment in the store half word instruction, because it does
2703 not have an auto increment mode. */
2704 if (bytes > 0) /* assert (bytes == 1) */
2705 {
2706 dst_offset += 2;
2707 last_shift = 8;
2708 }
2709 }
2710 else
2711 last_shift = 24;
2712
2713 if (bytes > 0)
2714 {
2715 my_operands[0] = operands[6];
2716 my_operands[1] = GEN_INT (last_shift);
2717 output_asm_insn ("srai\t%0, #%1", my_operands);
2718 my_operands[0] = operands[6];
2719 my_operands[1] = GEN_INT (dst_offset);
2720 my_operands[2] = operands[0];
2721 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2722 }
2723
2724 /* Update the destination pointer if needed. We have to do
2725 this so that the patterns matches what we output in this
2726 function. */
2727 if (dst_inc_amount
2728 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2729 {
2730 my_operands[0] = operands[0];
2731 my_operands[1] = GEN_INT (dst_inc_amount);
2732 output_asm_insn ("addi\t%0, #%1", my_operands);
2733 }
2734
2735 /* Update the source pointer if needed. We have to do this
2736 so that the patterns matches what we output in this
2737 function. */
2738 if (src_inc_amount
2739 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2740 {
2741 my_operands[0] = operands[1];
2742 my_operands[1] = GEN_INT (src_inc_amount);
2743 output_asm_insn ("addi\t%0, #%1", my_operands);
2744 }
2745
2746 bytes = 0;
2747 }
2748
2749 first_time = 0;
2750 }
2751 }
2752
2753 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2754
2755 static bool
m32r_hard_regno_mode_ok(unsigned int regno,machine_mode mode)2756 m32r_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2757 {
2758 return (m32r_hard_regno_modes[regno] & m32r_mode_class[mode]) != 0;
2759 }
2760
2761 /* Implement TARGET_MODES_TIEABLE_P. Tie QI/HI/SI modes together. */
2762
2763 static bool
m32r_modes_tieable_p(machine_mode mode1,machine_mode mode2)2764 m32r_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2765 {
2766 return (GET_MODE_CLASS (mode1) == MODE_INT
2767 && GET_MODE_CLASS (mode2) == MODE_INT
2768 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
2769 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD);
2770 }
2771
2772 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2773
2774 int
m32r_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)2775 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2776 unsigned int new_reg)
2777 {
2778 /* Interrupt routines can't clobber any register that isn't already used. */
2779 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2780 && !df_regs_ever_live_p (new_reg))
2781 return 0;
2782
2783 return 1;
2784 }
2785
2786 rtx
m32r_return_addr(int count)2787 m32r_return_addr (int count)
2788 {
2789 if (count != 0)
2790 return const0_rtx;
2791
2792 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2793 }
2794
2795 static void
m32r_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)2796 m32r_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2797 {
2798 emit_move_insn (adjust_address (m_tramp, SImode, 0),
2799 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2800 0x017e8e17 : 0x178e7e01, SImode));
2801 emit_move_insn (adjust_address (m_tramp, SImode, 4),
2802 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2803 0x0c00ae86 : 0x86ae000c, SImode));
2804 emit_move_insn (adjust_address (m_tramp, SImode, 8),
2805 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2806 0xe627871e : 0x1e8727e6, SImode));
2807 emit_move_insn (adjust_address (m_tramp, SImode, 12),
2808 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2809 0xc616c626 : 0x26c61fc6, SImode));
2810 emit_move_insn (adjust_address (m_tramp, SImode, 16),
2811 chain_value);
2812 emit_move_insn (adjust_address (m_tramp, SImode, 20),
2813 XEXP (DECL_RTL (fndecl), 0));
2814
2815 if (m32r_cache_flush_trap >= 0)
2816 emit_insn (gen_flush_icache
2817 (validize_mem (adjust_address (m_tramp, SImode, 0)),
2818 gen_int_mode (m32r_cache_flush_trap, SImode)));
2819 else if (m32r_cache_flush_func && m32r_cache_flush_func[0])
2820 emit_library_call (m32r_function_symbol (m32r_cache_flush_func),
2821 LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode,
2822 gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode,
2823 GEN_INT (3), SImode);
2824 }
2825
2826 /* True if X is a reg that can be used as a base reg. */
2827
2828 static bool
m32r_rtx_ok_for_base_p(const_rtx x,bool strict)2829 m32r_rtx_ok_for_base_p (const_rtx x, bool strict)
2830 {
2831 if (! REG_P (x))
2832 return false;
2833
2834 if (strict)
2835 {
2836 if (GPR_P (REGNO (x)))
2837 return true;
2838 }
2839 else
2840 {
2841 if (GPR_P (REGNO (x))
2842 || REGNO (x) == ARG_POINTER_REGNUM
2843 || ! HARD_REGISTER_P (x))
2844 return true;
2845 }
2846
2847 return false;
2848 }
2849
2850 static inline bool
m32r_rtx_ok_for_offset_p(const_rtx x)2851 m32r_rtx_ok_for_offset_p (const_rtx x)
2852 {
2853 return (CONST_INT_P (x) && INT16_P (INTVAL (x)));
2854 }
2855
2856 static inline bool
m32r_legitimate_offset_addres_p(machine_mode mode ATTRIBUTE_UNUSED,const_rtx x,bool strict)2857 m32r_legitimate_offset_addres_p (machine_mode mode ATTRIBUTE_UNUSED,
2858 const_rtx x, bool strict)
2859 {
2860 if (GET_CODE (x) == PLUS
2861 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2862 && m32r_rtx_ok_for_offset_p (XEXP (x, 1)))
2863 return true;
2864
2865 return false;
2866 }
2867
2868 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2869 since more than one instruction will be required. */
2870
2871 static inline bool
m32r_legitimate_lo_sum_addres_p(machine_mode mode,const_rtx x,bool strict)2872 m32r_legitimate_lo_sum_addres_p (machine_mode mode, const_rtx x,
2873 bool strict)
2874 {
2875 if (GET_CODE (x) == LO_SUM
2876 && (mode != BLKmode && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
2877 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2878 && CONSTANT_P (XEXP (x, 1)))
2879 return true;
2880
2881 return false;
2882 }
2883
2884 /* Is this a load and increment operation. */
2885
2886 static inline bool
m32r_load_postinc_p(machine_mode mode,const_rtx x,bool strict)2887 m32r_load_postinc_p (machine_mode mode, const_rtx x, bool strict)
2888 {
2889 if ((mode == SImode || mode == SFmode)
2890 && GET_CODE (x) == POST_INC
2891 && REG_P (XEXP (x, 0))
2892 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2893 return true;
2894
2895 return false;
2896 }
2897
2898 /* Is this an increment/decrement and store operation. */
2899
2900 static inline bool
m32r_store_preinc_predec_p(machine_mode mode,const_rtx x,bool strict)2901 m32r_store_preinc_predec_p (machine_mode mode, const_rtx x, bool strict)
2902 {
2903 if ((mode == SImode || mode == SFmode)
2904 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
2905 && REG_P (XEXP (x, 0)) \
2906 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2907 return true;
2908
2909 return false;
2910 }
2911
2912 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2913
2914 static bool
m32r_legitimate_address_p(machine_mode mode,rtx x,bool strict)2915 m32r_legitimate_address_p (machine_mode mode, rtx x, bool strict)
2916 {
2917 if (m32r_rtx_ok_for_base_p (x, strict)
2918 || m32r_legitimate_offset_addres_p (mode, x, strict)
2919 || m32r_legitimate_lo_sum_addres_p (mode, x, strict)
2920 || m32r_load_postinc_p (mode, x, strict)
2921 || m32r_store_preinc_predec_p (mode, x, strict))
2922 return true;
2923
2924 return false;
2925 }
2926
2927 static void
m32r_conditional_register_usage(void)2928 m32r_conditional_register_usage (void)
2929 {
2930 if (flag_pic)
2931 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2932 }
2933
2934 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2935
2936 We don't allow (plus symbol large-constant) as the relocations can't
2937 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2938 We allow all CONST_DOUBLE's as the md file patterns will force the
2939 constant to memory if they can't handle them. */
2940
2941 static bool
m32r_legitimate_constant_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x)2942 m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2943 {
2944 return !(GET_CODE (x) == CONST
2945 && GET_CODE (XEXP (x, 0)) == PLUS
2946 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2947 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
2948 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
2949 && UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767);
2950 }
2951
2952 /* Implement TARGET_STARTING_FRAME_OFFSET. The frame pointer points at
2953 the same place as the stack pointer, except if alloca has been called. */
2954
2955 static HOST_WIDE_INT
m32r_starting_frame_offset(void)2956 m32r_starting_frame_offset (void)
2957 {
2958 return M32R_STACK_ALIGN (crtl->outgoing_args_size);
2959 }
2960