1 /* $NetBSD: iodevice.h,v 1.19 2024/01/07 07:58:35 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1993, 1994, 1995 Masaru Oki 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Masaru Oki. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * custom CRTC 35 */ 36 struct crtc { 37 unsigned short r00, r01, r02, r03, r04, r05, r06, r07; 38 unsigned short r08, r09, r10, r11, r12, r13, r14, r15; 39 unsigned short r16, r17, r18, r19, r20, r21, r22, r23; 40 char pad0[0x0450]; 41 unsigned short crtctrl; 42 char pad1[0x1b7e]; 43 }; 44 45 /* 46 * custom VIDEO Controller 47 */ 48 struct videoc { 49 unsigned short r0; 50 char pad1[0x00fe]; unsigned short r1; 51 char pad2[0x00fe]; unsigned short r2; 52 char pad3[0x19fe]; 53 }; 54 55 /* 56 * Hitachi HD63450 DMA chip 57 */ 58 struct dmac { 59 unsigned char csr; 60 unsigned char cer; 61 char pad0[2]; unsigned char dcr; 62 unsigned char ocr; 63 unsigned char scr; 64 unsigned char ccr; 65 char pad1[2]; unsigned short mtc; 66 unsigned long mar; 67 char pad2[4]; unsigned long dar; 68 char pad3[2]; unsigned short btc; 69 unsigned long bar; 70 char pad4[5]; unsigned char niv; 71 char pad5[1]; unsigned char eiv; 72 char pad6[1]; unsigned char mfc; 73 char pad7[3]; unsigned char cpr; 74 char pad8[3]; unsigned char dfc; 75 char pad9[7]; unsigned char bfc; 76 char pada[5]; unsigned char gcr; 77 }; 78 79 /* 80 * MC68901 Multi Function Periferal 81 */ 82 struct mfp { 83 char pad00; unsigned char gpip; 84 #define MFP_GPIP_HSYNC 0x80 85 #define MFP_GPIP_VDISP 0x10 86 char pad01; unsigned char aer; 87 char pad02; unsigned char ddr; 88 char pad03; unsigned char iera; 89 #define MFP_TIMERA_STOP 0 90 #define MFP_TIMERA_RESET 0x10 91 char pad04; unsigned char ierb; 92 #define MFP_TIMERB_STOP 0 93 #define MFP_TIMERB_RESET 0x10 94 char pad05; unsigned char ipra; 95 char pad06; unsigned char iprb; 96 char pad07; unsigned char isra; 97 char pad08; unsigned char isrb; 98 char pad09; unsigned char imra; 99 char pad0a; unsigned char imrb; 100 char pad0b; unsigned char vr; 101 char pad0c; unsigned char tacr; 102 char pad0d; unsigned char tbcr; 103 char pad0e; unsigned char tcdcr; 104 char pad0f; unsigned char tadr; 105 char pad10; unsigned char tbdr; 106 char pad11; unsigned char tcdr; 107 char pad12; unsigned char tddr; 108 char pad13; unsigned char scr; 109 char pad14; unsigned char ucr; 110 #define MFP_UCR_EVENP 0x02 111 #define MFP_UCR_PARENB 0x04 112 #define MFP_UCR_SYNCMODE 0x00 113 #define MFP_UCR_ONESB 0x08 114 #define MFP_UCR_1P5SB 0x10 115 #define MFP_UCR_TWOSB 0x18 116 #define MFP_UCR_RW_5 0x60 117 #define MFP_UCR_RW_6 0x40 118 #define MFP_UCR_RW_7 0x20 119 #define MFP_UCR_RW_8 0x00 120 #define MFP_UCR_CLKX16 0x80 121 char pad15; unsigned char rsr; 122 #define MFP_RSR_BF 0x80 123 #define MFP_RSR_OE 0x40 124 #define MFP_RSR_PE 0x20 125 #define MFP_RSR_FE 0x10 126 #define MFP_RSR_SS 0x02 127 #define MFP_RSR_RE 0x01 128 char pad16; unsigned char tsr; 129 #define MFP_TSR_BE 0x80 130 #define MFP_TSR_TE 0x01 131 char pad17; unsigned char udr; 132 char pad[0x1fd0]; 133 }; 134 135 /* 136 * RICOH Real Time Clock RP5C15 137 */ 138 union rtc { 139 struct { 140 char pad0; unsigned char sec; 141 char pad1; unsigned char sec10; 142 char pad2; unsigned char min; 143 char pad3; unsigned char min10; 144 char pad4; unsigned char hour; 145 char pad5; unsigned char hour10; 146 char pad6; unsigned char week; 147 char pad7; unsigned char day; 148 char pad8; unsigned char day10; 149 char pad9; unsigned char mon; 150 char pada; unsigned char mon10; 151 char padb; unsigned char year; 152 char padc; unsigned char year10; 153 char padd; unsigned char mode; 154 char pade; unsigned char test; 155 char padf; unsigned char reset; 156 char pad[0x1fe0]; 157 } bank0; 158 struct { 159 char pad0; unsigned char clkout; 160 char pad1; unsigned char adjust; 161 char pad2; unsigned char al_min; 162 char pad3; unsigned char al_min10; 163 char pad4; unsigned char al_hour; 164 char pad5; unsigned char al_hour10; 165 char pad6; unsigned char al_week; 166 char pad7; unsigned char al_day; 167 char pad8; unsigned char al_day10; 168 char pad9; unsigned char unused; 169 char pada; unsigned char ampm; 170 char padb; unsigned char leep; 171 char padc; unsigned char unused2; 172 char padd; unsigned char mode; 173 char pade; unsigned char test; 174 char padf; unsigned char reset; 175 char pad[0x1fe0]; 176 } bank1; 177 }; 178 179 /* 180 * Centronics printer port (output only) 181 */ 182 struct centro { 183 char pad0; unsigned char data; 184 char pad1; unsigned char strobe; 185 char pad[0x1ffc]; 186 }; 187 188 /* 189 * system control port 190 */ 191 struct sysport { 192 char pad0; unsigned char contrast; 193 char pad1; unsigned char tvctrl; 194 char pad2; unsigned char imageunit; 195 char pad3; unsigned char keyctrl; 196 char pad4; unsigned char waitctrl; /* XXX: X68030 only */ 197 char pad5; unsigned char mpustat; 198 char pad6; unsigned char sramwp; 199 char pad7; unsigned char powoff; 200 char pad[0x1ff0]; 201 }; 202 203 /* 204 * YAMAHA (Operator type-M) chip. 205 */ 206 struct opm { 207 char pad0; unsigned char reg; 208 char pad1; unsigned char data; 209 char pad[0x1ffc]; 210 }; 211 212 /* 213 * OKI MSM6258V ADPCM chip. 214 */ 215 struct adpcm { 216 char pad0; unsigned char stat; 217 char pad1; unsigned char data; 218 char pad[0x1ffc]; 219 }; 220 221 /* 222 * NEC 72065 Floppy Disk Controller 223 */ 224 struct fdc { 225 char pad0; unsigned char stat; 226 char pad1; unsigned char data; 227 char pad2; unsigned char drvstat; 228 char pad3; unsigned char select; 229 char pad[0x1ff8]; 230 }; 231 232 /* 233 * FUJITSU SCSI Protocol Controller MB89352 234 */ 235 struct spc { 236 char pad00; unsigned char bdid; 237 char pad02; unsigned char sctl; 238 char pad04; unsigned char scmd; 239 char pad06; unsigned char tmod; 240 char pad08; unsigned char ints; 241 char pad0a; unsigned char psns; 242 char pad0c; unsigned char ssts; 243 char pad0e; unsigned char serr; 244 char pad10; unsigned char pctl; 245 char pad12; unsigned char mbc; 246 char pad14; unsigned char dreg; 247 char pad16; unsigned char temp; 248 char pad18; unsigned char tch; 249 char pad1a; unsigned char tcm; 250 char pad1c; unsigned char tcl; 251 char pad1e; 252 char pad1f; 253 }; 254 255 /* 256 * Zilog scc. 257 */ 258 struct zschan { 259 unsigned char zc_xxx0; 260 unsigned char zc_csr; /* control and status, and indirect access */ 261 unsigned char zc_xxx1; 262 unsigned char zc_data; /* data */ 263 }; 264 265 struct zsdevice { 266 /* Yes, they are backwards. */ 267 struct zschan zs_chan_b; 268 struct zschan zs_chan_a; 269 char pad4; unsigned char bstat; /* external only : 2 bytes */ 270 char pad[6]; /* --- : 6 bytes */ 271 }; 272 273 struct ppi8255 { 274 char pad0; unsigned char porta; 275 char pad1; unsigned char portb; 276 char pad2; unsigned char portc; 277 char pad3; unsigned char ctrl; 278 char pad[0x1ff8]; 279 }; 280 281 struct ioctlr { 282 char pad0; unsigned char intr; 283 char pad1; unsigned char vect; 284 char pad[0x1ffc]; 285 }; 286 287 /* 288 * YAMAHA YM3802 MIDI chip. 289 */ 290 struct midi { 291 char pad0; unsigned char r00; 292 char pad1; unsigned char r01; 293 char pad2; unsigned char r02; 294 char pad3; unsigned char r03; 295 char pad4; unsigned char rn4; 296 char pad5; unsigned char rn5; 297 char pad6; unsigned char rn6; 298 char pad7; unsigned char rn7; 299 }; 300 301 struct IODEVICE 302 { 303 unsigned short gvram[0x100000]; /* 0x00c00000 */ 304 unsigned char tvram[0x080000]; /* 0x00e00000 */ 305 struct crtc io_crtc; /* 0x00e80000 */ 306 unsigned short gpalet[0x00100]; /* 0x00e82000 */ 307 unsigned short tpalet[0x00100]; /* 0x00e82200 */ 308 struct videoc io_videoc; /* 0x00e82400 */ 309 struct dmac io_dma[4]; /* 0x00e84000 */ 310 char dmapad[0x1f00]; 311 char areapad[0x2000]; /* 0x00e86000 */ 312 struct mfp io_mfp; /* 0x00e88000 */ 313 union rtc io_rtc; /* 0x00e8a000 */ 314 struct centro io_printer; /* 0x00e8c000 */ 315 struct sysport io_sysport; /* 0x00e8e000 */ 316 struct opm io_opm; /* 0x00e90000 */ 317 struct adpcm io_adpcm; 318 struct fdc io_fdc; 319 char spcpad1[0x20]; /* 0x00e96000 */ 320 struct spc io_inspc; /* 0x00e96020 */ 321 char spcpad2[0x1fc0]; 322 struct zsdevice io_inscc; 323 char sccpad[0x1ff0]; 324 struct ppi8255 io_joyport; 325 struct ioctlr io_ctlr; /* 0x00e9c000 */ 326 char fpcprsv[0x2000]; /* 0x00e9e000 */ 327 struct spc io_exspc; /* 0x00ea0000 */ 328 char exscsirom[0x1fe0]; /* */ 329 char sysiorsv1[0xda00]; /* 0x00ea2000 */ 330 struct midi io_midi[2]; /* 0x00eafa00 */ 331 char sysiorsv2[0x1e0]; /* 0x00eafa20 */ 332 struct zsdevice io_exscc[4]; /* 0x00eafc00 */ 333 char sysiorsv3[0x3c0]; /* 0x00eafc40 */ 334 char sprite[0x10000]; /* 0x00eb0000 */ 335 char usriorsv1[0xe000]; /* 0x00ec0000 */ 336 char neptune[0x400]; /* 0x00ece000 */ 337 char usriorsv2[0x1c00]; /* 0x00ece400 */ 338 char io_sram[0x10000]; /* 0x00ed0000 */ 339 char rsv[0x1ff00]; /* 0x00ee0000 */ 340 char psx16550[0x00020]; /* 0x00efff00 */ 341 char rsv2[0x000e0]; /* 0x00efff20 */ 342 char cgrom0_16x16[0x05e00]; /* 0x00f00000 */ 343 char cgrom1_16x16[0x17800]; /* 0x00f05e00 */ 344 char cgrom2_16x16[0x1b2c0]; /* 0x00f1d600 */ 345 char cgrom__rsv1 [0x01740]; /* 0x00f388c0 */ 346 char cgrom0_8x8 [0x00800]; /* 0x00f3a000 */ 347 char cgrom0_8x16 [0x01000]; /* 0x00f3a800 */ 348 char cgrom0_12x12[0x01800]; /* 0x00f3b800 */ 349 char cgrom0_12x24[0x03000]; /* 0x00f3d000 */ 350 char cgrom0_24x24[0x0d380]; /* 0x00f40000 */ 351 char cgrom1_24x24[0x34e00]; /* 0x00f4d380 */ 352 char cgrom2_24x24[0x3d230]; /* 0x00f82180 */ 353 char cgrom__rsv2 [0x00c50]; /* 0x00fbf3b0 */ 354 char inscsirom[0x2000]; /* 0x00fc0000 */ 355 }; 356 357 #if defined(_KERNEL) && !defined(_LOCORE) 358 extern uint8_t *intiobase; /* XXX */ 359 #define IODEVbase ((volatile struct IODEVICE *)intiobase) 360 #endif 361