1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <dev/drm2/drmP.h>
37 #include <dev/drm2/drm_crtc.h>
38 #include <dev/drm2/drm_fourcc.h>
39 #include <dev/drm2/i915/intel_drv.h>
40 #include <dev/drm2/i915/i915_drm.h>
41 #include <dev/drm2/i915/i915_drv.h>
42
43 static void
ivb_update_plane(struct drm_plane * plane,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,uint32_t x,uint32_t y,uint32_t src_w,uint32_t src_h)44 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
45 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
46 unsigned int crtc_w, unsigned int crtc_h,
47 uint32_t x, uint32_t y,
48 uint32_t src_w, uint32_t src_h)
49 {
50 struct drm_device *dev = plane->dev;
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 struct intel_plane *intel_plane = to_intel_plane(plane);
53 int pipe = intel_plane->pipe;
54 u32 sprctl, sprscale = 0;
55 unsigned long sprsurf_offset, linear_offset;
56 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
57
58 sprctl = I915_READ(SPRCTL(pipe));
59
60 /* Mask out pixel format bits in case we change it */
61 sprctl &= ~SPRITE_PIXFORMAT_MASK;
62 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
63 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
64 sprctl &= ~SPRITE_TILED;
65
66 switch (fb->pixel_format) {
67 case DRM_FORMAT_XBGR8888:
68 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
69 break;
70 case DRM_FORMAT_XRGB8888:
71 sprctl |= SPRITE_FORMAT_RGBX888;
72 break;
73 case DRM_FORMAT_YUYV:
74 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
75 break;
76 case DRM_FORMAT_YVYU:
77 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
78 break;
79 case DRM_FORMAT_UYVY:
80 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
81 break;
82 case DRM_FORMAT_VYUY:
83 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
84 break;
85 default:
86 BUG();
87 }
88
89 if (obj->tiling_mode != I915_TILING_NONE)
90 sprctl |= SPRITE_TILED;
91
92 /* must disable */
93 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
94 sprctl |= SPRITE_ENABLE;
95
96 /* Sizes are 0 based */
97 src_w--;
98 src_h--;
99 crtc_w--;
100 crtc_h--;
101
102 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
103
104 /*
105 * IVB workaround: must disable low power watermarks for at least
106 * one frame before enabling scaling. LP watermarks can be re-enabled
107 * when scaling is disabled.
108 */
109 if (crtc_w != src_w || crtc_h != src_h) {
110 if (!dev_priv->sprite_scaling_enabled) {
111 dev_priv->sprite_scaling_enabled = true;
112 intel_update_watermarks(dev);
113 intel_wait_for_vblank(dev, pipe);
114 }
115 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
116 } else {
117 if (dev_priv->sprite_scaling_enabled) {
118 dev_priv->sprite_scaling_enabled = false;
119 /* potentially re-enable LP watermarks */
120 intel_update_watermarks(dev);
121 }
122 }
123
124 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
125 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
126
127 linear_offset = y * fb->pitches[0] + x * pixel_size;
128 sprsurf_offset =
129 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
130 pixel_size, fb->pitches[0]);
131 linear_offset -= sprsurf_offset;
132
133 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
134 * register */
135 if (IS_HASWELL(dev))
136 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
137 else if (obj->tiling_mode != I915_TILING_NONE)
138 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
139 else
140 I915_WRITE(SPRLINOFF(pipe), linear_offset);
141
142 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
143 if (intel_plane->can_scale)
144 I915_WRITE(SPRSCALE(pipe), sprscale);
145 I915_WRITE(SPRCTL(pipe), sprctl);
146 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);
147 POSTING_READ(SPRSURF(pipe));
148 }
149
150 static void
ivb_disable_plane(struct drm_plane * plane)151 ivb_disable_plane(struct drm_plane *plane)
152 {
153 struct drm_device *dev = plane->dev;
154 struct drm_i915_private *dev_priv = dev->dev_private;
155 struct intel_plane *intel_plane = to_intel_plane(plane);
156 int pipe = intel_plane->pipe;
157
158 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
159 /* Can't leave the scaler enabled... */
160 if (intel_plane->can_scale)
161 I915_WRITE(SPRSCALE(pipe), 0);
162 /* Activate double buffered register update */
163 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
164 POSTING_READ(SPRSURF(pipe));
165
166 dev_priv->sprite_scaling_enabled = false;
167 intel_update_watermarks(dev);
168 }
169
170 static int
ivb_update_colorkey(struct drm_plane * plane,struct drm_intel_sprite_colorkey * key)171 ivb_update_colorkey(struct drm_plane *plane,
172 struct drm_intel_sprite_colorkey *key)
173 {
174 struct drm_device *dev = plane->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_plane *intel_plane;
177 u32 sprctl;
178 int ret = 0;
179
180 intel_plane = to_intel_plane(plane);
181
182 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
183 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
184 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
185
186 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
187 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
188 if (key->flags & I915_SET_COLORKEY_DESTINATION)
189 sprctl |= SPRITE_DEST_KEY;
190 else if (key->flags & I915_SET_COLORKEY_SOURCE)
191 sprctl |= SPRITE_SOURCE_KEY;
192 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
193
194 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
195
196 return ret;
197 }
198
199 static void
ivb_get_colorkey(struct drm_plane * plane,struct drm_intel_sprite_colorkey * key)200 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
201 {
202 struct drm_device *dev = plane->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 struct intel_plane *intel_plane;
205 u32 sprctl;
206
207 intel_plane = to_intel_plane(plane);
208
209 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
210 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
211 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
212 key->flags = 0;
213
214 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
215
216 if (sprctl & SPRITE_DEST_KEY)
217 key->flags = I915_SET_COLORKEY_DESTINATION;
218 else if (sprctl & SPRITE_SOURCE_KEY)
219 key->flags = I915_SET_COLORKEY_SOURCE;
220 else
221 key->flags = I915_SET_COLORKEY_NONE;
222 }
223
224 static void
ilk_update_plane(struct drm_plane * plane,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,uint32_t x,uint32_t y,uint32_t src_w,uint32_t src_h)225 ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
226 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
227 unsigned int crtc_w, unsigned int crtc_h,
228 uint32_t x, uint32_t y,
229 uint32_t src_w, uint32_t src_h)
230 {
231 struct drm_device *dev = plane->dev;
232 struct drm_i915_private *dev_priv = dev->dev_private;
233 struct intel_plane *intel_plane = to_intel_plane(plane);
234 int pipe = intel_plane->pipe;
235 unsigned long dvssurf_offset, linear_offset;
236 u32 dvscntr, dvsscale;
237 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
238
239 dvscntr = I915_READ(DVSCNTR(pipe));
240
241 /* Mask out pixel format bits in case we change it */
242 dvscntr &= ~DVS_PIXFORMAT_MASK;
243 dvscntr &= ~DVS_RGB_ORDER_XBGR;
244 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
245 dvscntr &= ~DVS_TILED;
246
247 switch (fb->pixel_format) {
248 case DRM_FORMAT_XBGR8888:
249 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
250 break;
251 case DRM_FORMAT_XRGB8888:
252 dvscntr |= DVS_FORMAT_RGBX888;
253 break;
254 case DRM_FORMAT_YUYV:
255 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
256 break;
257 case DRM_FORMAT_YVYU:
258 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
259 break;
260 case DRM_FORMAT_UYVY:
261 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
262 break;
263 case DRM_FORMAT_VYUY:
264 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
265 break;
266 default:
267 BUG();
268 }
269
270 if (obj->tiling_mode != I915_TILING_NONE)
271 dvscntr |= DVS_TILED;
272
273 if (IS_GEN6(dev))
274 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
275 dvscntr |= DVS_ENABLE;
276
277 /* Sizes are 0 based */
278 src_w--;
279 src_h--;
280 crtc_w--;
281 crtc_h--;
282
283 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
284
285 dvsscale = 0;
286 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
287 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
288
289 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
290 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
291
292 linear_offset = y * fb->pitches[0] + x * pixel_size;
293 dvssurf_offset =
294 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
295 pixel_size, fb->pitches[0]);
296 linear_offset -= dvssurf_offset;
297
298 if (obj->tiling_mode != I915_TILING_NONE)
299 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
300 else
301 I915_WRITE(DVSLINOFF(pipe), linear_offset);
302
303 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
304 I915_WRITE(DVSSCALE(pipe), dvsscale);
305 I915_WRITE(DVSCNTR(pipe), dvscntr);
306 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);
307 POSTING_READ(DVSSURF(pipe));
308 }
309
310 static void
ilk_disable_plane(struct drm_plane * plane)311 ilk_disable_plane(struct drm_plane *plane)
312 {
313 struct drm_device *dev = plane->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 struct intel_plane *intel_plane = to_intel_plane(plane);
316 int pipe = intel_plane->pipe;
317
318 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
319 /* Disable the scaler */
320 I915_WRITE(DVSSCALE(pipe), 0);
321 /* Flush double buffered register updates */
322 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
323 POSTING_READ(DVSSURF(pipe));
324 }
325
326 static void
intel_enable_primary(struct drm_crtc * crtc)327 intel_enable_primary(struct drm_crtc *crtc)
328 {
329 struct drm_device *dev = crtc->dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
332 int reg = DSPCNTR(intel_crtc->plane);
333
334 if (!intel_crtc->primary_disabled)
335 return;
336
337 intel_crtc->primary_disabled = false;
338 intel_update_fbc(dev);
339
340 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
341 }
342
343 static void
intel_disable_primary(struct drm_crtc * crtc)344 intel_disable_primary(struct drm_crtc *crtc)
345 {
346 struct drm_device *dev = crtc->dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
349 int reg = DSPCNTR(intel_crtc->plane);
350
351 if (intel_crtc->primary_disabled)
352 return;
353
354 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
355
356 intel_crtc->primary_disabled = true;
357 intel_update_fbc(dev);
358 }
359
360 static int
ilk_update_colorkey(struct drm_plane * plane,struct drm_intel_sprite_colorkey * key)361 ilk_update_colorkey(struct drm_plane *plane,
362 struct drm_intel_sprite_colorkey *key)
363 {
364 struct drm_device *dev = plane->dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct intel_plane *intel_plane;
367 u32 dvscntr;
368 int ret = 0;
369
370 intel_plane = to_intel_plane(plane);
371
372 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
373 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
374 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
375
376 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
377 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
378 if (key->flags & I915_SET_COLORKEY_DESTINATION)
379 dvscntr |= DVS_DEST_KEY;
380 else if (key->flags & I915_SET_COLORKEY_SOURCE)
381 dvscntr |= DVS_SOURCE_KEY;
382 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
383
384 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
385
386 return ret;
387 }
388
389 static void
ilk_get_colorkey(struct drm_plane * plane,struct drm_intel_sprite_colorkey * key)390 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
391 {
392 struct drm_device *dev = plane->dev;
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct intel_plane *intel_plane;
395 u32 dvscntr;
396
397 intel_plane = to_intel_plane(plane);
398
399 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
400 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
401 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
402 key->flags = 0;
403
404 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
405
406 if (dvscntr & DVS_DEST_KEY)
407 key->flags = I915_SET_COLORKEY_DESTINATION;
408 else if (dvscntr & DVS_SOURCE_KEY)
409 key->flags = I915_SET_COLORKEY_SOURCE;
410 else
411 key->flags = I915_SET_COLORKEY_NONE;
412 }
413
414 static int
intel_update_plane(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,uint32_t src_x,uint32_t src_y,uint32_t src_w,uint32_t src_h)415 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
416 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
417 unsigned int crtc_w, unsigned int crtc_h,
418 uint32_t src_x, uint32_t src_y,
419 uint32_t src_w, uint32_t src_h)
420 {
421 struct drm_device *dev = plane->dev;
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
424 struct intel_plane *intel_plane = to_intel_plane(plane);
425 struct intel_framebuffer *intel_fb;
426 struct drm_i915_gem_object *obj, *old_obj;
427 int pipe = intel_plane->pipe;
428 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
429 pipe);
430 int ret = 0;
431 int x = src_x >> 16, y = src_y >> 16;
432 int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
433 bool disable_primary = false;
434
435 intel_fb = to_intel_framebuffer(fb);
436 obj = intel_fb->obj;
437
438 old_obj = intel_plane->obj;
439
440 src_w = src_w >> 16;
441 src_h = src_h >> 16;
442
443 /* Pipe must be running... */
444 if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
445 return -EINVAL;
446
447 if (crtc_x >= primary_w || crtc_y >= primary_h)
448 return -EINVAL;
449
450 /* Don't modify another pipe's plane */
451 if (intel_plane->pipe != intel_crtc->pipe)
452 return -EINVAL;
453
454 /* Sprite planes can be linear or x-tiled surfaces */
455 switch (obj->tiling_mode) {
456 case I915_TILING_NONE:
457 case I915_TILING_X:
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 /*
464 * Clamp the width & height into the visible area. Note we don't
465 * try to scale the source if part of the visible region is offscreen.
466 * The caller must handle that by adjusting source offset and size.
467 */
468 if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
469 crtc_w += crtc_x;
470 crtc_x = 0;
471 }
472 if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
473 goto out;
474 if ((crtc_x + crtc_w) > primary_w)
475 crtc_w = primary_w - crtc_x;
476
477 if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
478 crtc_h += crtc_y;
479 crtc_y = 0;
480 }
481 if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
482 goto out;
483 if (crtc_y + crtc_h > primary_h)
484 crtc_h = primary_h - crtc_y;
485
486 if (!crtc_w || !crtc_h) /* Again, nothing to display */
487 goto out;
488
489 /*
490 * We may not have a scaler, eg. HSW does not have it any more
491 */
492 if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h))
493 return -EINVAL;
494
495 /*
496 * We can take a larger source and scale it down, but
497 * only so much... 16x is the max on SNB.
498 */
499 if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
500 return -EINVAL;
501
502 /*
503 * If the sprite is completely covering the primary plane,
504 * we can disable the primary and save power.
505 */
506 if ((crtc_x == 0) && (crtc_y == 0) &&
507 (crtc_w == primary_w) && (crtc_h == primary_h))
508 disable_primary = true;
509
510 DRM_LOCK(dev);
511
512 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
513 if (ret)
514 goto out_unlock;
515
516 intel_plane->obj = obj;
517
518 /*
519 * Be sure to re-enable the primary before the sprite is no longer
520 * covering it fully.
521 */
522 if (!disable_primary)
523 intel_enable_primary(crtc);
524
525 intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
526 crtc_w, crtc_h, x, y, src_w, src_h);
527
528 if (disable_primary)
529 intel_disable_primary(crtc);
530
531 /* Unpin old obj after new one is active to avoid ugliness */
532 if (old_obj) {
533 /*
534 * It's fairly common to simply update the position of
535 * an existing object. In that case, we don't need to
536 * wait for vblank to avoid ugliness, we only need to
537 * do the pin & ref bookkeeping.
538 */
539 if (old_obj != obj) {
540 DRM_UNLOCK(dev);
541 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
542 DRM_LOCK(dev);
543 }
544 intel_unpin_fb_obj(old_obj);
545 }
546
547 out_unlock:
548 DRM_UNLOCK(dev);
549 out:
550 return ret;
551 }
552
553 static int
intel_disable_plane(struct drm_plane * plane)554 intel_disable_plane(struct drm_plane *plane)
555 {
556 struct drm_device *dev = plane->dev;
557 struct intel_plane *intel_plane = to_intel_plane(plane);
558 int ret = 0;
559
560 if (plane->crtc)
561 intel_enable_primary(plane->crtc);
562 intel_plane->disable_plane(plane);
563
564 if (!intel_plane->obj)
565 goto out;
566
567 DRM_LOCK(dev);
568 intel_unpin_fb_obj(intel_plane->obj);
569 intel_plane->obj = NULL;
570 DRM_UNLOCK(dev);
571 out:
572
573 return ret;
574 }
575
intel_destroy_plane(struct drm_plane * plane)576 static void intel_destroy_plane(struct drm_plane *plane)
577 {
578 struct intel_plane *intel_plane = to_intel_plane(plane);
579 intel_disable_plane(plane);
580 drm_plane_cleanup(plane);
581 free(intel_plane, DRM_MEM_KMS);
582 }
583
intel_sprite_set_colorkey(struct drm_device * dev,void * data,struct drm_file * file_priv)584 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
585 struct drm_file *file_priv)
586 {
587 struct drm_intel_sprite_colorkey *set = data;
588 struct drm_mode_object *obj;
589 struct drm_plane *plane;
590 struct intel_plane *intel_plane;
591 int ret = 0;
592
593 if (!drm_core_check_feature(dev, DRIVER_MODESET))
594 return -ENODEV;
595
596 /* Make sure we don't try to enable both src & dest simultaneously */
597 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
598 return -EINVAL;
599
600 sx_xlock(&dev->mode_config.mutex);
601
602 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
603 if (!obj) {
604 ret = -EINVAL;
605 goto out_unlock;
606 }
607
608 plane = obj_to_plane(obj);
609 intel_plane = to_intel_plane(plane);
610 ret = intel_plane->update_colorkey(plane, set);
611
612 out_unlock:
613 sx_xunlock(&dev->mode_config.mutex);
614 return ret;
615 }
616
intel_sprite_get_colorkey(struct drm_device * dev,void * data,struct drm_file * file_priv)617 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
618 struct drm_file *file_priv)
619 {
620 struct drm_intel_sprite_colorkey *get = data;
621 struct drm_mode_object *obj;
622 struct drm_plane *plane;
623 struct intel_plane *intel_plane;
624 int ret = 0;
625
626 if (!drm_core_check_feature(dev, DRIVER_MODESET))
627 return -ENODEV;
628
629 sx_xlock(&dev->mode_config.mutex);
630
631 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
632 if (!obj) {
633 ret = -EINVAL;
634 goto out_unlock;
635 }
636
637 plane = obj_to_plane(obj);
638 intel_plane = to_intel_plane(plane);
639 intel_plane->get_colorkey(plane, get);
640
641 out_unlock:
642 sx_xunlock(&dev->mode_config.mutex);
643 return ret;
644 }
645
646 static const struct drm_plane_funcs intel_plane_funcs = {
647 .update_plane = intel_update_plane,
648 .disable_plane = intel_disable_plane,
649 .destroy = intel_destroy_plane,
650 };
651
652 static uint32_t ilk_plane_formats[] = {
653 DRM_FORMAT_XRGB8888,
654 DRM_FORMAT_YUYV,
655 DRM_FORMAT_YVYU,
656 DRM_FORMAT_UYVY,
657 DRM_FORMAT_VYUY,
658 };
659
660 static uint32_t snb_plane_formats[] = {
661 DRM_FORMAT_XBGR8888,
662 DRM_FORMAT_XRGB8888,
663 DRM_FORMAT_YUYV,
664 DRM_FORMAT_YVYU,
665 DRM_FORMAT_UYVY,
666 DRM_FORMAT_VYUY,
667 };
668
669 int
intel_plane_init(struct drm_device * dev,enum pipe pipe)670 intel_plane_init(struct drm_device *dev, enum pipe pipe)
671 {
672 struct intel_plane *intel_plane;
673 unsigned long possible_crtcs;
674 const uint32_t *plane_formats;
675 int num_plane_formats;
676 int ret;
677
678 if (INTEL_INFO(dev)->gen < 5)
679 return -ENODEV;
680
681 intel_plane = malloc(sizeof(struct intel_plane), DRM_MEM_KMS, M_WAITOK | M_ZERO);
682 if (!intel_plane)
683 return -ENOMEM;
684
685 switch (INTEL_INFO(dev)->gen) {
686 case 5:
687 case 6:
688 intel_plane->can_scale = true;
689 intel_plane->max_downscale = 16;
690 intel_plane->update_plane = ilk_update_plane;
691 intel_plane->disable_plane = ilk_disable_plane;
692 intel_plane->update_colorkey = ilk_update_colorkey;
693 intel_plane->get_colorkey = ilk_get_colorkey;
694
695 if (IS_GEN6(dev)) {
696 plane_formats = snb_plane_formats;
697 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
698 } else {
699 plane_formats = ilk_plane_formats;
700 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
701 }
702 break;
703
704 case 7:
705 if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev))
706 intel_plane->can_scale = false;
707 else
708 intel_plane->can_scale = true;
709 intel_plane->max_downscale = 2;
710 intel_plane->update_plane = ivb_update_plane;
711 intel_plane->disable_plane = ivb_disable_plane;
712 intel_plane->update_colorkey = ivb_update_colorkey;
713 intel_plane->get_colorkey = ivb_get_colorkey;
714
715 plane_formats = snb_plane_formats;
716 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
717 break;
718
719 default:
720 free(intel_plane, DRM_MEM_KMS);
721 return -ENODEV;
722 }
723
724 intel_plane->pipe = pipe;
725 possible_crtcs = (1 << pipe);
726 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
727 &intel_plane_funcs,
728 plane_formats, num_plane_formats,
729 false);
730 if (ret)
731 free(intel_plane, DRM_MEM_KMS);
732
733 return ret;
734 }
735