1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 #define drm_i915_private inteldrm_softc
31
32 #include "i915_reg_defs.h"
33 #include "intel_display_limits.h"
34
35 enum drm_scaling_filter;
36 struct dpll;
37 struct drm_atomic_state;
38 struct drm_connector;
39 struct drm_device;
40 struct drm_display_mode;
41 struct drm_encoder;
42 struct drm_file;
43 struct drm_format_info;
44 struct drm_framebuffer;
45 struct drm_i915_gem_object;
46 struct drm_i915_private;
47 struct drm_mode_fb_cmd2;
48 struct drm_modeset_acquire_ctx;
49 struct drm_plane;
50 struct drm_plane_state;
51 struct i915_address_space;
52 struct i915_gtt_view;
53 struct intel_atomic_state;
54 struct intel_crtc;
55 struct intel_crtc_state;
56 struct intel_digital_port;
57 struct intel_dp;
58 struct intel_encoder;
59 struct intel_initial_plane_config;
60 struct intel_link_m_n;
61 struct intel_plane;
62 struct intel_plane_state;
63 struct intel_power_domain_mask;
64 struct intel_remapped_info;
65 struct intel_rotation_info;
66 struct pci_dev;
67 struct work_struct;
68
69
70 #define pipe_name(p) ((p) + 'A')
71
transcoder_name(enum transcoder transcoder)72 static inline const char *transcoder_name(enum transcoder transcoder)
73 {
74 switch (transcoder) {
75 case TRANSCODER_A:
76 return "A";
77 case TRANSCODER_B:
78 return "B";
79 case TRANSCODER_C:
80 return "C";
81 case TRANSCODER_D:
82 return "D";
83 case TRANSCODER_EDP:
84 return "EDP";
85 case TRANSCODER_DSI_A:
86 return "DSI A";
87 case TRANSCODER_DSI_C:
88 return "DSI C";
89 default:
90 return "<invalid>";
91 }
92 }
93
transcoder_is_dsi(enum transcoder transcoder)94 static inline bool transcoder_is_dsi(enum transcoder transcoder)
95 {
96 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
97 }
98
99 /*
100 * Global legacy plane identifier. Valid only for primary/sprite
101 * planes on pre-g4x, and only for primary planes on g4x-bdw.
102 */
103 enum i9xx_plane_id {
104 PLANE_A,
105 PLANE_B,
106 PLANE_C,
107 };
108
109 #define plane_name(p) ((p) + 'A')
110
111 #define for_each_plane_id_on_crtc(__crtc, __p) \
112 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
113 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
114
115 #define for_each_dbuf_slice(__dev_priv, __slice) \
116 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
117 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
118
119 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
120 for_each_dbuf_slice((__dev_priv), (__slice)) \
121 for_each_if((__mask) & BIT(__slice))
122
123 #define port_name(p) ((p) + 'A')
124
125 /*
126 * Ports identifier referenced from other drivers.
127 * Expected to remain stable over time
128 */
port_identifier(enum port port)129 static inline const char *port_identifier(enum port port)
130 {
131 switch (port) {
132 case PORT_A:
133 return "Port A";
134 case PORT_B:
135 return "Port B";
136 case PORT_C:
137 return "Port C";
138 case PORT_D:
139 return "Port D";
140 case PORT_E:
141 return "Port E";
142 case PORT_F:
143 return "Port F";
144 case PORT_G:
145 return "Port G";
146 case PORT_H:
147 return "Port H";
148 case PORT_I:
149 return "Port I";
150 default:
151 return "<invalid>";
152 }
153 }
154
155 enum tc_port {
156 TC_PORT_NONE = -1,
157
158 TC_PORT_1 = 0,
159 TC_PORT_2,
160 TC_PORT_3,
161 TC_PORT_4,
162 TC_PORT_5,
163 TC_PORT_6,
164
165 I915_MAX_TC_PORTS
166 };
167
168 enum aux_ch {
169 AUX_CH_NONE = -1,
170
171 AUX_CH_A,
172 AUX_CH_B,
173 AUX_CH_C,
174 AUX_CH_D,
175 AUX_CH_E, /* ICL+ */
176 AUX_CH_F,
177 AUX_CH_G,
178 AUX_CH_H,
179 AUX_CH_I,
180
181 /* tgl+ */
182 AUX_CH_USBC1 = AUX_CH_D,
183 AUX_CH_USBC2,
184 AUX_CH_USBC3,
185 AUX_CH_USBC4,
186 AUX_CH_USBC5,
187 AUX_CH_USBC6,
188
189 /* XE_LPD repositions D/E offsets and bitfields */
190 AUX_CH_D_XELPD = AUX_CH_USBC5,
191 AUX_CH_E_XELPD,
192 };
193
194 enum phy {
195 PHY_NONE = -1,
196
197 PHY_A = 0,
198 PHY_B,
199 PHY_C,
200 PHY_D,
201 PHY_E,
202 PHY_F,
203 PHY_G,
204 PHY_H,
205 PHY_I,
206
207 I915_MAX_PHYS
208 };
209
210 #define phy_name(a) ((a) + 'A')
211
212 enum phy_fia {
213 FIA1,
214 FIA2,
215 FIA3,
216 };
217
218 #define for_each_hpd_pin(__pin) \
219 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
220
221 #define for_each_pipe(__dev_priv, __p) \
222 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
223 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
224
225 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
226 for_each_pipe(__dev_priv, __p) \
227 for_each_if((__mask) & BIT(__p))
228
229 #define for_each_cpu_transcoder(__dev_priv, __t) \
230 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
231 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
232
233 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
234 for_each_cpu_transcoder(__dev_priv, __t) \
235 for_each_if ((__mask) & BIT(__t))
236
237 #define for_each_sprite(__dev_priv, __p, __s) \
238 for ((__s) = 0; \
239 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
240 (__s)++)
241
242 #define for_each_port(__port) \
243 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
244
245 #define for_each_port_masked(__port, __ports_mask) \
246 for_each_port(__port) \
247 for_each_if((__ports_mask) & BIT(__port))
248
249 #define for_each_phy_masked(__phy, __phys_mask) \
250 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
251 for_each_if((__phys_mask) & BIT(__phy))
252
253 #define for_each_crtc(dev, crtc) \
254 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
255
256 #define for_each_intel_plane(dev, intel_plane) \
257 list_for_each_entry(intel_plane, \
258 &(dev)->mode_config.plane_list, \
259 base.head)
260
261 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
262 list_for_each_entry(intel_plane, \
263 &(dev)->mode_config.plane_list, \
264 base.head) \
265 for_each_if((plane_mask) & \
266 drm_plane_mask(&intel_plane->base))
267
268 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
269 list_for_each_entry(intel_plane, \
270 &(dev)->mode_config.plane_list, \
271 base.head) \
272 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
273
274 #define for_each_intel_crtc(dev, intel_crtc) \
275 list_for_each_entry(intel_crtc, \
276 &(dev)->mode_config.crtc_list, \
277 base.head)
278
279 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
280 list_for_each_entry(intel_crtc, \
281 &(dev)->mode_config.crtc_list, \
282 base.head) \
283 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
284
285 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \
286 list_for_each_entry_reverse((intel_crtc), \
287 &(dev)->mode_config.crtc_list, \
288 base.head) \
289 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
290
291 #define for_each_intel_encoder(dev, intel_encoder) \
292 list_for_each_entry(intel_encoder, \
293 &(dev)->mode_config.encoder_list, \
294 base.head)
295
296 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
297 list_for_each_entry(intel_encoder, \
298 &(dev)->mode_config.encoder_list, \
299 base.head) \
300 for_each_if((encoder_mask) & \
301 drm_encoder_mask(&intel_encoder->base))
302
303 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
304 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
305 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
306 intel_encoder_can_psr(intel_encoder))
307
308 #define for_each_intel_dp(dev, intel_encoder) \
309 for_each_intel_encoder(dev, intel_encoder) \
310 for_each_if(intel_encoder_is_dp(intel_encoder))
311
312 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
313 for_each_intel_encoder((dev), (intel_encoder)) \
314 for_each_if(intel_encoder_can_psr(intel_encoder))
315
316 #define for_each_intel_connector_iter(intel_connector, iter) \
317 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
318
319 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
320 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
321 for_each_if((intel_encoder)->base.crtc == (__crtc))
322
323 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
324 for ((__i) = 0; \
325 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
326 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
327 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
328 (__i)++) \
329 for_each_if(plane)
330
331 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
332 for ((__i) = 0; \
333 (__i) < (__state)->base.dev->mode_config.num_crtc && \
334 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
335 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
336 (__i)++) \
337 for_each_if(crtc)
338
339 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
340 for ((__i) = 0; \
341 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
342 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
343 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
344 (__i)++) \
345 for_each_if(plane)
346
347 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
348 for ((__i) = 0; \
349 (__i) < (__state)->base.dev->mode_config.num_crtc && \
350 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
351 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
352 (__i)++) \
353 for_each_if(crtc)
354
355 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
356 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
357 (__i) >= 0 && \
358 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
359 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
360 (__i)--) \
361 for_each_if(crtc)
362
363 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
364 for ((__i) = 0; \
365 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
366 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
367 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
368 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
369 (__i)++) \
370 for_each_if(plane)
371
372 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
373 for ((__i) = 0; \
374 (__i) < (__state)->base.dev->mode_config.num_crtc && \
375 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
376 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
377 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
378 (__i)++) \
379 for_each_if(crtc)
380
381 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
382 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
383 (__i) >= 0 && \
384 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
385 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
386 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
387 (__i)--) \
388 for_each_if(crtc)
389
390 #define intel_atomic_crtc_state_for_each_plane_state( \
391 plane, plane_state, \
392 crtc_state) \
393 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
394 ((crtc_state)->uapi.plane_mask)) \
395 for_each_if ((plane_state = \
396 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
397
398 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
399 for ((__i) = 0; \
400 (__i) < (__state)->base.num_connector; \
401 (__i)++) \
402 for_each_if ((__state)->base.connectors[__i].ptr && \
403 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
404 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
405
406 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
407 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
408 struct intel_crtc *crtc);
409 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
410 u8 active_pipes);
411 void intel_link_compute_m_n(u16 bpp, int nlanes,
412 int pixel_clock, int link_clock,
413 int bw_overhead,
414 struct intel_link_m_n *m_n);
415 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
416 u32 pixel_format, u64 modifier);
417 enum drm_mode_status
418 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
419 const struct drm_display_mode *mode,
420 bool joiner);
421 enum drm_mode_status
422 intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
423 const struct drm_display_mode *mode);
424 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
425 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
426 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
427 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
428 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
429 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
430 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
431 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
432 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
433 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
434 const struct intel_crtc_state *pipe_config,
435 bool fastset);
436
437 void intel_plane_destroy(struct drm_plane *plane);
438 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
439 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
440 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
441 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
442 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
443 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
444 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
445 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
446 const char *name, u32 reg, int ref_freq);
447 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
448 const char *name, u32 reg);
449 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
450 unsigned int intel_fb_xy_to_linear(int x, int y,
451 const struct intel_plane_state *state,
452 int plane);
453 void intel_add_fb_offsets(int *x, int *y,
454 const struct intel_plane_state *state, int plane);
455 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
456 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
457 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
458 void intel_encoder_destroy(struct drm_encoder *encoder);
459 struct drm_display_mode *
460 intel_encoder_current_mode(struct intel_encoder *encoder);
461 void intel_encoder_get_config(struct intel_encoder *encoder,
462 struct intel_crtc_state *crtc_state);
463 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
464 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
465 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
466 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
467 enum port port);
468
469 enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
470 bool intel_encoder_is_combo(struct intel_encoder *encoder);
471 bool intel_encoder_is_snps(struct intel_encoder *encoder);
472 bool intel_encoder_is_tc(struct intel_encoder *encoder);
473 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
474
475 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
476 struct drm_file *file_priv);
477
478 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
479 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
480 struct intel_digital_port *dig_port,
481 unsigned int expected_mask);
482 struct drm_framebuffer *
483 intel_framebuffer_create(struct drm_i915_gem_object *obj,
484 struct drm_mode_fb_cmd2 *mode_cmd);
485
486 bool intel_fuzzy_clock_check(int clock1, int clock2);
487
488 void intel_zero_m_n(struct intel_link_m_n *m_n);
489 void intel_set_m_n(struct drm_i915_private *i915,
490 const struct intel_link_m_n *m_n,
491 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
492 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
493 void intel_get_m_n(struct drm_i915_private *i915,
494 struct intel_link_m_n *m_n,
495 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
496 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
497 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
498 enum transcoder transcoder);
499 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
500 enum transcoder cpu_transcoder,
501 const struct intel_link_m_n *m_n);
502 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
503 enum transcoder cpu_transcoder,
504 const struct intel_link_m_n *m_n);
505 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
506 enum transcoder cpu_transcoder,
507 struct intel_link_m_n *m_n);
508 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
509 enum transcoder cpu_transcoder,
510 struct intel_link_m_n *m_n);
511 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
512 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
513 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
514 enum intel_display_power_domain
515 intel_aux_power_domain(struct intel_digital_port *dig_port);
516 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
517 struct intel_crtc_state *crtc_state);
518 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
519
520 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
521 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
522
523 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
524
525 struct intel_encoder *
526 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
527 const struct intel_crtc_state *crtc_state);
528 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
529 struct intel_plane *plane);
530 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
531 struct intel_plane_state *plane_state,
532 bool visible);
533 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
534
535 void intel_update_watermarks(struct drm_i915_private *i915);
536
537 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
538 struct intel_crtc *crtc);
539
540 /* modesetting */
541 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
542 const char *reason, u8 pipe_mask);
543 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
544 const char *reason);
545 int intel_modeset_commit_pipes(struct drm_i915_private *i915,
546 u8 pipe_mask,
547 struct drm_modeset_acquire_ctx *ctx);
548 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
549 struct intel_power_domain_mask *old_domains);
550 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
551 struct intel_power_domain_mask *domains);
552
553 /* interface for intel_display_driver.c */
554 void intel_setup_outputs(struct drm_i915_private *i915);
555 int intel_initial_commit(struct drm_device *dev);
556 void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
557 void intel_update_czclk(struct drm_i915_private *i915);
558 void intel_atomic_helper_free_state_worker(struct work_struct *work);
559 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
560 const struct drm_display_mode *mode);
561 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
562 bool nonblock);
563
564 void intel_hpd_poll_fini(struct drm_i915_private *i915);
565
566 /* modesetting asserts */
567 void assert_transcoder(struct drm_i915_private *dev_priv,
568 enum transcoder cpu_transcoder, bool state);
569 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
570 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
571
572 bool assert_port_valid(struct drm_i915_private *i915, enum port port);
573
574 /*
575 * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity
576 * checks to check for unexpected conditions which may not necessarily be a user
577 * visible problem. This will either WARN() or DRM_ERROR() depending on the
578 * verbose_state_checks module param, to enable distros and users to tailor
579 * their preferred amount of i915 abrt spam.
580 */
581 #define I915_STATE_WARN(__i915, condition, format...) ({ \
582 struct drm_device *drm = &(__i915)->drm; \
583 int __ret_warn_on = !!(condition); \
584 if (unlikely(__ret_warn_on)) \
585 if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \
586 drm_err(drm, format); \
587 unlikely(__ret_warn_on); \
588 })
589
590 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
591
592 #endif
593