1 /*-
2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
18 * permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71 /*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77 /*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/errno.h>
85 #include <sys/kernel.h>
86 #include <sys/sockio.h>
87 #include <sys/mbuf.h>
88 #include <sys/socket.h>
89 #include <sys/syslog.h>
90
91 #include <sys/module.h>
92 #include <sys/bus.h>
93
94 #include <machine/bus.h>
95 #include <machine/resource.h>
96 #include <sys/rman.h>
97
98 #include <net/ethernet.h>
99 #include <net/if.h>
100 #include <net/if_var.h>
101 #include <net/if_arp.h>
102 #include <net/if_dl.h>
103 #include <net/if_types.h>
104 #include <net/if_mib.h>
105
106 #ifdef INET
107 #include <netinet/in.h>
108 #include <netinet/in_systm.h>
109 #include <netinet/in_var.h>
110 #include <netinet/ip.h>
111 #endif
112
113 #include <net/bpf.h>
114 #include <net/bpfdesc.h>
115
116 #include <dev/sn/if_snreg.h>
117 #include <dev/sn/if_snvar.h>
118
119 /* Exported variables */
120 devclass_t sn_devclass;
121
122 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
123
124 static void snresume(struct ifnet *);
125
126 static void snintr_locked(struct sn_softc *);
127 static void sninit_locked(void *);
128 static void snstart_locked(struct ifnet *);
129
130 static void sninit(void *);
131 static void snread(struct ifnet *);
132 static void snstart(struct ifnet *);
133 static void snstop(struct sn_softc *);
134 static void snwatchdog(void *);
135
136 static void sn_setmcast(struct sn_softc *);
137 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
138
139 /* I (GB) have been unlucky getting the hardware padding
140 * to work properly.
141 */
142 #define SW_PAD
143
144 static const char *chip_ids[15] = {
145 NULL, NULL, NULL,
146 /* 3 */ "SMC91C90/91C92",
147 /* 4 */ "SMC91C94/91C96",
148 /* 5 */ "SMC91C95",
149 NULL,
150 /* 7 */ "SMC91C100",
151 /* 8 */ "SMC91C100FD",
152 /* 9 */ "SMC91C110",
153 NULL, NULL,
154 NULL, NULL, NULL
155 };
156
157 int
sn_attach(device_t dev)158 sn_attach(device_t dev)
159 {
160 struct sn_softc *sc = device_get_softc(dev);
161 struct ifnet *ifp;
162 uint16_t i;
163 uint8_t *p;
164 int rev;
165 uint16_t address;
166 int err;
167 u_char eaddr[6];
168
169 ifp = sc->ifp = if_alloc(IFT_ETHER);
170 if (ifp == NULL) {
171 device_printf(dev, "can not if_alloc()\n");
172 return (ENOSPC);
173 }
174
175 SN_LOCK_INIT(sc);
176 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
177 snstop(sc);
178 sc->pages_wanted = -1;
179
180 if (bootverbose || 1) {
181 SMC_SELECT_BANK(sc, 3);
182 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
183 if (chip_ids[rev])
184 device_printf(dev, " %s ", chip_ids[rev]);
185 else
186 device_printf(dev, " unsupported chip: rev %d ", rev);
187 SMC_SELECT_BANK(sc, 1);
188 i = CSR_READ_2(sc, CONFIG_REG_W);
189 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
190 }
191
192 /*
193 * Read the station address from the chip. The MAC address is bank 1,
194 * regs 4 - 9
195 */
196 SMC_SELECT_BANK(sc, 1);
197 p = (uint8_t *) eaddr;
198 for (i = 0; i < 6; i += 2) {
199 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
200 p[i + 1] = address >> 8;
201 p[i] = address & 0xFF;
202 }
203 ifp->if_softc = sc;
204 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
205 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
206 ifp->if_start = snstart;
207 ifp->if_ioctl = snioctl;
208 ifp->if_init = sninit;
209 ifp->if_baudrate = 10000000;
210 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
211 ifp->if_snd.ifq_maxlen = ifqmaxlen;
212 IFQ_SET_READY(&ifp->if_snd);
213
214 ether_ifattach(ifp, eaddr);
215
216 /*
217 * Activate the interrupt so we can get card interrupts. This
218 * needs to be done last so that we don't have/hold the lock
219 * during startup to avoid LORs in the network layer.
220 */
221 if ((err = bus_setup_intr(dev, sc->irq_res,
222 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
223 &sc->intrhand)) != 0) {
224 sn_detach(dev);
225 return err;
226 }
227 return 0;
228 }
229
230
231 int
sn_detach(device_t dev)232 sn_detach(device_t dev)
233 {
234 struct sn_softc *sc = device_get_softc(dev);
235 struct ifnet *ifp = sc->ifp;
236
237 ether_ifdetach(ifp);
238 SN_LOCK(sc);
239 snstop(sc);
240 SN_UNLOCK(sc);
241 callout_drain(&sc->watchdog);
242 sn_deactivate(dev);
243 if_free(ifp);
244 SN_LOCK_DESTROY(sc);
245 return 0;
246 }
247
248 static void
sninit(void * xsc)249 sninit(void *xsc)
250 {
251 struct sn_softc *sc = xsc;
252 SN_LOCK(sc);
253 sninit_locked(sc);
254 SN_UNLOCK(sc);
255 }
256
257 /*
258 * Reset and initialize the chip
259 */
260 static void
sninit_locked(void * xsc)261 sninit_locked(void *xsc)
262 {
263 struct sn_softc *sc = xsc;
264 struct ifnet *ifp = sc->ifp;
265 int flags;
266 int mask;
267
268 SN_ASSERT_LOCKED(sc);
269
270 /*
271 * This resets the registers mostly to defaults, but doesn't affect
272 * EEPROM. After the reset cycle, we pause briefly for the chip to
273 * be happy.
274 */
275 SMC_SELECT_BANK(sc, 0);
276 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
277 SMC_DELAY(sc);
278 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
279 SMC_DELAY(sc);
280 SMC_DELAY(sc);
281
282 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
283
284 /*
285 * Set the control register to automatically release succesfully
286 * transmitted packets (making the best use out of our limited
287 * memory) and to enable the EPH interrupt on certain TX errors.
288 */
289 SMC_SELECT_BANK(sc, 1);
290 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
291 CTR_CR_ENABLE | CTR_LE_ENABLE));
292
293 /* Set squelch level to 240mV (default 480mV) */
294 flags = CSR_READ_2(sc, CONFIG_REG_W);
295 flags |= CR_SET_SQLCH;
296 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
297
298 /*
299 * Reset the MMU and wait for it to be un-busy.
300 */
301 SMC_SELECT_BANK(sc, 2);
302 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
303 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
304 ;
305
306 /*
307 * Disable all interrupts
308 */
309 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
310
311 sn_setmcast(sc);
312
313 /*
314 * Set the transmitter control. We want it enabled.
315 */
316 flags = TCR_ENABLE;
317
318 #ifndef SW_PAD
319 /*
320 * I (GB) have been unlucky getting this to work.
321 */
322 flags |= TCR_PAD_ENABLE;
323 #endif /* SW_PAD */
324
325 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
326
327
328 /*
329 * Now, enable interrupts
330 */
331 SMC_SELECT_BANK(sc, 2);
332
333 mask = IM_EPH_INT |
334 IM_RX_OVRN_INT |
335 IM_RCV_INT |
336 IM_TX_INT;
337
338 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
339 sc->intr_mask = mask;
340 sc->pages_wanted = -1;
341
342
343 /*
344 * Mark the interface running but not active.
345 */
346 ifp->if_drv_flags |= IFF_DRV_RUNNING;
347 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
348 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
349
350 /*
351 * Attempt to push out any waiting packets.
352 */
353 snstart_locked(ifp);
354 }
355
356 static void
snstart(struct ifnet * ifp)357 snstart(struct ifnet *ifp)
358 {
359 struct sn_softc *sc = ifp->if_softc;
360 SN_LOCK(sc);
361 snstart_locked(ifp);
362 SN_UNLOCK(sc);
363 }
364
365
366 static void
snstart_locked(struct ifnet * ifp)367 snstart_locked(struct ifnet *ifp)
368 {
369 struct sn_softc *sc = ifp->if_softc;
370 u_int len;
371 struct mbuf *m;
372 struct mbuf *top;
373 int pad;
374 int mask;
375 uint16_t length;
376 uint16_t numPages;
377 uint8_t packet_no;
378 int time_out;
379 int junk = 0;
380
381 SN_ASSERT_LOCKED(sc);
382
383 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
384 return;
385 if (sc->pages_wanted != -1) {
386 if_printf(ifp, "snstart() while memory allocation pending\n");
387 return;
388 }
389 startagain:
390
391 /*
392 * Sneak a peek at the next packet
393 */
394 m = ifp->if_snd.ifq_head;
395 if (m == 0)
396 return;
397 /*
398 * Compute the frame length and set pad to give an overall even
399 * number of bytes. Below we assume that the packet length is even.
400 */
401 for (len = 0, top = m; m; m = m->m_next)
402 len += m->m_len;
403
404 pad = (len & 1);
405
406 /*
407 * We drop packets that are too large. Perhaps we should truncate
408 * them instead?
409 */
410 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
411 if_printf(ifp, "large packet discarded (A)\n");
412 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
413 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
414 m_freem(m);
415 goto readcheck;
416 }
417 #ifdef SW_PAD
418
419 /*
420 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
421 */
422 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
423 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
424
425 #endif /* SW_PAD */
426
427 length = pad + len;
428
429 /*
430 * The MMU wants the number of pages to be the number of 256 byte
431 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
432 * include space for the status word, byte count and control bytes in
433 * the allocation request.
434 */
435 numPages = (length + 6) >> 8;
436
437
438 /*
439 * Now, try to allocate the memory
440 */
441 SMC_SELECT_BANK(sc, 2);
442 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
443
444 /*
445 * Wait a short amount of time to see if the allocation request
446 * completes. Otherwise, I enable the interrupt and wait for
447 * completion asynchronously.
448 */
449
450 time_out = MEMORY_WAIT_TIME;
451 do {
452 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
453 break;
454 } while (--time_out);
455
456 if (!time_out || junk > 10) {
457
458 /*
459 * No memory now. Oh well, wait until the chip finds memory
460 * later. Remember how many pages we were asking for and
461 * enable the allocation completion interrupt. Also set a
462 * watchdog in case we miss the interrupt. We mark the
463 * interface active since there is no point in attempting an
464 * snstart() until after the memory is available.
465 */
466 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
467 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
468 sc->intr_mask = mask;
469
470 sc->timer = 1;
471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
472 sc->pages_wanted = numPages;
473 return;
474 }
475 /*
476 * The memory allocation completed. Check the results.
477 */
478 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
479 if (packet_no & ARR_FAILED) {
480 if (junk++ > 10)
481 if_printf(ifp, "Memory allocation failed\n");
482 goto startagain;
483 }
484 /*
485 * We have a packet number, so tell the card to use it.
486 */
487 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
488
489 /*
490 * Point to the beginning of the packet
491 */
492 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
493
494 /*
495 * Send the packet length (+6 for status, length and control byte)
496 * and the status word (set to zeros)
497 */
498 CSR_WRITE_2(sc, DATA_REG_W, 0);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
500 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
501
502 /*
503 * Get the packet from the kernel. This will include the Ethernet
504 * frame header, MAC Addresses etc.
505 */
506 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
507
508 /*
509 * Push out the data to the card.
510 */
511 for (top = m; m != 0; m = m->m_next) {
512
513 /*
514 * Push out words.
515 */
516 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
517 m->m_len / 2);
518
519 /*
520 * Push out remaining byte.
521 */
522 if (m->m_len & 1)
523 CSR_WRITE_1(sc, DATA_REG_B,
524 *(mtod(m, caddr_t) + m->m_len - 1));
525 }
526
527 /*
528 * Push out padding.
529 */
530 while (pad > 1) {
531 CSR_WRITE_2(sc, DATA_REG_W, 0);
532 pad -= 2;
533 }
534 if (pad)
535 CSR_WRITE_1(sc, DATA_REG_B, 0);
536
537 /*
538 * Push out control byte and unused packet byte The control byte is 0
539 * meaning the packet is even lengthed and no special CRC handling is
540 * desired.
541 */
542 CSR_WRITE_2(sc, DATA_REG_W, 0);
543
544 /*
545 * Enable the interrupts and let the chipset deal with it Also set a
546 * watchdog in case we miss the interrupt.
547 */
548 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
549 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
550 sc->intr_mask = mask;
551
552 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
553
554 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
555 sc->timer = 1;
556
557 BPF_MTAP(ifp, top);
558
559 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
560 m_freem(top);
561
562
563 readcheck:
564
565 /*
566 * Is another packet coming in? We don't want to overflow the tiny
567 * RX FIFO. If nothing has arrived then attempt to queue another
568 * transmit packet.
569 */
570 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
571 goto startagain;
572 return;
573 }
574
575
576
577 /* Resume a packet transmit operation after a memory allocation
578 * has completed.
579 *
580 * This is basically a hacked up copy of snstart() which handles
581 * a completed memory allocation the same way snstart() does.
582 * It then passes control to snstart to handle any other queued
583 * packets.
584 */
585 static void
snresume(struct ifnet * ifp)586 snresume(struct ifnet *ifp)
587 {
588 struct sn_softc *sc = ifp->if_softc;
589 u_int len;
590 struct mbuf *m;
591 struct mbuf *top;
592 int pad;
593 int mask;
594 uint16_t length;
595 uint16_t numPages;
596 uint16_t pages_wanted;
597 uint8_t packet_no;
598
599 if (sc->pages_wanted < 0)
600 return;
601
602 pages_wanted = sc->pages_wanted;
603 sc->pages_wanted = -1;
604
605 /*
606 * Sneak a peek at the next packet
607 */
608 m = ifp->if_snd.ifq_head;
609 if (m == 0) {
610 if_printf(ifp, "snresume() with nothing to send\n");
611 return;
612 }
613 /*
614 * Compute the frame length and set pad to give an overall even
615 * number of bytes. Below we assume that the packet length is even.
616 */
617 for (len = 0, top = m; m; m = m->m_next)
618 len += m->m_len;
619
620 pad = (len & 1);
621
622 /*
623 * We drop packets that are too large. Perhaps we should truncate
624 * them instead?
625 */
626 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
627 if_printf(ifp, "large packet discarded (B)\n");
628 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
629 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
630 m_freem(m);
631 return;
632 }
633 #ifdef SW_PAD
634
635 /*
636 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
637 */
638 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
639 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
640
641 #endif /* SW_PAD */
642
643 length = pad + len;
644
645
646 /*
647 * The MMU wants the number of pages to be the number of 256 byte
648 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
649 * include space for the status word, byte count and control bytes in
650 * the allocation request.
651 */
652 numPages = (length + 6) >> 8;
653
654
655 SMC_SELECT_BANK(sc, 2);
656
657 /*
658 * The memory allocation completed. Check the results. If it failed,
659 * we simply set a watchdog timer and hope for the best.
660 */
661 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
662 if (packet_no & ARR_FAILED) {
663 if_printf(ifp, "Memory allocation failed. Weird.\n");
664 sc->timer = 1;
665 goto try_start;
666 }
667 /*
668 * We have a packet number, so tell the card to use it.
669 */
670 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
671
672 /*
673 * Now, numPages should match the pages_wanted recorded when the
674 * memory allocation was initiated.
675 */
676 if (pages_wanted != numPages) {
677 if_printf(ifp, "memory allocation wrong size. Weird.\n");
678 /*
679 * If the allocation was the wrong size we simply release the
680 * memory once it is granted. Wait for the MMU to be un-busy.
681 */
682 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
683 ;
684 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
685
686 return;
687 }
688 /*
689 * Point to the beginning of the packet
690 */
691 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
692
693 /*
694 * Send the packet length (+6 for status, length and control byte)
695 * and the status word (set to zeros)
696 */
697 CSR_WRITE_2(sc, DATA_REG_W, 0);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
699 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
700
701 /*
702 * Get the packet from the kernel. This will include the Ethernet
703 * frame header, MAC Addresses etc.
704 */
705 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
706
707 /*
708 * Push out the data to the card.
709 */
710 for (top = m; m != 0; m = m->m_next) {
711
712 /*
713 * Push out words.
714 */
715 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
716 m->m_len / 2);
717 /*
718 * Push out remaining byte.
719 */
720 if (m->m_len & 1)
721 CSR_WRITE_1(sc, DATA_REG_B,
722 *(mtod(m, caddr_t) + m->m_len - 1));
723 }
724
725 /*
726 * Push out padding.
727 */
728 while (pad > 1) {
729 CSR_WRITE_2(sc, DATA_REG_W, 0);
730 pad -= 2;
731 }
732 if (pad)
733 CSR_WRITE_1(sc, DATA_REG_B, 0);
734
735 /*
736 * Push out control byte and unused packet byte The control byte is 0
737 * meaning the packet is even lengthed and no special CRC handling is
738 * desired.
739 */
740 CSR_WRITE_2(sc, DATA_REG_W, 0);
741
742 /*
743 * Enable the interrupts and let the chipset deal with it Also set a
744 * watchdog in case we miss the interrupt.
745 */
746 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
747 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
748 sc->intr_mask = mask;
749 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
750
751 BPF_MTAP(ifp, top);
752
753 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
754 m_freem(top);
755
756 try_start:
757
758 /*
759 * Now pass control to snstart() to queue any additional packets
760 */
761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
762 snstart_locked(ifp);
763
764 /*
765 * We've sent something, so we're active. Set a watchdog in case the
766 * TX_EMPTY interrupt is lost.
767 */
768 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
769 sc->timer = 1;
770
771 return;
772 }
773
774 void
sn_intr(void * arg)775 sn_intr(void *arg)
776 {
777 struct sn_softc *sc = (struct sn_softc *) arg;
778
779 SN_LOCK(sc);
780 snintr_locked(sc);
781 SN_UNLOCK(sc);
782 }
783
784 static void
snintr_locked(struct sn_softc * sc)785 snintr_locked(struct sn_softc *sc)
786 {
787 int status, interrupts;
788 struct ifnet *ifp = sc->ifp;
789
790 /*
791 * Chip state registers
792 */
793 uint8_t mask;
794 uint8_t packet_no;
795 uint16_t tx_status;
796 uint16_t card_stats;
797
798 /*
799 * Clear the watchdog.
800 */
801 sc->timer = 0;
802
803 SMC_SELECT_BANK(sc, 2);
804
805 /*
806 * Obtain the current interrupt mask and clear the hardware mask
807 * while servicing interrupts.
808 */
809 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
810 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
811
812 /*
813 * Get the set of interrupts which occurred and eliminate any which
814 * are masked.
815 */
816 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
817 status = interrupts & mask;
818
819 /*
820 * Now, process each of the interrupt types.
821 */
822
823 /*
824 * Receive Overrun.
825 */
826 if (status & IM_RX_OVRN_INT) {
827 /*
828 * Acknowlege Interrupt
829 */
830 SMC_SELECT_BANK(sc, 2);
831 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
832
833 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
834 }
835 /*
836 * Got a packet.
837 */
838 if (status & IM_RCV_INT) {
839 int packet_number;
840
841 SMC_SELECT_BANK(sc, 2);
842 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
843
844 if (packet_number & FIFO_REMPTY) {
845 /*
846 * we got called , but nothing was on the FIFO
847 */
848 printf("sn: Receive interrupt with nothing on FIFO\n");
849 goto out;
850 }
851 snread(ifp);
852 }
853 /*
854 * An on-card memory allocation came through.
855 */
856 if (status & IM_ALLOC_INT) {
857 /*
858 * Disable this interrupt.
859 */
860 mask &= ~IM_ALLOC_INT;
861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
862 snresume(ifp);
863 }
864 /*
865 * TX Completion. Handle a transmit error message. This will only be
866 * called when there is an error, because of the AUTO_RELEASE mode.
867 */
868 if (status & IM_TX_INT) {
869 /*
870 * Acknowlege Interrupt
871 */
872 SMC_SELECT_BANK(sc, 2);
873 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
874
875 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
876 packet_no &= FIFO_TX_MASK;
877
878 /*
879 * select this as the packet to read from
880 */
881 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
882
883 /*
884 * Position the pointer to the first word from this packet
885 */
886 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
887
888 /*
889 * Fetch the TX status word. The value found here will be a
890 * copy of the EPH_STATUS_REG_W at the time the transmit
891 * failed.
892 */
893 tx_status = CSR_READ_2(sc, DATA_REG_W);
894
895 if (tx_status & EPHSR_TX_SUC) {
896 device_printf(sc->dev,
897 "Successful packet caused interrupt\n");
898 } else {
899 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
900 }
901
902 if (tx_status & EPHSR_LATCOL)
903 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
904
905 /*
906 * Some of these errors will have disabled transmit.
907 * Re-enable transmit now.
908 */
909 SMC_SELECT_BANK(sc, 0);
910
911 #ifdef SW_PAD
912 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
913 #else
914 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
915 #endif /* SW_PAD */
916
917 /*
918 * kill the failed packet. Wait for the MMU to be un-busy.
919 */
920 SMC_SELECT_BANK(sc, 2);
921 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
922 ;
923 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
924
925 /*
926 * Attempt to queue more transmits.
927 */
928 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
929 snstart_locked(ifp);
930 }
931 /*
932 * Transmit underrun. We use this opportunity to update transmit
933 * statistics from the card.
934 */
935 if (status & IM_TX_EMPTY_INT) {
936
937 /*
938 * Acknowlege Interrupt
939 */
940 SMC_SELECT_BANK(sc, 2);
941 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
942
943 /*
944 * Disable this interrupt.
945 */
946 mask &= ~IM_TX_EMPTY_INT;
947
948 SMC_SELECT_BANK(sc, 0);
949 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
950
951 /*
952 * Single collisions
953 */
954 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK);
955
956 /*
957 * Multiple collisions
958 */
959 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4);
960
961 SMC_SELECT_BANK(sc, 2);
962
963 /*
964 * Attempt to enqueue some more stuff.
965 */
966 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
967 snstart_locked(ifp);
968 }
969 /*
970 * Some other error. Try to fix it by resetting the adapter.
971 */
972 if (status & IM_EPH_INT) {
973 snstop(sc);
974 sninit_locked(sc);
975 }
976
977 out:
978 /*
979 * Handled all interrupt sources.
980 */
981
982 SMC_SELECT_BANK(sc, 2);
983
984 /*
985 * Reestablish interrupts from mask which have not been deselected
986 * during this interrupt. Note that the hardware mask, which was set
987 * to 0x00 at the start of this service routine, may have been
988 * updated by one or more of the interrupt handers and we must let
989 * those new interrupts stay enabled here.
990 */
991 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
992 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
993 sc->intr_mask = mask;
994 }
995
996 static void
snread(struct ifnet * ifp)997 snread(struct ifnet *ifp)
998 {
999 struct sn_softc *sc = ifp->if_softc;
1000 struct ether_header *eh;
1001 struct mbuf *m;
1002 short status;
1003 int packet_number;
1004 uint16_t packet_length;
1005 uint8_t *data;
1006
1007 SMC_SELECT_BANK(sc, 2);
1008 #if 0
1009 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1010
1011 if (packet_number & FIFO_REMPTY) {
1012
1013 /*
1014 * we got called , but nothing was on the FIFO
1015 */
1016 printf("sn: Receive interrupt with nothing on FIFO\n");
1017 return;
1018 }
1019 #endif
1020 read_another:
1021
1022 /*
1023 * Start reading from the start of the packet. Since PTR_RCV is set,
1024 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1025 */
1026 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1027
1028 /*
1029 * First two words are status and packet_length
1030 */
1031 status = CSR_READ_2(sc, DATA_REG_W);
1032 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1033
1034 /*
1035 * The packet length contains 3 extra words: status, length, and a
1036 * extra word with the control byte.
1037 */
1038 packet_length -= 6;
1039
1040 /*
1041 * Account for receive errors and discard.
1042 */
1043 if (status & RS_ERRORS) {
1044 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1045 goto out;
1046 }
1047 /*
1048 * A packet is received.
1049 */
1050
1051 /*
1052 * Adjust for odd-length packet.
1053 */
1054 if (status & RS_ODDFRAME)
1055 packet_length++;
1056
1057 /*
1058 * Allocate a header mbuf from the kernel.
1059 */
1060 MGETHDR(m, M_NOWAIT, MT_DATA);
1061 if (m == NULL)
1062 goto out;
1063
1064 m->m_pkthdr.rcvif = ifp;
1065 m->m_pkthdr.len = m->m_len = packet_length;
1066
1067 /*
1068 * Attach an mbuf cluster.
1069 */
1070 if (!(MCLGET(m, M_NOWAIT))) {
1071 m_freem(m);
1072 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1073 printf("sn: snread() kernel memory allocation problem\n");
1074 goto out;
1075 }
1076 eh = mtod(m, struct ether_header *);
1077
1078 /*
1079 * Get packet, including link layer address, from interface.
1080 */
1081 data = (uint8_t *) eh;
1082 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1083 if (packet_length & 1) {
1084 data += packet_length & ~1;
1085 *data = CSR_READ_1(sc, DATA_REG_B);
1086 }
1087 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1088
1089 /*
1090 * Remove link layer addresses and whatnot.
1091 */
1092 m->m_pkthdr.len = m->m_len = packet_length;
1093
1094 /*
1095 * Drop locks before calling if_input() since it may re-enter
1096 * snstart() in the netisr case. This would result in a
1097 * lock reversal. Better performance might be obtained by
1098 * chaining all packets received, dropping the lock, and then
1099 * calling if_input() on each one.
1100 */
1101 SN_UNLOCK(sc);
1102 (*ifp->if_input)(ifp, m);
1103 SN_LOCK(sc);
1104
1105 out:
1106
1107 /*
1108 * Error or good, tell the card to get rid of this packet Wait for
1109 * the MMU to be un-busy.
1110 */
1111 SMC_SELECT_BANK(sc, 2);
1112 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1113 ;
1114 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1115
1116 /*
1117 * Check whether another packet is ready
1118 */
1119 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1120 if (packet_number & FIFO_REMPTY) {
1121 return;
1122 }
1123 goto read_another;
1124 }
1125
1126
1127 /*
1128 * Handle IOCTLS. This function is completely stolen from if_ep.c
1129 * As with its progenitor, it does not handle hardware address
1130 * changes.
1131 */
1132 static int
snioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1133 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1134 {
1135 struct sn_softc *sc = ifp->if_softc;
1136 int error = 0;
1137
1138 switch (cmd) {
1139 case SIOCSIFFLAGS:
1140 SN_LOCK(sc);
1141 if ((ifp->if_flags & IFF_UP) == 0 &&
1142 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1143 snstop(sc);
1144 } else {
1145 /* reinitialize card on any parameter change */
1146 sninit_locked(sc);
1147 }
1148 SN_UNLOCK(sc);
1149 break;
1150
1151 case SIOCADDMULTI:
1152 case SIOCDELMULTI:
1153 /* update multicast filter list. */
1154 SN_LOCK(sc);
1155 sn_setmcast(sc);
1156 error = 0;
1157 SN_UNLOCK(sc);
1158 break;
1159 default:
1160 error = ether_ioctl(ifp, cmd, data);
1161 break;
1162 }
1163 return (error);
1164 }
1165
1166 static void
snwatchdog(void * arg)1167 snwatchdog(void *arg)
1168 {
1169 struct sn_softc *sc;
1170
1171 sc = arg;
1172 SN_ASSERT_LOCKED(sc);
1173 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1174 if (sc->timer == 0 || --sc->timer > 0)
1175 return;
1176 snintr_locked(sc);
1177 }
1178
1179
1180 /* 1. zero the interrupt mask
1181 * 2. clear the enable receive flag
1182 * 3. clear the enable xmit flags
1183 */
1184 static void
snstop(struct sn_softc * sc)1185 snstop(struct sn_softc *sc)
1186 {
1187
1188 struct ifnet *ifp = sc->ifp;
1189
1190 /*
1191 * Clear interrupt mask; disable all interrupts.
1192 */
1193 SMC_SELECT_BANK(sc, 2);
1194 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1195
1196 /*
1197 * Disable transmitter and Receiver
1198 */
1199 SMC_SELECT_BANK(sc, 0);
1200 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1201 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1202
1203 /*
1204 * Cancel watchdog.
1205 */
1206 sc->timer = 0;
1207 callout_stop(&sc->watchdog);
1208 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1209 }
1210
1211
1212 int
sn_activate(device_t dev)1213 sn_activate(device_t dev)
1214 {
1215 struct sn_softc *sc = device_get_softc(dev);
1216
1217 sc->port_rid = 0;
1218 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1219 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1220 if (!sc->port_res) {
1221 if (bootverbose)
1222 device_printf(dev, "Cannot allocate ioport\n");
1223 return ENOMEM;
1224 }
1225
1226 sc->irq_rid = 0;
1227 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1228 RF_ACTIVE);
1229 if (!sc->irq_res) {
1230 if (bootverbose)
1231 device_printf(dev, "Cannot allocate irq\n");
1232 sn_deactivate(dev);
1233 return ENOMEM;
1234 }
1235 return (0);
1236 }
1237
1238 void
sn_deactivate(device_t dev)1239 sn_deactivate(device_t dev)
1240 {
1241 struct sn_softc *sc = device_get_softc(dev);
1242
1243 if (sc->intrhand)
1244 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1245 sc->intrhand = 0;
1246 if (sc->port_res)
1247 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1248 sc->port_res);
1249 sc->port_res = 0;
1250 if (sc->modem_res)
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1252 sc->modem_res);
1253 sc->modem_res = 0;
1254 if (sc->irq_res)
1255 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1256 sc->irq_res);
1257 sc->irq_res = 0;
1258 return;
1259 }
1260
1261 /*
1262 * Function: sn_probe(device_t dev)
1263 *
1264 * Purpose:
1265 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1266 * Tries to cause as little damage as possible if it's not a SMC chip.
1267 * Returns a 0 on success
1268 *
1269 * Algorithm:
1270 * (1) see if the high byte of BANK_SELECT is 0x33
1271 * (2) compare the ioaddr with the base register's address
1272 * (3) see if I recognize the chip ID in the appropriate register
1273 *
1274 *
1275 */
1276 int
sn_probe(device_t dev)1277 sn_probe(device_t dev)
1278 {
1279 struct sn_softc *sc = device_get_softc(dev);
1280 uint16_t bank;
1281 uint16_t revision_register;
1282 uint16_t base_address_register;
1283 int err;
1284
1285 if ((err = sn_activate(dev)) != 0)
1286 return err;
1287
1288 /*
1289 * First, see if the high byte is 0x33
1290 */
1291 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1292 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1293 #ifdef SN_DEBUG
1294 device_printf(dev, "test1 failed\n");
1295 #endif
1296 goto error;
1297 }
1298 /*
1299 * The above MIGHT indicate a device, but I need to write to further
1300 * test this. Go to bank 0, then test that the register still
1301 * reports the high byte is 0x33.
1302 */
1303 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1304 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1305 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1306 #ifdef SN_DEBUG
1307 device_printf(dev, "test2 failed\n");
1308 #endif
1309 goto error;
1310 }
1311 /*
1312 * well, we've already written once, so hopefully another time won't
1313 * hurt. This time, I need to switch the bank register to bank 1, so
1314 * I can access the base address register. The contents of the
1315 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1316 * to match the I/O port address where the adapter is being probed.
1317 */
1318 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1319 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1320
1321 if (rman_get_start(sc->port_res) != base_address_register) {
1322
1323 /*
1324 * Well, the base address register didn't match. Must not
1325 * have been a SMC chip after all.
1326 */
1327 #ifdef SN_DEBUG
1328 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1329 "base_address_register = 0x%x\n",
1330 rman_get_start(sc->port_res), base_address_register);
1331 #endif
1332 goto error;
1333 }
1334
1335 /*
1336 * Check if the revision register is something that I recognize.
1337 * These might need to be added to later, as future revisions could
1338 * be added.
1339 */
1340 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1341 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1342 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1343
1344 /*
1345 * I don't regonize this chip, so...
1346 */
1347 #ifdef SN_DEBUG
1348 device_printf(dev, "test4 failed\n");
1349 #endif
1350 goto error;
1351 }
1352
1353 /*
1354 * at this point I'll assume that the chip is an SMC9xxx. It might be
1355 * prudent to check a listing of MAC addresses against the hardware
1356 * address, or do some other tests.
1357 */
1358 sn_deactivate(dev);
1359 return 0;
1360 error:
1361 sn_deactivate(dev);
1362 return ENXIO;
1363 }
1364
1365 #define MCFSZ 8
1366
1367 static void
sn_setmcast(struct sn_softc * sc)1368 sn_setmcast(struct sn_softc *sc)
1369 {
1370 struct ifnet *ifp = sc->ifp;
1371 int flags;
1372 uint8_t mcf[MCFSZ];
1373
1374 SN_ASSERT_LOCKED(sc);
1375
1376 /*
1377 * Set the receiver filter. We want receive enabled and auto strip
1378 * of CRC from received packet. If we are promiscuous then set that
1379 * bit too.
1380 */
1381 flags = RCR_ENABLE | RCR_STRIP_CRC;
1382
1383 if (ifp->if_flags & IFF_PROMISC) {
1384 flags |= RCR_PROMISC | RCR_ALMUL;
1385 } else if (ifp->if_flags & IFF_ALLMULTI) {
1386 flags |= RCR_ALMUL;
1387 } else {
1388 if (sn_getmcf(ifp, mcf)) {
1389 /* set filter */
1390 SMC_SELECT_BANK(sc, 3);
1391 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1392 ((uint16_t)mcf[1] << 8) | mcf[0]);
1393 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1394 ((uint16_t)mcf[3] << 8) | mcf[2]);
1395 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1396 ((uint16_t)mcf[5] << 8) | mcf[4]);
1397 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1398 ((uint16_t)mcf[7] << 8) | mcf[6]);
1399 } else {
1400 flags |= RCR_ALMUL;
1401 }
1402 }
1403 SMC_SELECT_BANK(sc, 0);
1404 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1405 }
1406
1407 static int
sn_getmcf(struct ifnet * ifp,uint8_t * mcf)1408 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1409 {
1410 int i;
1411 uint32_t index, index2;
1412 uint8_t *af = mcf;
1413 struct ifmultiaddr *ifma;
1414
1415 bzero(mcf, MCFSZ);
1416
1417 if_maddr_rlock(ifp);
1418 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1419 if (ifma->ifma_addr->sa_family != AF_LINK) {
1420 if_maddr_runlock(ifp);
1421 return 0;
1422 }
1423 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1424 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1425 index2 = 0;
1426 for (i = 0; i < 6; i++) {
1427 index2 <<= 1;
1428 index2 |= (index & 0x01);
1429 index >>= 1;
1430 }
1431 af[index2 >> 3] |= 1 << (index2 & 7);
1432 }
1433 if_maddr_runlock(ifp);
1434 return 1; /* use multicast filter */
1435 }
1436