1 /* $NetBSD: if_muereg.h,v 1.6 2019/08/15 08:02:32 mrg Exp $ */ 2 /* $OpenBSD: if_muereg.h,v 1.1 2018/08/03 01:50:15 kevlo Exp $ */ 3 4 /* 5 * Copyright (c) 2018 Kevin Lo <kevlo@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _IF_MUEREG_H_ 21 #define _IF_MUEREG_H_ 22 23 /* XXX for ETHER_HDR_LEN and ETHER_VLAN_ENCAP_LEN */ 24 #include <net/if_ether.h> 25 26 /* XXX for IP_MAXPACKET */ 27 #include <netinet/in.h> 28 #include <netinet/ip.h> 29 /* XXX for struct ip6_hdr */ 30 #include <netinet/ip6.h> 31 /* XXX for struct mue_txbuf_hdr */ 32 #include <dev/usb/if_muevar.h> 33 34 /* USB vendor requests */ 35 #define MUE_UR_WRITEREG 0xa0 36 #define MUE_UR_READREG 0xa1 37 38 /* registers */ 39 #define MUE_ID_REV 0x000 40 #define MUE_INT_STATUS 0x00c 41 #define MUE_HW_CFG 0x010 42 #define MUE_PMT_CTL 0x014 43 #define MUE_LED_CFG 0x018 44 #define MUE_DP_SEL 0x024 45 #define MUE_DP_CMD 0x028 46 #define MUE_DP_ADDR 0x02c 47 #define MUE_DP_DATA 0x030 48 #define MUE_7500_BURST_CAP 0x034 49 #define MUE_7500_INT_EP_CTL 0x038 50 #define MUE_7500_BULKIN_DELAY 0x03c 51 #define MUE_E2P_CMD 0x040 52 #define MUE_E2P_DATA 0x044 53 #define MUE_E2P_IND 0x0a5 54 #define MUE_7500_RFE_CTL 0x060 55 #define MUE_USB_CFG0 0x080 56 #define MUE_USB_CFG1 0x084 57 #define MUE_7500_FCT_RX_CTL 0x090 58 #define MUE_7800_BURST_CAP 0x090 59 #define MUE_7500_FCT_TX_CTL 0x094 60 #define MUE_7800_BULKIN_DELAY 0x094 61 #define MUE_7500_FCT_RX_FIFO_END 0x098 62 #define MUE_7800_INT_EP_CTL 0x098 63 #define MUE_7500_FCT_TX_FIFO_END 0x09c 64 #define MUE_7500_FCT_FLOW 0x0a0 65 #define MUE_7800_RFE_CTL 0x0b0 66 #define MUE_7800_FCT_RX_CTL 0x0c0 67 #define MUE_7800_FCT_TX_CTL 0x0c4 68 #define MUE_7800_FCT_RX_FIFO_END 0x0c8 69 #define MUE_7800_FCT_TX_FIFO_END 0x0cc 70 #define MUE_7800_FCT_FLOW 0x0d0 71 #define MUE_LTM_INDEX(idx) (0x0e0 + (idx) * 4) 72 #define MUE_NUM_LTM_INDEX 6 73 #define MUE_MAC_CR 0x100 74 #define MUE_MAC_RX 0x104 75 #define MUE_MAC_TX 0x108 76 #define MUE_FLOW 0x10c 77 #define MUE_RX_ADDRH 0x118 78 #define MUE_RX_ADDRL 0x11c 79 #define MUE_MII_ACCESS 0x120 80 #define MUE_MII_DATA 0x124 81 #define MUE_7500_ADDR_FILTX_BASE 0x300 82 #define MUE_7500_ADDR_FILTX(i) (MUE_7500_ADDR_FILTX_BASE + 8 * (i)) 83 #define MUE_7800_ADDR_FILTX_BASE 0x400 84 #define MUE_7800_ADDR_FILTX(i) (MUE_7800_ADDR_FILTX_BASE + 8 * (i)) 85 #define MUE_NUM_ADDR_FILTX 33 86 87 /* device ID and revision register */ 88 #define MUE_ID_REV_ID __BITS(16,31) 89 #define MUE_ID_REV_REV __BITS(0,15) 90 91 /* hardware configuration register */ 92 #define MUE_HW_CFG_SRST 0x00000001 93 #define MUE_HW_CFG_LRST 0x00000002 94 #define MUE_HW_CFG_BCE 0x00000004 95 #define MUE_HW_CFG_MEF 0x00000010 96 #define MUE_HW_CFG_BIR 0x00000080 97 #define MUE_HW_CFG_LED0_EN 0x00100000 98 #define MUE_HW_CFG_LED1_EN 0x00200000 99 100 /* power management control register */ 101 #define MUE_PMT_CTL_PHY_RST 0x00000010 102 #define MUE_PMT_CTL_READY 0x00000080 103 104 /* LED configuration register */ 105 #define MUE_LED_CFG_LEDGPIO_EN 0x0000f000 106 #define MUE_LED_CFG_LED10_FUN_SEL 0x40000000 107 #define MUE_LED_CFG_LED2_FUN_SEL 0x80000000 108 109 /* data port select register */ 110 #define MUE_DP_SEL_RSEL_MASK 0x0000000f 111 #define MUE_DP_SEL_VHF 0x00000001 112 #define MUE_DP_SEL_DPRDY 0x80000000 113 #define MUE_DP_SEL_VHF_HASH_LEN 16 114 #define MUE_DP_SEL_VHF_VLAN_LEN 128 115 116 /* data port command register */ 117 #define MUE_DP_CMD_WRITE 0x00000001 118 119 /* burst cap register and etc */ 120 #define MUE_SS_USB_PKT_SIZE 1024 121 #define MUE_HS_USB_PKT_SIZE 512 122 #define MUE_FS_USB_PKT_SIZE 64 123 #define MUE_7500_HS_RX_BUFSIZE \ 124 (16 * 1024 + 5 * MUE_HS_USB_PKT_SIZE) 125 #define MUE_7500_FS_RX_BUFSIZE \ 126 (6 * 1024 + 33 * MUE_FS_USB_PKT_SIZE) 127 #define MUE_7500_MAX_RX_FIFO_SIZE (20 * 1024) 128 #define MUE_7500_MAX_TX_FIFO_SIZE (12 * 1024) 129 #define MUE_7800_RX_BUFSIZE (12 * 1024) 130 #define MUE_7800_MAX_RX_FIFO_SIZE MUE_7800_RX_BUFSIZE 131 #define MUE_7800_MAX_TX_FIFO_SIZE MUE_7800_RX_BUFSIZE 132 #define MUE_FRAME_LEN(mtu) \ 133 (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 134 #define MUE_TSO_FRAME_LEN MUE_FRAME_LEN(IP_MAXPACKET) 135 #define MUE_TX_BUFSIZE \ 136 (sizeof(struct mue_txbuf_hdr) + MUE_TSO_FRAME_LEN) 137 138 /* interrupt endpoint control register */ 139 #define MUE_INT_EP_CTL_PHY_INT 0x20000 140 141 /* bulk-in delay register */ 142 #define MUE_7500_DEFAULT_BULKIN_DELAY 0x00002000 143 #define MUE_7800_DEFAULT_BULKIN_DELAY 0x00000800 144 145 /* EEPROM command register */ 146 #define MUE_E2P_CMD_ADDR_MASK 0x000001ff 147 #define MUE_E2P_CMD_READ 0x00000000 148 #define MUE_E2P_CMD_LOADED 0x00000200 149 #define MUE_E2P_CMD_TIMEOUT 0x00000400 150 #define MUE_E2P_CMD_BUSY 0x80000000 151 #define MUE_E2P_IND_OFFSET 0x000 152 #define MUE_E2P_MAC_OFFSET 0x001 153 #define MUE_E2P_LTM_OFFSET 0x03f 154 155 /* Receive Filtering Engine control register */ 156 #define MUE_RFE_CTL_PERFECT 0x00000002 157 #define MUE_RFE_CTL_MULTICAST_HASH 0x00000008 158 #define MUE_RFE_CTL_VLAN_FILTER 0x00000020 159 #define MUE_RFE_CTL_UNICAST 0x00000100 160 #define MUE_RFE_CTL_MULTICAST 0x00000200 161 #define MUE_RFE_CTL_BROADCAST 0x00000400 162 #define MUE_RFE_CTL_IP_COE 0x00000800 163 #define MUE_RFE_CTL_TCPUDP_COE 0x00001000 164 #define MUE_RFE_CTL_ICMP_COE 0x00002000 165 #define MUE_RFE_CTL_IGMP_COE 0x00004000 166 167 /* USB configuration register 0 */ 168 #define MUE_USB_CFG0_BCE 0x00000020 169 #define MUE_USB_CFG0_BIR 0x00000040 170 171 /* USB configuration register 1 */ 172 #define MUE_USB_CFG1_LTM_ENABLE 0x00000100 173 #define MUE_USB_CFG1_DEV_U1_INIT_EN 0x00000400 174 #define MUE_USB_CFG1_DEV_U2_INIT_EN 0x00001000 175 176 /* RX FIFO control register */ 177 #define MUE_FCT_RX_CTL_EN 0x80000000 178 179 /* TX FIFO control register */ 180 #define MUE_FCT_TX_CTL_EN 0x80000000 181 182 /* MAC control register */ 183 #define MUE_MAC_CR_RST 0x00000001 184 #define MUE_MAC_CR_FULL_DUPLEX 0x00000008 185 #define MUE_MAC_CR_AUTO_SPEED 0x00000800 186 #define MUE_MAC_CR_AUTO_DUPLEX 0x00001000 187 #define MUE_MAC_CR_GMII_EN 0x00080000 188 189 /* MAC receive register */ 190 #define MUE_MAC_RX_RXEN 0x00000001 191 #define MUE_MAC_RX_MAX_SIZE_MASK 0x3fff0000 192 #define MUE_MAC_RX_MAX_SIZE_SHIFT 16 193 #define MUE_MAC_RX_MAX_LEN(x) \ 194 (((x) << MUE_MAC_RX_MAX_SIZE_SHIFT) & MUE_MAC_RX_MAX_SIZE_MASK) 195 196 /* MAC transmit register */ 197 #define MUE_MAC_TX_TXEN 0x00000001 198 199 /* flow control register */ 200 #define MUE_FLOW_PAUSE_TIME 0x0000ffff 201 #define MUE_FLOW_RX_FCEN 0x20000000 202 #define MUE_FLOW_TX_FCEN 0x40000000 203 204 /* MII access register */ 205 #define MUE_MII_ACCESS_READ 0x00000000 206 #define MUE_MII_ACCESS_BUSY 0x00000001 207 #define MUE_MII_ACCESS_WRITE 0x00000002 208 #define MUE_MII_ACCESS_REGADDR_MASK 0x000007c0 209 #define MUE_MII_ACCESS_REGADDR_SHIFT 6 210 #define MUE_MII_ACCESS_PHYADDR_MASK 0x0000f800 211 #define MUE_MII_ACCESS_PHYADDR_SHIFT 11 212 #define MUE_MII_ACCESS_REGADDR(x) \ 213 (((x) << MUE_MII_ACCESS_REGADDR_SHIFT) & MUE_MII_ACCESS_REGADDR_MASK) 214 #define MUE_MII_ACCESS_PHYADDR(x) \ 215 (((x) << MUE_MII_ACCESS_PHYADDR_SHIFT) & MUE_MII_ACCESS_PHYADDR_MASK) 216 217 /* MAC address perfect filter register */ 218 #define MUE_ADDR_FILTX_VALID 0x80000000 219 220 /* undocumented OTP registers from Linux via FreeBSD */ 221 #define MUE_OTP_BASE_ADDR 0x01000 222 #define MUE_OTP_ADDR(off) (MUE_OTP_BASE_ADDR + 4 * (off)) 223 #define MUE_OTP_PWR_DN MUE_OTP_ADDR(0x00) 224 #define MUE_OTP_PWR_DN_PWRDN_N 0x01 225 #define MUE_OTP_ADDR1 MUE_OTP_ADDR(0x01) 226 #define MUE_OTP_ADDR1_MASK 0x1f 227 #define MUE_OTP_ADDR2 MUE_OTP_ADDR(0x02) 228 #define MUE_OTP_ADDR2_MASK 0xff 229 #define MUE_OTP_ADDR3 MUE_OTP_ADDR(0x03) 230 #define MUE_OTP_ADDR3_MASK 0x03 231 #define MUE_OTP_RD_DATA MUE_OTP_ADDR(0x06) 232 #define MUE_OTP_FUNC_CMD MUE_OTP_ADDR(0x08) 233 #define MUE_OTP_FUNC_CMD_RESET 0x04 234 #define MUE_OTP_FUNC_CMD_PROGRAM 0x02 235 #define MUE_OTP_FUNC_CMD_READ 0x01 236 #define MUE_OTP_MAC_OFFSET 0x01 237 #define MUE_OTP_IND_OFFSET 0x00 238 #define MUE_OTP_IND_1 0xf3 239 #define MUE_OTP_IND_2 0xf7 240 #define MUE_OTP_CMD_GO MUE_OTP_ADDR(0x0a) 241 #define MUE_OTP_CMD_GO_GO 0x01 242 #define MUE_OTP_STATUS MUE_OTP_ADDR(0x0a) 243 #define MUE_OTP_STATUS_OTP_LOCK 0x10 244 #define MUE_OTP_STATUS_BUSY 0x01 245 246 #endif /* _IF_MUEREG_H_ */ 247