1 /*-
2 * Copyright 2008 Nathan Whitehorn. All rights reserved.
3 * Copyright 2003 by Peter Grehan. All rights reserved.
4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * From:
30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp
31 */
32
33 /*
34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver
35 * The low-cost, low-feature Apple variant of the Sun HME
36 */
37
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/endian.h>
45 #include <sys/mbuf.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
50
51 #include <net/bpf.h>
52 #include <net/if.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58
59 #include <machine/pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <sys/bus.h>
63 #include <sys/rman.h>
64
65 #include <dev/mii/mii.h>
66 #include <dev/mii/mii_bitbang.h>
67 #include <dev/mii/miivar.h>
68
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/openfirm.h>
71 #include <machine/dbdma.h>
72
73 MODULE_DEPEND(bm, ether, 1, 1, 1);
74 MODULE_DEPEND(bm, miibus, 1, 1, 1);
75
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
78
79 #include "if_bmreg.h"
80 #include "if_bmvar.h"
81
82 static int bm_probe (device_t);
83 static int bm_attach (device_t);
84 static int bm_detach (device_t);
85 static int bm_shutdown (device_t);
86
87 static void bm_start (struct ifnet *);
88 static void bm_start_locked (struct ifnet *);
89 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head);
90 static int bm_ioctl (struct ifnet *, u_long, caddr_t);
91 static void bm_init (void *);
92 static void bm_init_locked (struct bm_softc *sc);
93 static void bm_chip_setup (struct bm_softc *sc);
94 static void bm_stop (struct bm_softc *sc);
95 static void bm_setladrf (struct bm_softc *sc);
96 static void bm_dummypacket (struct bm_softc *sc);
97 static void bm_txintr (void *xsc);
98 static void bm_rxintr (void *xsc);
99
100 static int bm_add_rxbuf (struct bm_softc *sc, int i);
101 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i);
102 static void bm_enable_interrupts (struct bm_softc *sc);
103 static void bm_disable_interrupts (struct bm_softc *sc);
104 static void bm_tick (void *xsc);
105
106 static int bm_ifmedia_upd (struct ifnet *);
107 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *);
108
109 static int bm_miibus_readreg (device_t, int, int);
110 static int bm_miibus_writereg (device_t, int, int, int);
111 static void bm_miibus_statchg (device_t);
112
113 /*
114 * MII bit-bang glue
115 */
116 static uint32_t bm_mii_bitbang_read(device_t);
117 static void bm_mii_bitbang_write(device_t, uint32_t);
118
119 static const struct mii_bitbang_ops bm_mii_bitbang_ops = {
120 bm_mii_bitbang_read,
121 bm_mii_bitbang_write,
122 {
123 BM_MII_DATAOUT, /* MII_BIT_MDO */
124 BM_MII_DATAIN, /* MII_BIT_MDI */
125 BM_MII_CLK, /* MII_BIT_MDC */
126 BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */
127 0, /* MII_BIT_DIR_PHY_HOST */
128 }
129 };
130
131 static device_method_t bm_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, bm_probe),
134 DEVMETHOD(device_attach, bm_attach),
135 DEVMETHOD(device_detach, bm_detach),
136 DEVMETHOD(device_shutdown, bm_shutdown),
137
138 /* MII interface */
139 DEVMETHOD(miibus_readreg, bm_miibus_readreg),
140 DEVMETHOD(miibus_writereg, bm_miibus_writereg),
141 DEVMETHOD(miibus_statchg, bm_miibus_statchg),
142
143 DEVMETHOD_END
144 };
145
146 static driver_t bm_macio_driver = {
147 "bm",
148 bm_methods,
149 sizeof(struct bm_softc)
150 };
151
152 static devclass_t bm_devclass;
153
154 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0);
155 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
156
157 /*
158 * MII internal routines
159 */
160
161 /*
162 * Write the MII serial port for the MII bit-bang module.
163 */
164 static void
bm_mii_bitbang_write(device_t dev,uint32_t val)165 bm_mii_bitbang_write(device_t dev, uint32_t val)
166 {
167 struct bm_softc *sc;
168
169 sc = device_get_softc(dev);
170
171 CSR_WRITE_2(sc, BM_MII_CSR, val);
172 CSR_BARRIER(sc, BM_MII_CSR, 2,
173 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
174 }
175
176 /*
177 * Read the MII serial port for the MII bit-bang module.
178 */
179 static uint32_t
bm_mii_bitbang_read(device_t dev)180 bm_mii_bitbang_read(device_t dev)
181 {
182 struct bm_softc *sc;
183 uint32_t reg;
184
185 sc = device_get_softc(dev);
186
187 reg = CSR_READ_2(sc, BM_MII_CSR);
188 CSR_BARRIER(sc, BM_MII_CSR, 2,
189 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
190
191 return (reg);
192 }
193
194 /*
195 * MII bus i/f
196 */
197 static int
bm_miibus_readreg(device_t dev,int phy,int reg)198 bm_miibus_readreg(device_t dev, int phy, int reg)
199 {
200
201 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg));
202 }
203
204 static int
bm_miibus_writereg(device_t dev,int phy,int reg,int data)205 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
206 {
207
208 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg);
209
210 return (0);
211 }
212
213 static void
bm_miibus_statchg(device_t dev)214 bm_miibus_statchg(device_t dev)
215 {
216 struct bm_softc *sc = device_get_softc(dev);
217 uint16_t reg;
218 int new_duplex;
219
220 reg = CSR_READ_2(sc, BM_TX_CONFIG);
221 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX;
222
223 if (new_duplex != sc->sc_duplex) {
224 /* Turn off TX MAC while we fiddle its settings */
225 reg &= ~BM_ENABLE;
226
227 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
228 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
229 DELAY(10);
230 }
231
232 if (new_duplex && !sc->sc_duplex)
233 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX;
234 else if (!new_duplex && sc->sc_duplex)
235 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX);
236
237 if (new_duplex != sc->sc_duplex) {
238 /* Turn TX MAC back on */
239 reg |= BM_ENABLE;
240
241 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
242 sc->sc_duplex = new_duplex;
243 }
244 }
245
246 /*
247 * ifmedia/mii callbacks
248 */
249 static int
bm_ifmedia_upd(struct ifnet * ifp)250 bm_ifmedia_upd(struct ifnet *ifp)
251 {
252 struct bm_softc *sc = ifp->if_softc;
253 int error;
254
255 BM_LOCK(sc);
256 error = mii_mediachg(sc->sc_mii);
257 BM_UNLOCK(sc);
258 return (error);
259 }
260
261 static void
bm_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifm)262 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm)
263 {
264 struct bm_softc *sc = ifp->if_softc;
265
266 BM_LOCK(sc);
267 mii_pollstat(sc->sc_mii);
268 ifm->ifm_active = sc->sc_mii->mii_media_active;
269 ifm->ifm_status = sc->sc_mii->mii_media_status;
270 BM_UNLOCK(sc);
271 }
272
273 /*
274 * Macio probe/attach
275 */
276 static int
bm_probe(device_t dev)277 bm_probe(device_t dev)
278 {
279 const char *dname = ofw_bus_get_name(dev);
280 const char *dcompat = ofw_bus_get_compat(dev);
281
282 /*
283 * BMAC+ cells have a name of "ethernet" and
284 * a compatible property of "bmac+"
285 */
286 if (strcmp(dname, "bmac") == 0) {
287 device_set_desc(dev, "Apple BMAC Ethernet Adaptor");
288 } else if (strcmp(dcompat, "bmac+") == 0) {
289 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor");
290 } else
291 return (ENXIO);
292
293 return (0);
294 }
295
296 static int
bm_attach(device_t dev)297 bm_attach(device_t dev)
298 {
299 phandle_t node;
300 u_char *eaddr;
301 struct ifnet *ifp;
302 int error, cellid, i;
303 struct bm_txsoft *txs;
304 struct bm_softc *sc = device_get_softc(dev);
305
306 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
307 ifp->if_softc = sc;
308 sc->sc_dev = dev;
309 sc->sc_duplex = ~IFM_FDX;
310
311 error = 0;
312 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
313 MTX_DEF);
314 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
315
316 /* Check for an improved version of Paddington */
317 sc->sc_streaming = 0;
318 cellid = -1;
319 node = ofw_bus_get_node(dev);
320
321 OF_getprop(node, "cell-id", &cellid, sizeof(cellid));
322 if (cellid >= 0xc4)
323 sc->sc_streaming = 1;
324
325 sc->sc_memrid = 0;
326 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
327 &sc->sc_memrid, RF_ACTIVE);
328 if (sc->sc_memr == NULL) {
329 device_printf(dev, "Could not alloc chip registers!\n");
330 return (ENXIO);
331 }
332
333 sc->sc_txdmarid = BM_TXDMA_REGISTERS;
334 sc->sc_rxdmarid = BM_RXDMA_REGISTERS;
335
336 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
337 &sc->sc_txdmarid, RF_ACTIVE);
338 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
339 &sc->sc_rxdmarid, RF_ACTIVE);
340
341 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) {
342 device_printf(dev, "Could not map DBDMA registers!\n");
343 return (ENXIO);
344 }
345
346 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev),
347 BM_MAX_DMA_COMMANDS, &sc->sc_txdma);
348 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev),
349 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma);
350
351 if (error) {
352 device_printf(dev,"Could not allocate DBDMA channel!\n");
353 return (ENXIO);
354 }
355
356 /* alloc DMA tags and buffers */
357 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
358 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
359 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
360 NULL, &sc->sc_pdma_tag);
361
362 if (error) {
363 device_printf(dev,"Could not allocate DMA tag!\n");
364 return (ENXIO);
365 }
366
367 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
368 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES,
369 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag);
370
371 if (error) {
372 device_printf(dev,"Could not allocate RX DMA channel!\n");
373 return (ENXIO);
374 }
375
376 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
377 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS,
378 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag);
379
380 if (error) {
381 device_printf(dev,"Could not allocate TX DMA tag!\n");
382 return (ENXIO);
383 }
384
385 /* init transmit descriptors */
386 STAILQ_INIT(&sc->sc_txfreeq);
387 STAILQ_INIT(&sc->sc_txdirtyq);
388
389 /* create TX DMA maps */
390 error = ENOMEM;
391 for (i = 0; i < BM_MAX_TX_PACKETS; i++) {
392 txs = &sc->sc_txsoft[i];
393 txs->txs_mbuf = NULL;
394 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap);
395 if (error) {
396 device_printf(sc->sc_dev,
397 "unable to create TX DMA map %d, error = %d\n",
398 i, error);
399 }
400 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
401 }
402
403 /* Create the receive buffer DMA maps. */
404 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
405 error = bus_dmamap_create(sc->sc_rdma_tag, 0,
406 &sc->sc_rxsoft[i].rxs_dmamap);
407 if (error) {
408 device_printf(sc->sc_dev,
409 "unable to create RX DMA map %d, error = %d\n",
410 i, error);
411 }
412 sc->sc_rxsoft[i].rxs_mbuf = NULL;
413 }
414
415 /* alloc interrupt */
416 bm_disable_interrupts(sc);
417
418 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT;
419 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
420 &sc->sc_txdmairqid, RF_ACTIVE);
421
422 if (error) {
423 device_printf(dev,"Could not allocate TX interrupt!\n");
424 return (ENXIO);
425 }
426
427 bus_setup_intr(dev,sc->sc_txdmairq,
428 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc,
429 &sc->sc_txihtx);
430
431 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT;
432 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
433 &sc->sc_rxdmairqid, RF_ACTIVE);
434
435 if (error) {
436 device_printf(dev,"Could not allocate RX interrupt!\n");
437 return (ENXIO);
438 }
439
440 bus_setup_intr(dev,sc->sc_rxdmairq,
441 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc,
442 &sc->sc_rxih);
443
444 /*
445 * Get the ethernet address from OpenFirmware
446 */
447 eaddr = sc->sc_enaddr;
448 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN);
449
450 /*
451 * Setup MII
452 * On Apple BMAC controllers, we end up in a weird state of
453 * partially-completed autonegotiation on boot. So we force
454 * autonegotation to try again.
455 */
456 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd,
457 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
458 MIIF_FORCEANEG);
459 if (error != 0) {
460 device_printf(dev, "attaching PHYs failed\n");
461 return (error);
462 }
463
464 /* reset the adapter */
465 bm_chip_setup(sc);
466
467 sc->sc_mii = device_get_softc(sc->sc_miibus);
468
469 if_initname(ifp, device_get_name(sc->sc_dev),
470 device_get_unit(sc->sc_dev));
471 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
472 ifp->if_start = bm_start;
473 ifp->if_ioctl = bm_ioctl;
474 ifp->if_init = bm_init;
475 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS);
476 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS;
477 IFQ_SET_READY(&ifp->if_snd);
478
479 /* Attach the interface. */
480 ether_ifattach(ifp, sc->sc_enaddr);
481 ifp->if_hwassist = 0;
482
483 return (0);
484 }
485
486 static int
bm_detach(device_t dev)487 bm_detach(device_t dev)
488 {
489 struct bm_softc *sc = device_get_softc(dev);
490
491 BM_LOCK(sc);
492 bm_stop(sc);
493 BM_UNLOCK(sc);
494
495 callout_drain(&sc->sc_tick_ch);
496 ether_ifdetach(sc->sc_ifp);
497 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx);
498 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih);
499
500 dbdma_free_channel(sc->sc_txdma);
501 dbdma_free_channel(sc->sc_rxdma);
502
503 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
504 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid,
505 sc->sc_txdmar);
506 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid,
507 sc->sc_rxdmar);
508
509 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid,
510 sc->sc_txdmairq);
511 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid,
512 sc->sc_rxdmairq);
513
514 mtx_destroy(&sc->sc_mtx);
515 if_free(sc->sc_ifp);
516
517 return (0);
518 }
519
520 static int
bm_shutdown(device_t dev)521 bm_shutdown(device_t dev)
522 {
523 struct bm_softc *sc;
524
525 sc = device_get_softc(dev);
526
527 BM_LOCK(sc);
528 bm_stop(sc);
529 BM_UNLOCK(sc);
530
531 return (0);
532 }
533
534 static void
bm_dummypacket(struct bm_softc * sc)535 bm_dummypacket(struct bm_softc *sc)
536 {
537 struct mbuf *m;
538 struct ifnet *ifp;
539
540 ifp = sc->sc_ifp;
541
542 MGETHDR(m, M_NOWAIT, MT_DATA);
543
544 if (m == NULL)
545 return;
546
547 bcopy(sc->sc_enaddr,
548 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
549 bcopy(sc->sc_enaddr,
550 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
551 mtod(m, struct ether_header *)->ether_type = htons(3);
552 mtod(m, unsigned char *)[14] = 0;
553 mtod(m, unsigned char *)[15] = 0;
554 mtod(m, unsigned char *)[16] = 0xE3;
555 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
556 IF_ENQUEUE(&ifp->if_snd, m);
557 bm_start_locked(ifp);
558 }
559
560 static void
bm_rxintr(void * xsc)561 bm_rxintr(void *xsc)
562 {
563 struct bm_softc *sc = xsc;
564 struct ifnet *ifp = sc->sc_ifp;
565 struct mbuf *m;
566 int i, prev_stop, new_stop;
567 uint16_t status;
568
569 BM_LOCK(sc);
570
571 status = dbdma_get_chan_status(sc->sc_rxdma);
572 if (status & DBDMA_STATUS_DEAD) {
573 dbdma_reset(sc->sc_rxdma);
574 BM_UNLOCK(sc);
575 return;
576 }
577 if (!(status & DBDMA_STATUS_RUN)) {
578 device_printf(sc->sc_dev,"Bad RX Interrupt!\n");
579 BM_UNLOCK(sc);
580 return;
581 }
582
583 prev_stop = sc->next_rxdma_slot - 1;
584 if (prev_stop < 0)
585 prev_stop = sc->rxdma_loop_slot - 1;
586
587 if (prev_stop < 0) {
588 BM_UNLOCK(sc);
589 return;
590 }
591
592 new_stop = -1;
593 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD);
594
595 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) {
596 if (i == sc->rxdma_loop_slot)
597 i = 0;
598
599 if (i == prev_stop)
600 break;
601
602 status = dbdma_get_cmd_status(sc->sc_rxdma, i);
603
604 if (status == 0)
605 break;
606
607 m = sc->sc_rxsoft[i].rxs_mbuf;
608
609 if (bm_add_rxbuf(sc, i)) {
610 ifp->if_ierrors++;
611 m = NULL;
612 continue;
613 }
614
615 if (m == NULL)
616 continue;
617
618 ifp->if_ipackets++;
619 m->m_pkthdr.rcvif = ifp;
620 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2);
621 m->m_pkthdr.len = m->m_len;
622
623 /* Send up the stack */
624 BM_UNLOCK(sc);
625 (*ifp->if_input)(ifp, m);
626 BM_LOCK(sc);
627
628 /* Clear all fields on this command */
629 bm_add_rxbuf_dma(sc, i);
630
631 new_stop = i;
632 }
633
634 /* Change the last packet we processed to the ring buffer terminator,
635 * and restore a receive buffer to the old terminator */
636 if (new_stop >= 0) {
637 dbdma_insert_stop(sc->sc_rxdma, new_stop);
638 bm_add_rxbuf_dma(sc, prev_stop);
639 if (i < sc->rxdma_loop_slot)
640 sc->next_rxdma_slot = i;
641 else
642 sc->next_rxdma_slot = 0;
643 }
644 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
645
646 dbdma_wake(sc->sc_rxdma);
647
648 BM_UNLOCK(sc);
649 }
650
651 static void
bm_txintr(void * xsc)652 bm_txintr(void *xsc)
653 {
654 struct bm_softc *sc = xsc;
655 struct ifnet *ifp = sc->sc_ifp;
656 struct bm_txsoft *txs;
657 int progress = 0;
658
659 BM_LOCK(sc);
660
661 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
662 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc))
663 break;
664
665 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
666 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
667
668 if (txs->txs_mbuf != NULL) {
669 m_freem(txs->txs_mbuf);
670 txs->txs_mbuf = NULL;
671 }
672
673 /* Set the first used TXDMA slot to the location of the
674 * STOP/NOP command associated with this packet. */
675
676 sc->first_used_txdma_slot = txs->txs_stopdesc;
677
678 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
679
680 ifp->if_opackets++;
681 progress = 1;
682 }
683
684 if (progress) {
685 /*
686 * We freed some descriptors, so reset IFF_DRV_OACTIVE
687 * and restart.
688 */
689 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
690 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
691
692 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
693 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
694 bm_start_locked(ifp);
695 }
696
697 BM_UNLOCK(sc);
698 }
699
700 static void
bm_start(struct ifnet * ifp)701 bm_start(struct ifnet *ifp)
702 {
703 struct bm_softc *sc = ifp->if_softc;
704
705 BM_LOCK(sc);
706 bm_start_locked(ifp);
707 BM_UNLOCK(sc);
708 }
709
710 static void
bm_start_locked(struct ifnet * ifp)711 bm_start_locked(struct ifnet *ifp)
712 {
713 struct bm_softc *sc = ifp->if_softc;
714 struct mbuf *mb_head;
715 int prev_stop;
716 int txqueued = 0;
717
718 /*
719 * We lay out our DBDMA program in the following manner:
720 * OUTPUT_MORE
721 * ...
722 * OUTPUT_LAST (+ Interrupt)
723 * STOP
724 *
725 * To extend the channel, we append a new program,
726 * then replace STOP with NOP and wake the channel.
727 * If we stalled on the STOP already, the program proceeds,
728 * if not it will sail through the NOP.
729 */
730
731 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
732 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
733
734 if (mb_head == NULL)
735 break;
736
737 prev_stop = sc->next_txdma_slot - 1;
738
739 if (bm_encap(sc, &mb_head)) {
740 /* Put the packet back and stop */
741 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
742 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
743 break;
744 }
745
746 dbdma_insert_nop(sc->sc_txdma, prev_stop);
747
748 txqueued = 1;
749
750 BPF_MTAP(ifp, mb_head);
751 }
752
753 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
754
755 if (txqueued) {
756 dbdma_wake(sc->sc_txdma);
757 sc->sc_wdog_timer = 5;
758 }
759 }
760
761 static int
bm_encap(struct bm_softc * sc,struct mbuf ** m_head)762 bm_encap(struct bm_softc *sc, struct mbuf **m_head)
763 {
764 bus_dma_segment_t segs[BM_NTXSEGS];
765 struct bm_txsoft *txs;
766 struct mbuf *m;
767 int nsegs = BM_NTXSEGS;
768 int error = 0;
769 uint8_t branch_type;
770 int i;
771
772 /* Limit the command size to the number of free DBDMA slots */
773
774 if (sc->next_txdma_slot >= sc->first_used_txdma_slot)
775 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot +
776 sc->first_used_txdma_slot; /* -2 for branch and indexing */
777 else
778 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot;
779
780 /* Remove one slot for the STOP/NOP terminator */
781 nsegs--;
782
783 if (nsegs > BM_NTXSEGS)
784 nsegs = BM_NTXSEGS;
785
786 /* Get a work queue entry. */
787 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
788 /* Ran out of descriptors. */
789 return (ENOBUFS);
790 }
791
792 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap,
793 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
794
795 if (error == EFBIG) {
796 m = m_collapse(*m_head, M_NOWAIT, nsegs);
797 if (m == NULL) {
798 m_freem(*m_head);
799 *m_head = NULL;
800 return (ENOBUFS);
801 }
802 *m_head = m;
803
804 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag,
805 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
806 if (error != 0) {
807 m_freem(*m_head);
808 *m_head = NULL;
809 return (error);
810 }
811 } else if (error != 0)
812 return (error);
813
814 if (nsegs == 0) {
815 m_freem(*m_head);
816 *m_head = NULL;
817 return (EIO);
818 }
819
820 txs->txs_ndescs = nsegs;
821 txs->txs_firstdesc = sc->next_txdma_slot;
822
823 for (i = 0; i < nsegs; i++) {
824 /* Loop back to the beginning if this is our last slot */
825 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1))
826 branch_type = DBDMA_ALWAYS;
827 else
828 branch_type = DBDMA_NEVER;
829
830 if (i+1 == nsegs)
831 txs->txs_lastdesc = sc->next_txdma_slot;
832
833 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++,
834 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST,
835 0, segs[i].ds_addr, segs[i].ds_len,
836 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS,
837 branch_type, DBDMA_NEVER, 0);
838
839 if (branch_type == DBDMA_ALWAYS)
840 sc->next_txdma_slot = 0;
841 }
842
843 /* We have a corner case where the STOP command is the last slot,
844 * but you can't branch in STOP commands. So add a NOP branch here
845 * and the STOP in slot 0. */
846
847 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) {
848 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0);
849 sc->next_txdma_slot = 0;
850 }
851
852 txs->txs_stopdesc = sc->next_txdma_slot;
853 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++);
854
855 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
856 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
857 txs->txs_mbuf = *m_head;
858
859 return (0);
860 }
861
862 static int
bm_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)863 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
864 {
865 struct bm_softc *sc = ifp->if_softc;
866 struct ifreq *ifr = (struct ifreq *)data;
867 int error;
868
869 error = 0;
870
871 switch(cmd) {
872 case SIOCSIFFLAGS:
873 BM_LOCK(sc);
874 if ((ifp->if_flags & IFF_UP) != 0) {
875 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
876 ((ifp->if_flags ^ sc->sc_ifpflags) &
877 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
878 bm_setladrf(sc);
879 else
880 bm_init_locked(sc);
881 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
882 bm_stop(sc);
883 sc->sc_ifpflags = ifp->if_flags;
884 BM_UNLOCK(sc);
885 break;
886 case SIOCADDMULTI:
887 case SIOCDELMULTI:
888 BM_LOCK(sc);
889 bm_setladrf(sc);
890 BM_UNLOCK(sc);
891 case SIOCGIFMEDIA:
892 case SIOCSIFMEDIA:
893 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
894 break;
895 default:
896 error = ether_ioctl(ifp, cmd, data);
897 break;
898 }
899
900 return (error);
901 }
902
903 static void
bm_setladrf(struct bm_softc * sc)904 bm_setladrf(struct bm_softc *sc)
905 {
906 struct ifnet *ifp = sc->sc_ifp;
907 struct ifmultiaddr *inm;
908 uint16_t hash[4];
909 uint16_t reg;
910 uint32_t crc;
911
912 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS;
913
914 /* Turn off RX MAC while we fiddle its settings */
915 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
916 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
917 DELAY(10);
918
919 if ((ifp->if_flags & IFF_PROMISC) != 0) {
920 reg |= BM_PROMISC;
921
922 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
923
924 DELAY(15);
925
926 reg = CSR_READ_2(sc, BM_RX_CONFIG);
927 reg |= BM_ENABLE;
928 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
929 return;
930 }
931
932 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
933 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
934 } else {
935 /* Clear the hash table. */
936 memset(hash, 0, sizeof(hash));
937
938 if_maddr_rlock(ifp);
939 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
940 if (inm->ifma_addr->sa_family != AF_LINK)
941 continue;
942 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
943 inm->ifma_addr), ETHER_ADDR_LEN);
944
945 /* We just want the 6 most significant bits */
946 crc >>= 26;
947
948 /* Set the corresponding bit in the filter. */
949 hash[crc >> 4] |= 1 << (crc & 0xf);
950 }
951 if_maddr_runlock(ifp);
952 }
953
954 /* Write out new hash table */
955 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
956 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
957 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
958 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);
959
960 /* And turn the RX MAC back on, this time with the hash bit set */
961 reg |= BM_HASH_FILTER_ENABLE;
962 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
963
964 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
965 DELAY(10);
966
967 reg = CSR_READ_2(sc, BM_RX_CONFIG);
968 reg |= BM_ENABLE;
969 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
970 }
971
972 static void
bm_init(void * xsc)973 bm_init(void *xsc)
974 {
975 struct bm_softc *sc = xsc;
976
977 BM_LOCK(sc);
978 bm_init_locked(sc);
979 BM_UNLOCK(sc);
980 }
981
982 static void
bm_chip_setup(struct bm_softc * sc)983 bm_chip_setup(struct bm_softc *sc)
984 {
985 uint16_t reg;
986 uint16_t *eaddr_sect;
987
988 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
989 dbdma_stop(sc->sc_txdma);
990 dbdma_stop(sc->sc_rxdma);
991
992 /* Reset chip */
993 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);
994 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);
995 do {
996 DELAY(10);
997 reg = CSR_READ_2(sc, BM_TX_RESET);
998 } while (reg & 0x0001);
999
1000 /* Some random junk. OS X uses the system time. We use
1001 * the low 16 bits of the MAC address. */
1002 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]);
1003
1004 /* Enable transmit */
1005 reg = CSR_READ_2(sc, BM_TX_IFC);
1006 reg |= BM_ENABLE;
1007 CSR_WRITE_2(sc, BM_TX_IFC, reg);
1008
1009 CSR_READ_2(sc, BM_TX_PEAKCNT);
1010 }
1011
1012 static void
bm_stop(struct bm_softc * sc)1013 bm_stop(struct bm_softc *sc)
1014 {
1015 struct bm_txsoft *txs;
1016 uint16_t reg;
1017
1018 /* Disable TX and RX MACs */
1019 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1020 reg &= ~BM_ENABLE;
1021 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1022
1023 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1024 reg &= ~BM_ENABLE;
1025 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1026
1027 DELAY(100);
1028
1029 /* Stop DMA engine */
1030 dbdma_stop(sc->sc_rxdma);
1031 dbdma_stop(sc->sc_txdma);
1032 sc->next_rxdma_slot = 0;
1033 sc->rxdma_loop_slot = 0;
1034
1035 /* Disable interrupts */
1036 bm_disable_interrupts(sc);
1037
1038 /* Don't worry about pending transmits anymore */
1039 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1040 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1041 if (txs->txs_ndescs != 0) {
1042 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap,
1043 BUS_DMASYNC_POSTWRITE);
1044 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
1045 if (txs->txs_mbuf != NULL) {
1046 m_freem(txs->txs_mbuf);
1047 txs->txs_mbuf = NULL;
1048 }
1049 }
1050 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1051 }
1052
1053 /* And we're down */
1054 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1055 sc->sc_wdog_timer = 0;
1056 callout_stop(&sc->sc_tick_ch);
1057 }
1058
1059 static void
bm_init_locked(struct bm_softc * sc)1060 bm_init_locked(struct bm_softc *sc)
1061 {
1062 uint16_t reg;
1063 uint16_t *eaddr_sect;
1064 struct bm_rxsoft *rxs;
1065 int i;
1066
1067 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1068
1069 /* Zero RX slot info and stop DMA */
1070 dbdma_stop(sc->sc_rxdma);
1071 dbdma_stop(sc->sc_txdma);
1072 sc->next_rxdma_slot = 0;
1073 sc->rxdma_loop_slot = 0;
1074
1075 /* Initialize TX/RX DBDMA programs */
1076 dbdma_insert_stop(sc->sc_rxdma, 0);
1077 dbdma_insert_stop(sc->sc_txdma, 0);
1078 dbdma_set_current_cmd(sc->sc_rxdma, 0);
1079 dbdma_set_current_cmd(sc->sc_txdma, 0);
1080
1081 sc->next_rxdma_slot = 0;
1082 sc->next_txdma_slot = 1;
1083 sc->first_used_txdma_slot = 0;
1084
1085 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
1086 rxs = &sc->sc_rxsoft[i];
1087 rxs->dbdma_slot = i;
1088
1089 if (rxs->rxs_mbuf == NULL) {
1090 bm_add_rxbuf(sc, i);
1091
1092 if (rxs->rxs_mbuf == NULL) {
1093 /* If we can't add anymore, mark the problem */
1094 rxs->dbdma_slot = -1;
1095 break;
1096 }
1097 }
1098
1099 if (i > 0)
1100 bm_add_rxbuf_dma(sc, i);
1101 }
1102
1103 /*
1104 * Now terminate the RX ring buffer, and follow with the loop to
1105 * the beginning.
1106 */
1107 dbdma_insert_stop(sc->sc_rxdma, i - 1);
1108 dbdma_insert_branch(sc->sc_rxdma, i, 0);
1109 sc->rxdma_loop_slot = i;
1110
1111 /* Now add in the first element of the RX DMA chain */
1112 bm_add_rxbuf_dma(sc, 0);
1113
1114 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
1115 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
1116
1117 /* Zero collision counters */
1118 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1119 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1120 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1121 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1122
1123 /* Zero receive counters */
1124 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1125 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1126 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1127 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1128 CSR_WRITE_2(sc, BM_RXCV, 0);
1129
1130 /* Prime transmit */
1131 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);
1132
1133 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);
1134 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);
1135
1136 /* Prime receive */
1137 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);
1138 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);
1139
1140 /* Clear status reg */
1141 CSR_READ_2(sc, BM_STATUS);
1142
1143 /* Zero hash filters */
1144 CSR_WRITE_2(sc, BM_HASHTAB0, 0);
1145 CSR_WRITE_2(sc, BM_HASHTAB1, 0);
1146 CSR_WRITE_2(sc, BM_HASHTAB2, 0);
1147 CSR_WRITE_2(sc, BM_HASHTAB3, 0);
1148
1149 /* Write MAC address to chip */
1150 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);
1151 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);
1152 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);
1153
1154 /* Final receive engine setup */
1155 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE;
1156 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1157
1158 /* Now turn it all on! */
1159 dbdma_reset(sc->sc_rxdma);
1160 dbdma_reset(sc->sc_txdma);
1161
1162 /* Enable RX and TX MACs. Setting the address filter has
1163 * the side effect of enabling the RX MAC. */
1164 bm_setladrf(sc);
1165
1166 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1167 reg |= BM_ENABLE;
1168 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1169
1170 /*
1171 * Enable interrupts, unwedge the controller with a dummy packet,
1172 * and nudge the DMA queue.
1173 */
1174 bm_enable_interrupts(sc);
1175 bm_dummypacket(sc);
1176 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */
1177
1178 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
1179 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1180 sc->sc_ifpflags = sc->sc_ifp->if_flags;
1181
1182 /* Resync PHY and MAC states */
1183 sc->sc_mii = device_get_softc(sc->sc_miibus);
1184 sc->sc_duplex = ~IFM_FDX;
1185 mii_mediachg(sc->sc_mii);
1186
1187 /* Start the one second timer. */
1188 sc->sc_wdog_timer = 0;
1189 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1190 }
1191
1192 static void
bm_tick(void * arg)1193 bm_tick(void *arg)
1194 {
1195 struct bm_softc *sc = arg;
1196
1197 /* Read error counters */
1198 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) +
1199 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) +
1200 CSR_READ_2(sc, BM_TX_LTCNT);
1201
1202 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) +
1203 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT);
1204
1205 /* Zero collision counters */
1206 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1207 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1208 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1209 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1210
1211 /* Zero receive counters */
1212 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1213 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1214 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1215 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1216 CSR_WRITE_2(sc, BM_RXCV, 0);
1217
1218 /* Check for link changes and run watchdog */
1219 mii_tick(sc->sc_mii);
1220 bm_miibus_statchg(sc->sc_dev);
1221
1222 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
1223 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1224 return;
1225 }
1226
1227 /* Problems */
1228 device_printf(sc->sc_dev, "device timeout\n");
1229
1230 bm_init_locked(sc);
1231 }
1232
1233 static int
bm_add_rxbuf(struct bm_softc * sc,int idx)1234 bm_add_rxbuf(struct bm_softc *sc, int idx)
1235 {
1236 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1237 struct mbuf *m;
1238 bus_dma_segment_t segs[1];
1239 int error, nsegs;
1240
1241 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1242 if (m == NULL)
1243 return (ENOBUFS);
1244 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1245
1246 if (rxs->rxs_mbuf != NULL) {
1247 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap,
1248 BUS_DMASYNC_POSTREAD);
1249 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap);
1250 }
1251
1252 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m,
1253 segs, &nsegs, BUS_DMA_NOWAIT);
1254 if (error != 0) {
1255 device_printf(sc->sc_dev,
1256 "cannot load RS DMA map %d, error = %d\n", idx, error);
1257 m_freem(m);
1258 return (error);
1259 }
1260 /* If nsegs is wrong then the stack is corrupt. */
1261 KASSERT(nsegs == 1,
1262 ("%s: too many DMA segments (%d)", __func__, nsegs));
1263 rxs->rxs_mbuf = m;
1264 rxs->segment = segs[0];
1265
1266 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1267
1268 return (0);
1269 }
1270
1271 static int
bm_add_rxbuf_dma(struct bm_softc * sc,int idx)1272 bm_add_rxbuf_dma(struct bm_softc *sc, int idx)
1273 {
1274 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1275
1276 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0,
1277 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS,
1278 DBDMA_NEVER, DBDMA_NEVER, 0);
1279
1280 return (0);
1281 }
1282
1283 static void
bm_enable_interrupts(struct bm_softc * sc)1284 bm_enable_interrupts(struct bm_softc *sc)
1285 {
1286 CSR_WRITE_2(sc, BM_INTR_DISABLE,
1287 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL);
1288 }
1289
1290 static void
bm_disable_interrupts(struct bm_softc * sc)1291 bm_disable_interrupts(struct bm_softc *sc)
1292 {
1293 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);
1294 }
1295