1 /*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 /*
38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
84
85 #include <net/if.h>
86 #include <net/if_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
91
92 #include <net/bpf.h>
93
94 #include <net/if_types.h>
95 #include <net/if_vlan_var.h>
96
97 #include <netinet/in_systm.h>
98 #include <netinet/in.h>
99 #include <netinet/ip.h>
100 #include <netinet/tcp.h>
101
102 #include <machine/bus.h>
103 #include <machine/resource.h>
104 #include <sys/bus.h>
105 #include <sys/rman.h>
106
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109 #include "miidevs.h"
110 #include <dev/mii/brgphyreg.h>
111
112 #ifdef __sparc64__
113 #include <dev/ofw/ofw_bus.h>
114 #include <dev/ofw/openfirm.h>
115 #include <machine/ofw_machdep.h>
116 #include <machine/ver.h>
117 #endif
118
119 #include <dev/pci/pcireg.h>
120 #include <dev/pci/pcivar.h>
121
122 #include <dev/bge/if_bgereg.h>
123
124 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126
127 MODULE_DEPEND(bge, pci, 1, 1, 1);
128 MODULE_DEPEND(bge, ether, 1, 1, 1);
129 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130
131 /* "device miibus" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
133
134 /*
135 * Various supported device vendors/types and their names. Note: the
136 * spec seems to indicate that the hardware still has Alteon's vendor
137 * ID burned into it, though it will always be overriden by the vendor
138 * ID in the EEPROM. Just to be safe, we cover all possibilities.
139 */
140 static const struct bge_type {
141 uint16_t bge_vid;
142 uint16_t bge_did;
143 } bge_devs[] = {
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
145 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
146
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
149 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
150
151 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
152
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
238
239 { SK_VENDORID, SK_DEVICEID_ALTIMA },
240
241 { TC_VENDORID, TC_DEVICEID_3C996 },
242
243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
244 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
245 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
246
247 { 0, 0 }
248 };
249
250 static const struct bge_vendor {
251 uint16_t v_id;
252 const char *v_name;
253 } bge_vendors[] = {
254 { ALTEON_VENDORID, "Alteon" },
255 { ALTIMA_VENDORID, "Altima" },
256 { APPLE_VENDORID, "Apple" },
257 { BCOM_VENDORID, "Broadcom" },
258 { SK_VENDORID, "SysKonnect" },
259 { TC_VENDORID, "3Com" },
260 { FJTSU_VENDORID, "Fujitsu" },
261
262 { 0, NULL }
263 };
264
265 static const struct bge_revision {
266 uint32_t br_chipid;
267 const char *br_name;
268 } bge_revisions[] = {
269 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
270 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
271 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
272 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
273 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
274 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
275 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
276 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
277 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
278 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
279 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
280 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
281 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
282 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
283 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
284 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
285 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
286 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
287 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
288 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
289 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
290 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
291 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
292 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
293 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
294 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
295 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
296 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
297 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
298 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
299 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
300 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
301 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
302 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
303 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
304 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
305 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
306 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
307 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
308 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
309 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
310 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
311 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
312 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
313 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
314 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
315 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
316 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
317 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
318 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
319 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
320 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
321 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
322 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
323 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
324 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
325 /* 5754 and 5787 share the same ASIC ID */
326 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
327 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
328 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
329 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
330 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
331 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
332 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
333 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
334 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
335
336 { 0, NULL }
337 };
338
339 /*
340 * Some defaults for major revisions, so that newer steppings
341 * that we don't know about have a shot at working.
342 */
343 static const struct bge_revision bge_majorrevs[] = {
344 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
345 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
346 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
347 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
348 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
349 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
350 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
351 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
352 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
353 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
354 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
355 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
356 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
357 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
358 /* 5754 and 5787 share the same ASIC ID */
359 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
360 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
361 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
362 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
363 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
364 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
365 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
366 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
367 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
368
369 { 0, NULL }
370 };
371
372 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
373 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
374 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
375 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
376 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
377 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
378 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
379 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
380
381 static uint32_t bge_chipid(device_t);
382 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
383 static const struct bge_revision * bge_lookup_rev(uint32_t);
384
385 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
386
387 static int bge_probe(device_t);
388 static int bge_attach(device_t);
389 static int bge_detach(device_t);
390 static int bge_suspend(device_t);
391 static int bge_resume(device_t);
392 static void bge_release_resources(struct bge_softc *);
393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
394 static int bge_dma_alloc(struct bge_softc *);
395 static void bge_dma_free(struct bge_softc *);
396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
397 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
398
399 static void bge_devinfo(struct bge_softc *);
400 static int bge_mbox_reorder(struct bge_softc *);
401
402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
407
408 static void bge_txeof(struct bge_softc *, uint16_t);
409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
410 static int bge_rxeof(struct bge_softc *, uint16_t, int);
411
412 static void bge_asf_driver_up (struct bge_softc *);
413 static void bge_tick(void *);
414 static void bge_stats_clear_regs(struct bge_softc *);
415 static void bge_stats_update(struct bge_softc *);
416 static void bge_stats_update_regs(struct bge_softc *);
417 static struct mbuf *bge_check_short_dma(struct mbuf *);
418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
419 uint16_t *, uint16_t *);
420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
421
422 static void bge_intr(void *);
423 static int bge_msi_intr(void *);
424 static void bge_intr_task(void *, int);
425 static void bge_start_locked(if_t);
426 static void bge_start(if_t);
427 static int bge_ioctl(if_t, u_long, caddr_t);
428 static void bge_init_locked(struct bge_softc *);
429 static void bge_init(void *);
430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
431 static void bge_stop(struct bge_softc *);
432 static void bge_watchdog(struct bge_softc *);
433 static int bge_shutdown(device_t);
434 static int bge_ifmedia_upd_locked(if_t);
435 static int bge_ifmedia_upd(if_t);
436 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
437 static uint64_t bge_get_counter(if_t, ift_counter);
438
439 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
440 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
441
442 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
443 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
444
445 static void bge_setpromisc(struct bge_softc *);
446 static void bge_setmulti(struct bge_softc *);
447 static void bge_setvlan(struct bge_softc *);
448
449 static __inline void bge_rxreuse_std(struct bge_softc *, int);
450 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
451 static int bge_newbuf_std(struct bge_softc *, int);
452 static int bge_newbuf_jumbo(struct bge_softc *, int);
453 static int bge_init_rx_ring_std(struct bge_softc *);
454 static void bge_free_rx_ring_std(struct bge_softc *);
455 static int bge_init_rx_ring_jumbo(struct bge_softc *);
456 static void bge_free_rx_ring_jumbo(struct bge_softc *);
457 static void bge_free_tx_ring(struct bge_softc *);
458 static int bge_init_tx_ring(struct bge_softc *);
459
460 static int bge_chipinit(struct bge_softc *);
461 static int bge_blockinit(struct bge_softc *);
462 static uint32_t bge_dma_swap_options(struct bge_softc *);
463
464 static int bge_has_eaddr(struct bge_softc *);
465 static uint32_t bge_readmem_ind(struct bge_softc *, int);
466 static void bge_writemem_ind(struct bge_softc *, int, int);
467 static void bge_writembx(struct bge_softc *, int, int);
468 #ifdef notdef
469 static uint32_t bge_readreg_ind(struct bge_softc *, int);
470 #endif
471 static void bge_writemem_direct(struct bge_softc *, int, int);
472 static void bge_writereg_ind(struct bge_softc *, int, int);
473
474 static int bge_miibus_readreg(device_t, int, int);
475 static int bge_miibus_writereg(device_t, int, int, int);
476 static void bge_miibus_statchg(device_t);
477 #ifdef DEVICE_POLLING
478 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
479 #endif
480
481 #define BGE_RESET_SHUTDOWN 0
482 #define BGE_RESET_START 1
483 #define BGE_RESET_SUSPEND 2
484 static void bge_sig_post_reset(struct bge_softc *, int);
485 static void bge_sig_legacy(struct bge_softc *, int);
486 static void bge_sig_pre_reset(struct bge_softc *, int);
487 static void bge_stop_fw(struct bge_softc *);
488 static int bge_reset(struct bge_softc *);
489 static void bge_link_upd(struct bge_softc *);
490
491 static void bge_ape_lock_init(struct bge_softc *);
492 static void bge_ape_read_fw_ver(struct bge_softc *);
493 static int bge_ape_lock(struct bge_softc *, int);
494 static void bge_ape_unlock(struct bge_softc *, int);
495 static void bge_ape_send_event(struct bge_softc *, uint32_t);
496 static void bge_ape_driver_state_change(struct bge_softc *, int);
497
498 /*
499 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
500 * leak information to untrusted users. It is also known to cause alignment
501 * traps on certain architectures.
502 */
503 #ifdef BGE_REGISTER_DEBUG
504 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
505 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
506 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
507 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
508 #endif
509 static void bge_add_sysctls(struct bge_softc *);
510 static void bge_add_sysctl_stats_regs(struct bge_softc *,
511 struct sysctl_ctx_list *, struct sysctl_oid_list *);
512 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
513 struct sysctl_oid_list *);
514 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
515
516 static device_method_t bge_methods[] = {
517 /* Device interface */
518 DEVMETHOD(device_probe, bge_probe),
519 DEVMETHOD(device_attach, bge_attach),
520 DEVMETHOD(device_detach, bge_detach),
521 DEVMETHOD(device_shutdown, bge_shutdown),
522 DEVMETHOD(device_suspend, bge_suspend),
523 DEVMETHOD(device_resume, bge_resume),
524
525 /* MII interface */
526 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
527 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
528 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
529
530 DEVMETHOD_END
531 };
532
533 static driver_t bge_driver = {
534 "bge",
535 bge_methods,
536 sizeof(struct bge_softc)
537 };
538
539 static devclass_t bge_devclass;
540
541 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
542 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
543
544 static int bge_allow_asf = 1;
545
546 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
547 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
548 "Allow ASF mode if available");
549
550 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
551 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
552 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
553 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
554 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
555
556 static int
bge_has_eaddr(struct bge_softc * sc)557 bge_has_eaddr(struct bge_softc *sc)
558 {
559 #ifdef __sparc64__
560 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
561 device_t dev;
562 uint32_t subvendor;
563
564 dev = sc->bge_dev;
565
566 /*
567 * The on-board BGEs found in sun4u machines aren't fitted with
568 * an EEPROM which means that we have to obtain the MAC address
569 * via OFW and that some tests will always fail. We distinguish
570 * such BGEs by the subvendor ID, which also has to be obtained
571 * from OFW instead of the PCI configuration space as the latter
572 * indicates Broadcom as the subvendor of the netboot interface.
573 * For early Blade 1500 and 2500 we even have to check the OFW
574 * device path as the subvendor ID always defaults to Broadcom
575 * there.
576 */
577 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
578 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
579 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
580 return (0);
581 memset(buf, 0, sizeof(buf));
582 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
583 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
584 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
585 return (0);
586 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
587 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
588 return (0);
589 }
590 #endif
591 return (1);
592 }
593
594 static uint32_t
bge_readmem_ind(struct bge_softc * sc,int off)595 bge_readmem_ind(struct bge_softc *sc, int off)
596 {
597 device_t dev;
598 uint32_t val;
599
600 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
601 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
602 return (0);
603
604 dev = sc->bge_dev;
605
606 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
607 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
608 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
609 return (val);
610 }
611
612 static void
bge_writemem_ind(struct bge_softc * sc,int off,int val)613 bge_writemem_ind(struct bge_softc *sc, int off, int val)
614 {
615 device_t dev;
616
617 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
618 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
619 return;
620
621 dev = sc->bge_dev;
622
623 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
624 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
625 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
626 }
627
628 #ifdef notdef
629 static uint32_t
bge_readreg_ind(struct bge_softc * sc,int off)630 bge_readreg_ind(struct bge_softc *sc, int off)
631 {
632 device_t dev;
633
634 dev = sc->bge_dev;
635
636 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
637 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
638 }
639 #endif
640
641 static void
bge_writereg_ind(struct bge_softc * sc,int off,int val)642 bge_writereg_ind(struct bge_softc *sc, int off, int val)
643 {
644 device_t dev;
645
646 dev = sc->bge_dev;
647
648 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
649 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
650 }
651
652 static void
bge_writemem_direct(struct bge_softc * sc,int off,int val)653 bge_writemem_direct(struct bge_softc *sc, int off, int val)
654 {
655 CSR_WRITE_4(sc, off, val);
656 }
657
658 static void
bge_writembx(struct bge_softc * sc,int off,int val)659 bge_writembx(struct bge_softc *sc, int off, int val)
660 {
661 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
662 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
663
664 CSR_WRITE_4(sc, off, val);
665 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
666 CSR_READ_4(sc, off);
667 }
668
669 /*
670 * Clear all stale locks and select the lock for this driver instance.
671 */
672 static void
bge_ape_lock_init(struct bge_softc * sc)673 bge_ape_lock_init(struct bge_softc *sc)
674 {
675 uint32_t bit, regbase;
676 int i;
677
678 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
679 regbase = BGE_APE_LOCK_GRANT;
680 else
681 regbase = BGE_APE_PER_LOCK_GRANT;
682
683 /* Clear any stale locks. */
684 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
685 switch (i) {
686 case BGE_APE_LOCK_PHY0:
687 case BGE_APE_LOCK_PHY1:
688 case BGE_APE_LOCK_PHY2:
689 case BGE_APE_LOCK_PHY3:
690 bit = BGE_APE_LOCK_GRANT_DRIVER0;
691 break;
692 default:
693 if (sc->bge_func_addr == 0)
694 bit = BGE_APE_LOCK_GRANT_DRIVER0;
695 else
696 bit = (1 << sc->bge_func_addr);
697 }
698 APE_WRITE_4(sc, regbase + 4 * i, bit);
699 }
700
701 /* Select the PHY lock based on the device's function number. */
702 switch (sc->bge_func_addr) {
703 case 0:
704 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
705 break;
706 case 1:
707 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
708 break;
709 case 2:
710 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
711 break;
712 case 3:
713 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
714 break;
715 default:
716 device_printf(sc->bge_dev,
717 "PHY lock not supported on this function\n");
718 }
719 }
720
721 /*
722 * Check for APE firmware, set flags, and print version info.
723 */
724 static void
bge_ape_read_fw_ver(struct bge_softc * sc)725 bge_ape_read_fw_ver(struct bge_softc *sc)
726 {
727 const char *fwtype;
728 uint32_t apedata, features;
729
730 /* Check for a valid APE signature in shared memory. */
731 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
732 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
733 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
734 return;
735 }
736
737 /* Check if APE firmware is running. */
738 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
739 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
740 device_printf(sc->bge_dev, "APE signature found "
741 "but FW status not ready! 0x%08x\n", apedata);
742 return;
743 }
744
745 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
746
747 /* Fetch the APE firwmare type and version. */
748 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
749 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
750 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
751 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
752 fwtype = "NCSI";
753 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
754 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
755 fwtype = "DASH";
756 } else
757 fwtype = "UNKN";
758
759 /* Print the APE firmware version. */
760 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
761 fwtype,
762 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
763 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
764 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
765 (apedata & BGE_APE_FW_VERSION_BLDMSK));
766 }
767
768 static int
bge_ape_lock(struct bge_softc * sc,int locknum)769 bge_ape_lock(struct bge_softc *sc, int locknum)
770 {
771 uint32_t bit, gnt, req, status;
772 int i, off;
773
774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
775 return (0);
776
777 /* Lock request/grant registers have different bases. */
778 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
779 req = BGE_APE_LOCK_REQ;
780 gnt = BGE_APE_LOCK_GRANT;
781 } else {
782 req = BGE_APE_PER_LOCK_REQ;
783 gnt = BGE_APE_PER_LOCK_GRANT;
784 }
785
786 off = 4 * locknum;
787
788 switch (locknum) {
789 case BGE_APE_LOCK_GPIO:
790 /* Lock required when using GPIO. */
791 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
792 return (0);
793 if (sc->bge_func_addr == 0)
794 bit = BGE_APE_LOCK_REQ_DRIVER0;
795 else
796 bit = (1 << sc->bge_func_addr);
797 break;
798 case BGE_APE_LOCK_GRC:
799 /* Lock required to reset the device. */
800 if (sc->bge_func_addr == 0)
801 bit = BGE_APE_LOCK_REQ_DRIVER0;
802 else
803 bit = (1 << sc->bge_func_addr);
804 break;
805 case BGE_APE_LOCK_MEM:
806 /* Lock required when accessing certain APE memory. */
807 if (sc->bge_func_addr == 0)
808 bit = BGE_APE_LOCK_REQ_DRIVER0;
809 else
810 bit = (1 << sc->bge_func_addr);
811 break;
812 case BGE_APE_LOCK_PHY0:
813 case BGE_APE_LOCK_PHY1:
814 case BGE_APE_LOCK_PHY2:
815 case BGE_APE_LOCK_PHY3:
816 /* Lock required when accessing PHYs. */
817 bit = BGE_APE_LOCK_REQ_DRIVER0;
818 break;
819 default:
820 return (EINVAL);
821 }
822
823 /* Request a lock. */
824 APE_WRITE_4(sc, req + off, bit);
825
826 /* Wait up to 1 second to acquire lock. */
827 for (i = 0; i < 20000; i++) {
828 status = APE_READ_4(sc, gnt + off);
829 if (status == bit)
830 break;
831 DELAY(50);
832 }
833
834 /* Handle any errors. */
835 if (status != bit) {
836 device_printf(sc->bge_dev, "APE lock %d request failed! "
837 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
838 locknum, req + off, bit & 0xFFFF, gnt + off,
839 status & 0xFFFF);
840 /* Revoke the lock request. */
841 APE_WRITE_4(sc, gnt + off, bit);
842 return (EBUSY);
843 }
844
845 return (0);
846 }
847
848 static void
bge_ape_unlock(struct bge_softc * sc,int locknum)849 bge_ape_unlock(struct bge_softc *sc, int locknum)
850 {
851 uint32_t bit, gnt;
852 int off;
853
854 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
855 return;
856
857 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
858 gnt = BGE_APE_LOCK_GRANT;
859 else
860 gnt = BGE_APE_PER_LOCK_GRANT;
861
862 off = 4 * locknum;
863
864 switch (locknum) {
865 case BGE_APE_LOCK_GPIO:
866 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
867 return;
868 if (sc->bge_func_addr == 0)
869 bit = BGE_APE_LOCK_GRANT_DRIVER0;
870 else
871 bit = (1 << sc->bge_func_addr);
872 break;
873 case BGE_APE_LOCK_GRC:
874 if (sc->bge_func_addr == 0)
875 bit = BGE_APE_LOCK_GRANT_DRIVER0;
876 else
877 bit = (1 << sc->bge_func_addr);
878 break;
879 case BGE_APE_LOCK_MEM:
880 if (sc->bge_func_addr == 0)
881 bit = BGE_APE_LOCK_GRANT_DRIVER0;
882 else
883 bit = (1 << sc->bge_func_addr);
884 break;
885 case BGE_APE_LOCK_PHY0:
886 case BGE_APE_LOCK_PHY1:
887 case BGE_APE_LOCK_PHY2:
888 case BGE_APE_LOCK_PHY3:
889 bit = BGE_APE_LOCK_GRANT_DRIVER0;
890 break;
891 default:
892 return;
893 }
894
895 APE_WRITE_4(sc, gnt + off, bit);
896 }
897
898 /*
899 * Send an event to the APE firmware.
900 */
901 static void
bge_ape_send_event(struct bge_softc * sc,uint32_t event)902 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
903 {
904 uint32_t apedata;
905 int i;
906
907 /* NCSI does not support APE events. */
908 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
909 return;
910
911 /* Wait up to 1ms for APE to service previous event. */
912 for (i = 10; i > 0; i--) {
913 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
914 break;
915 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
916 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
917 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
918 BGE_APE_EVENT_STATUS_EVENT_PENDING);
919 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
920 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
921 break;
922 }
923 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
924 DELAY(100);
925 }
926 if (i == 0)
927 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
928 event);
929 }
930
931 static void
bge_ape_driver_state_change(struct bge_softc * sc,int kind)932 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
933 {
934 uint32_t apedata, event;
935
936 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
937 return;
938
939 switch (kind) {
940 case BGE_RESET_START:
941 /* If this is the first load, clear the load counter. */
942 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
943 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
944 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
945 else {
946 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
947 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
948 }
949 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
950 BGE_APE_HOST_SEG_SIG_MAGIC);
951 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
952 BGE_APE_HOST_SEG_LEN_MAGIC);
953
954 /* Add some version info if bge(4) supports it. */
955 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
956 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
957 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
958 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
959 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
960 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
961 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
962 BGE_APE_HOST_DRVR_STATE_START);
963 event = BGE_APE_EVENT_STATUS_STATE_START;
964 break;
965 case BGE_RESET_SHUTDOWN:
966 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
967 BGE_APE_HOST_DRVR_STATE_UNLOAD);
968 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
969 break;
970 case BGE_RESET_SUSPEND:
971 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
972 break;
973 default:
974 return;
975 }
976
977 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
978 BGE_APE_EVENT_STATUS_STATE_CHNGE);
979 }
980
981 /*
982 * Map a single buffer address.
983 */
984
985 static void
bge_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)986 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
987 {
988 struct bge_dmamap_arg *ctx;
989
990 if (error)
991 return;
992
993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
994
995 ctx = arg;
996 ctx->bge_busaddr = segs->ds_addr;
997 }
998
999 static uint8_t
bge_nvram_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)1000 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1001 {
1002 uint32_t access, byte = 0;
1003 int i;
1004
1005 /* Lock. */
1006 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1007 for (i = 0; i < 8000; i++) {
1008 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1009 break;
1010 DELAY(20);
1011 }
1012 if (i == 8000)
1013 return (1);
1014
1015 /* Enable access. */
1016 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1017 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1018
1019 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1020 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1021 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1022 DELAY(10);
1023 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1024 DELAY(10);
1025 break;
1026 }
1027 }
1028
1029 if (i == BGE_TIMEOUT * 10) {
1030 if_printf(sc->bge_ifp, "nvram read timed out\n");
1031 return (1);
1032 }
1033
1034 /* Get result. */
1035 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1036
1037 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1038
1039 /* Disable access. */
1040 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1041
1042 /* Unlock. */
1043 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1044 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1045
1046 return (0);
1047 }
1048
1049 /*
1050 * Read a sequence of bytes from NVRAM.
1051 */
1052 static int
bge_read_nvram(struct bge_softc * sc,caddr_t dest,int off,int cnt)1053 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1054 {
1055 int err = 0, i;
1056 uint8_t byte = 0;
1057
1058 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1059 return (1);
1060
1061 for (i = 0; i < cnt; i++) {
1062 err = bge_nvram_getbyte(sc, off + i, &byte);
1063 if (err)
1064 break;
1065 *(dest + i) = byte;
1066 }
1067
1068 return (err ? 1 : 0);
1069 }
1070
1071 /*
1072 * Read a byte of data stored in the EEPROM at address 'addr.' The
1073 * BCM570x supports both the traditional bitbang interface and an
1074 * auto access interface for reading the EEPROM. We use the auto
1075 * access method.
1076 */
1077 static uint8_t
bge_eeprom_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)1078 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1079 {
1080 int i;
1081 uint32_t byte = 0;
1082
1083 /*
1084 * Enable use of auto EEPROM access so we can avoid
1085 * having to use the bitbang method.
1086 */
1087 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1088
1089 /* Reset the EEPROM, load the clock period. */
1090 CSR_WRITE_4(sc, BGE_EE_ADDR,
1091 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1092 DELAY(20);
1093
1094 /* Issue the read EEPROM command. */
1095 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1096
1097 /* Wait for completion */
1098 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1099 DELAY(10);
1100 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1101 break;
1102 }
1103
1104 if (i == BGE_TIMEOUT * 10) {
1105 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1106 return (1);
1107 }
1108
1109 /* Get result. */
1110 byte = CSR_READ_4(sc, BGE_EE_DATA);
1111
1112 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1113
1114 return (0);
1115 }
1116
1117 /*
1118 * Read a sequence of bytes from the EEPROM.
1119 */
1120 static int
bge_read_eeprom(struct bge_softc * sc,caddr_t dest,int off,int cnt)1121 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1122 {
1123 int i, error = 0;
1124 uint8_t byte = 0;
1125
1126 for (i = 0; i < cnt; i++) {
1127 error = bge_eeprom_getbyte(sc, off + i, &byte);
1128 if (error)
1129 break;
1130 *(dest + i) = byte;
1131 }
1132
1133 return (error ? 1 : 0);
1134 }
1135
1136 static int
bge_miibus_readreg(device_t dev,int phy,int reg)1137 bge_miibus_readreg(device_t dev, int phy, int reg)
1138 {
1139 struct bge_softc *sc;
1140 uint32_t val;
1141 int i;
1142
1143 sc = device_get_softc(dev);
1144
1145 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1146 return (0);
1147
1148 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1149 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1150 CSR_WRITE_4(sc, BGE_MI_MODE,
1151 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1152 DELAY(80);
1153 }
1154
1155 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1156 BGE_MIPHY(phy) | BGE_MIREG(reg));
1157
1158 /* Poll for the PHY register access to complete. */
1159 for (i = 0; i < BGE_TIMEOUT; i++) {
1160 DELAY(10);
1161 val = CSR_READ_4(sc, BGE_MI_COMM);
1162 if ((val & BGE_MICOMM_BUSY) == 0) {
1163 DELAY(5);
1164 val = CSR_READ_4(sc, BGE_MI_COMM);
1165 break;
1166 }
1167 }
1168
1169 if (i == BGE_TIMEOUT) {
1170 device_printf(sc->bge_dev,
1171 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1172 phy, reg, val);
1173 val = 0;
1174 }
1175
1176 /* Restore the autopoll bit if necessary. */
1177 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1178 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1179 DELAY(80);
1180 }
1181
1182 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1183
1184 if (val & BGE_MICOMM_READFAIL)
1185 return (0);
1186
1187 return (val & 0xFFFF);
1188 }
1189
1190 static int
bge_miibus_writereg(device_t dev,int phy,int reg,int val)1191 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1192 {
1193 struct bge_softc *sc;
1194 int i;
1195
1196 sc = device_get_softc(dev);
1197
1198 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1199 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1200 return (0);
1201
1202 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1203 return (0);
1204
1205 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1206 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1207 CSR_WRITE_4(sc, BGE_MI_MODE,
1208 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1209 DELAY(80);
1210 }
1211
1212 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1213 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1214
1215 for (i = 0; i < BGE_TIMEOUT; i++) {
1216 DELAY(10);
1217 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1218 DELAY(5);
1219 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1220 break;
1221 }
1222 }
1223
1224 /* Restore the autopoll bit if necessary. */
1225 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1226 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1227 DELAY(80);
1228 }
1229
1230 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1231
1232 if (i == BGE_TIMEOUT)
1233 device_printf(sc->bge_dev,
1234 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1235 phy, reg, val);
1236
1237 return (0);
1238 }
1239
1240 static void
bge_miibus_statchg(device_t dev)1241 bge_miibus_statchg(device_t dev)
1242 {
1243 struct bge_softc *sc;
1244 struct mii_data *mii;
1245 uint32_t mac_mode, rx_mode, tx_mode;
1246
1247 sc = device_get_softc(dev);
1248 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1249 return;
1250 mii = device_get_softc(sc->bge_miibus);
1251
1252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1253 (IFM_ACTIVE | IFM_AVALID)) {
1254 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1255 case IFM_10_T:
1256 case IFM_100_TX:
1257 sc->bge_link = 1;
1258 break;
1259 case IFM_1000_T:
1260 case IFM_1000_SX:
1261 case IFM_2500_SX:
1262 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1263 sc->bge_link = 1;
1264 else
1265 sc->bge_link = 0;
1266 break;
1267 default:
1268 sc->bge_link = 0;
1269 break;
1270 }
1271 } else
1272 sc->bge_link = 0;
1273 if (sc->bge_link == 0)
1274 return;
1275
1276 /*
1277 * APE firmware touches these registers to keep the MAC
1278 * connected to the outside world. Try to keep the
1279 * accesses atomic.
1280 */
1281
1282 /* Set the port mode (MII/GMII) to match the link speed. */
1283 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1284 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1285 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1286 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1287
1288 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1289 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1290 mac_mode |= BGE_PORTMODE_GMII;
1291 else
1292 mac_mode |= BGE_PORTMODE_MII;
1293
1294 /* Set MAC flow control behavior to match link flow control settings. */
1295 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1296 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1299 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1300 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1301 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1302 } else
1303 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1304
1305 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1306 DELAY(40);
1307 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1308 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1309 }
1310
1311 /*
1312 * Intialize a standard receive ring descriptor.
1313 */
1314 static int
bge_newbuf_std(struct bge_softc * sc,int i)1315 bge_newbuf_std(struct bge_softc *sc, int i)
1316 {
1317 struct mbuf *m;
1318 struct bge_rx_bd *r;
1319 bus_dma_segment_t segs[1];
1320 bus_dmamap_t map;
1321 int error, nsegs;
1322
1323 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1324 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1325 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1326 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1327 if (m == NULL)
1328 return (ENOBUFS);
1329 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1330 } else {
1331 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1332 if (m == NULL)
1333 return (ENOBUFS);
1334 m->m_len = m->m_pkthdr.len = MCLBYTES;
1335 }
1336 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1337 m_adj(m, ETHER_ALIGN);
1338
1339 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1340 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1341 if (error != 0) {
1342 m_freem(m);
1343 return (error);
1344 }
1345 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1346 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1347 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1348 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1349 sc->bge_cdata.bge_rx_std_dmamap[i]);
1350 }
1351 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1352 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1353 sc->bge_cdata.bge_rx_std_sparemap = map;
1354 sc->bge_cdata.bge_rx_std_chain[i] = m;
1355 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1356 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1357 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1358 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1359 r->bge_flags = BGE_RXBDFLAG_END;
1360 r->bge_len = segs[0].ds_len;
1361 r->bge_idx = i;
1362
1363 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1364 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1365
1366 return (0);
1367 }
1368
1369 /*
1370 * Initialize a jumbo receive ring descriptor. This allocates
1371 * a jumbo buffer from the pool managed internally by the driver.
1372 */
1373 static int
bge_newbuf_jumbo(struct bge_softc * sc,int i)1374 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1375 {
1376 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1377 bus_dmamap_t map;
1378 struct bge_extrx_bd *r;
1379 struct mbuf *m;
1380 int error, nsegs;
1381
1382 MGETHDR(m, M_NOWAIT, MT_DATA);
1383 if (m == NULL)
1384 return (ENOBUFS);
1385
1386 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1387 m_freem(m);
1388 return (ENOBUFS);
1389 }
1390 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1391 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1392 m_adj(m, ETHER_ALIGN);
1393
1394 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1395 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1396 if (error != 0) {
1397 m_freem(m);
1398 return (error);
1399 }
1400
1401 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1402 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1403 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1404 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1405 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1406 }
1407 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1409 sc->bge_cdata.bge_rx_jumbo_sparemap;
1410 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1411 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1412 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1413 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1416
1417 /*
1418 * Fill in the extended RX buffer descriptor.
1419 */
1420 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1421 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1422 r->bge_idx = i;
1423 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1424 switch (nsegs) {
1425 case 4:
1426 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1427 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1428 r->bge_len3 = segs[3].ds_len;
1429 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1430 case 3:
1431 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1432 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1433 r->bge_len2 = segs[2].ds_len;
1434 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1435 case 2:
1436 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1437 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1438 r->bge_len1 = segs[1].ds_len;
1439 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1440 case 1:
1441 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1442 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1443 r->bge_len0 = segs[0].ds_len;
1444 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1445 break;
1446 default:
1447 panic("%s: %d segments\n", __func__, nsegs);
1448 }
1449
1450 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1451 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1452
1453 return (0);
1454 }
1455
1456 static int
bge_init_rx_ring_std(struct bge_softc * sc)1457 bge_init_rx_ring_std(struct bge_softc *sc)
1458 {
1459 int error, i;
1460
1461 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1462 sc->bge_std = 0;
1463 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1464 if ((error = bge_newbuf_std(sc, i)) != 0)
1465 return (error);
1466 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1467 }
1468
1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1470 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1471
1472 sc->bge_std = 0;
1473 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1474
1475 return (0);
1476 }
1477
1478 static void
bge_free_rx_ring_std(struct bge_softc * sc)1479 bge_free_rx_ring_std(struct bge_softc *sc)
1480 {
1481 int i;
1482
1483 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1484 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1485 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1486 sc->bge_cdata.bge_rx_std_dmamap[i],
1487 BUS_DMASYNC_POSTREAD);
1488 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1489 sc->bge_cdata.bge_rx_std_dmamap[i]);
1490 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1491 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1492 }
1493 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1494 sizeof(struct bge_rx_bd));
1495 }
1496 }
1497
1498 static int
bge_init_rx_ring_jumbo(struct bge_softc * sc)1499 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1500 {
1501 struct bge_rcb *rcb;
1502 int error, i;
1503
1504 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1505 sc->bge_jumbo = 0;
1506 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1507 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1508 return (error);
1509 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1510 }
1511
1512 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1513 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1514
1515 sc->bge_jumbo = 0;
1516
1517 /* Enable the jumbo receive producer ring. */
1518 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1519 rcb->bge_maxlen_flags =
1520 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1522
1523 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1524
1525 return (0);
1526 }
1527
1528 static void
bge_free_rx_ring_jumbo(struct bge_softc * sc)1529 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1530 {
1531 int i;
1532
1533 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1534 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1535 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1536 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1537 BUS_DMASYNC_POSTREAD);
1538 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1539 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1540 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1541 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1542 }
1543 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1544 sizeof(struct bge_extrx_bd));
1545 }
1546 }
1547
1548 static void
bge_free_tx_ring(struct bge_softc * sc)1549 bge_free_tx_ring(struct bge_softc *sc)
1550 {
1551 int i;
1552
1553 if (sc->bge_ldata.bge_tx_ring == NULL)
1554 return;
1555
1556 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1557 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1558 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1559 sc->bge_cdata.bge_tx_dmamap[i],
1560 BUS_DMASYNC_POSTWRITE);
1561 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1562 sc->bge_cdata.bge_tx_dmamap[i]);
1563 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1564 sc->bge_cdata.bge_tx_chain[i] = NULL;
1565 }
1566 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1567 sizeof(struct bge_tx_bd));
1568 }
1569 }
1570
1571 static int
bge_init_tx_ring(struct bge_softc * sc)1572 bge_init_tx_ring(struct bge_softc *sc)
1573 {
1574 sc->bge_txcnt = 0;
1575 sc->bge_tx_saved_considx = 0;
1576
1577 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1578 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1579 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1580
1581 /* Initialize transmit producer index for host-memory send ring. */
1582 sc->bge_tx_prodidx = 0;
1583 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1584
1585 /* 5700 b2 errata */
1586 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1587 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1588
1589 /* NIC-memory send ring not used; initialize to zero. */
1590 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1591 /* 5700 b2 errata */
1592 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1593 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1594
1595 return (0);
1596 }
1597
1598 static void
bge_setpromisc(struct bge_softc * sc)1599 bge_setpromisc(struct bge_softc *sc)
1600 {
1601 if_t ifp;
1602
1603 BGE_LOCK_ASSERT(sc);
1604
1605 ifp = sc->bge_ifp;
1606
1607 /* Enable or disable promiscuous mode as needed. */
1608 if (if_getflags(ifp) & IFF_PROMISC)
1609 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1610 else
1611 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1612 }
1613
1614 static void
bge_setmulti(struct bge_softc * sc)1615 bge_setmulti(struct bge_softc *sc)
1616 {
1617 if_t ifp;
1618 int mc_count = 0;
1619 uint32_t hashes[4] = { 0, 0, 0, 0 };
1620 int h, i, mcnt;
1621 unsigned char *mta;
1622
1623 BGE_LOCK_ASSERT(sc);
1624
1625 ifp = sc->bge_ifp;
1626
1627 mc_count = if_multiaddr_count(ifp, -1);
1628 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN *
1629 mc_count, M_DEVBUF, M_NOWAIT);
1630
1631 if(mta == NULL) {
1632 device_printf(sc->bge_dev,
1633 "Failed to allocated temp mcast list\n");
1634 return;
1635 }
1636
1637 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1638 for (i = 0; i < 4; i++)
1639 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1640 free(mta, M_DEVBUF);
1641 return;
1642 }
1643
1644 /* First, zot all the existing filters. */
1645 for (i = 0; i < 4; i++)
1646 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1647
1648 if_multiaddr_array(ifp, mta, &mcnt, mc_count);
1649 for(i = 0; i < mcnt; i++) {
1650 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN),
1651 ETHER_ADDR_LEN) & 0x7F;
1652 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1653 }
1654
1655 for (i = 0; i < 4; i++)
1656 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1657
1658 free(mta, M_DEVBUF);
1659 }
1660
1661 static void
bge_setvlan(struct bge_softc * sc)1662 bge_setvlan(struct bge_softc *sc)
1663 {
1664 if_t ifp;
1665
1666 BGE_LOCK_ASSERT(sc);
1667
1668 ifp = sc->bge_ifp;
1669
1670 /* Enable or disable VLAN tag stripping as needed. */
1671 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1672 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1673 else
1674 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1675 }
1676
1677 static void
bge_sig_pre_reset(struct bge_softc * sc,int type)1678 bge_sig_pre_reset(struct bge_softc *sc, int type)
1679 {
1680
1681 /*
1682 * Some chips don't like this so only do this if ASF is enabled
1683 */
1684 if (sc->bge_asf_mode)
1685 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1686
1687 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1688 switch (type) {
1689 case BGE_RESET_START:
1690 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1691 BGE_FW_DRV_STATE_START);
1692 break;
1693 case BGE_RESET_SHUTDOWN:
1694 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1695 BGE_FW_DRV_STATE_UNLOAD);
1696 break;
1697 case BGE_RESET_SUSPEND:
1698 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1699 BGE_FW_DRV_STATE_SUSPEND);
1700 break;
1701 }
1702 }
1703
1704 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1705 bge_ape_driver_state_change(sc, type);
1706 }
1707
1708 static void
bge_sig_post_reset(struct bge_softc * sc,int type)1709 bge_sig_post_reset(struct bge_softc *sc, int type)
1710 {
1711
1712 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1713 switch (type) {
1714 case BGE_RESET_START:
1715 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1716 BGE_FW_DRV_STATE_START_DONE);
1717 /* START DONE */
1718 break;
1719 case BGE_RESET_SHUTDOWN:
1720 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1721 BGE_FW_DRV_STATE_UNLOAD_DONE);
1722 break;
1723 }
1724 }
1725 if (type == BGE_RESET_SHUTDOWN)
1726 bge_ape_driver_state_change(sc, type);
1727 }
1728
1729 static void
bge_sig_legacy(struct bge_softc * sc,int type)1730 bge_sig_legacy(struct bge_softc *sc, int type)
1731 {
1732
1733 if (sc->bge_asf_mode) {
1734 switch (type) {
1735 case BGE_RESET_START:
1736 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1737 BGE_FW_DRV_STATE_START);
1738 break;
1739 case BGE_RESET_SHUTDOWN:
1740 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1741 BGE_FW_DRV_STATE_UNLOAD);
1742 break;
1743 }
1744 }
1745 }
1746
1747 static void
bge_stop_fw(struct bge_softc * sc)1748 bge_stop_fw(struct bge_softc *sc)
1749 {
1750 int i;
1751
1752 if (sc->bge_asf_mode) {
1753 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1754 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1755 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1756
1757 for (i = 0; i < 100; i++ ) {
1758 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1759 BGE_RX_CPU_DRV_EVENT))
1760 break;
1761 DELAY(10);
1762 }
1763 }
1764 }
1765
1766 static uint32_t
bge_dma_swap_options(struct bge_softc * sc)1767 bge_dma_swap_options(struct bge_softc *sc)
1768 {
1769 uint32_t dma_options;
1770
1771 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1772 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1773 #if BYTE_ORDER == BIG_ENDIAN
1774 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1775 #endif
1776 return (dma_options);
1777 }
1778
1779 /*
1780 * Do endian, PCI and DMA initialization.
1781 */
1782 static int
bge_chipinit(struct bge_softc * sc)1783 bge_chipinit(struct bge_softc *sc)
1784 {
1785 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1786 uint16_t val;
1787 int i;
1788
1789 /* Set endianness before we access any non-PCI registers. */
1790 misc_ctl = BGE_INIT;
1791 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1792 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1793 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1794
1795 /*
1796 * Clear the MAC statistics block in the NIC's
1797 * internal memory.
1798 */
1799 for (i = BGE_STATS_BLOCK;
1800 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1801 BGE_MEMWIN_WRITE(sc, i, 0);
1802
1803 for (i = BGE_STATUS_BLOCK;
1804 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1805 BGE_MEMWIN_WRITE(sc, i, 0);
1806
1807 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1808 /*
1809 * Fix data corruption caused by non-qword write with WB.
1810 * Fix master abort in PCI mode.
1811 * Fix PCI latency timer.
1812 */
1813 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1814 val |= (1 << 10) | (1 << 12) | (1 << 13);
1815 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1816 }
1817
1818 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1819 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1820 /*
1821 * For the 57766 and non Ax versions of 57765, bootcode
1822 * needs to setup the PCIE Fast Training Sequence (FTS)
1823 * value to prevent transmit hangs.
1824 */
1825 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1826 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1827 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1828 BGE_CPMU_PADRNG_CTL_RDIV2);
1829 }
1830 }
1831
1832 /*
1833 * Set up the PCI DMA control register.
1834 */
1835 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1836 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1837 if (sc->bge_flags & BGE_FLAG_PCIE) {
1838 if (sc->bge_mps >= 256)
1839 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1840 else
1841 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1842 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1843 if (BGE_IS_5714_FAMILY(sc)) {
1844 /* 256 bytes for read and write. */
1845 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1846 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1847 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1848 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1849 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1850 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1851 /*
1852 * In the BCM5703, the DMA read watermark should
1853 * be set to less than or equal to the maximum
1854 * memory read byte count of the PCI-X command
1855 * register.
1856 */
1857 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1858 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1859 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1860 /* 1536 bytes for read, 384 bytes for write. */
1861 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1862 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1863 } else {
1864 /* 384 bytes for read and write. */
1865 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1866 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1867 0x0F;
1868 }
1869 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1870 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1871 uint32_t tmp;
1872
1873 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1874 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1875 if (tmp == 6 || tmp == 7)
1876 dma_rw_ctl |=
1877 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1878
1879 /* Set PCI-X DMA write workaround. */
1880 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1881 }
1882 } else {
1883 /* Conventional PCI bus: 256 bytes for read and write. */
1884 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1885 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1886
1887 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1888 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1889 dma_rw_ctl |= 0x0F;
1890 }
1891 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1892 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1893 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1894 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1895 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1896 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1897 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1898 if (BGE_IS_5717_PLUS(sc)) {
1899 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1900 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1901 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1902 /*
1903 * Enable HW workaround for controllers that misinterpret
1904 * a status tag update and leave interrupts permanently
1905 * disabled.
1906 */
1907 if (!BGE_IS_57765_PLUS(sc) &&
1908 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1909 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1910 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1911 }
1912 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1913
1914 /*
1915 * Set up general mode register.
1916 */
1917 mode_ctl = bge_dma_swap_options(sc);
1918 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1919 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1920 /* Retain Host-2-BMC settings written by APE firmware. */
1921 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1922 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1923 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1924 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1925 }
1926 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1927 BGE_MODECTL_TX_NO_PHDR_CSUM;
1928
1929 /*
1930 * BCM5701 B5 have a bug causing data corruption when using
1931 * 64-bit DMA reads, which can be terminated early and then
1932 * completed later as 32-bit accesses, in combination with
1933 * certain bridges.
1934 */
1935 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1936 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1937 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1938
1939 /*
1940 * Tell the firmware the driver is running
1941 */
1942 if (sc->bge_asf_mode & ASF_STACKUP)
1943 mode_ctl |= BGE_MODECTL_STACKUP;
1944
1945 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1946
1947 /*
1948 * Disable memory write invalidate. Apparently it is not supported
1949 * properly by these devices.
1950 */
1951 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1952
1953 /* Set the timer prescaler (always 66 MHz). */
1954 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1955
1956 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1957 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1958 DELAY(40); /* XXX */
1959
1960 /* Put PHY into ready state */
1961 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1962 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1963 DELAY(40);
1964 }
1965
1966 return (0);
1967 }
1968
1969 static int
bge_blockinit(struct bge_softc * sc)1970 bge_blockinit(struct bge_softc *sc)
1971 {
1972 struct bge_rcb *rcb;
1973 bus_size_t vrcb;
1974 bge_hostaddr taddr;
1975 uint32_t dmactl, rdmareg, val;
1976 int i, limit;
1977
1978 /*
1979 * Initialize the memory window pointer register so that
1980 * we can access the first 32K of internal NIC RAM. This will
1981 * allow us to set up the TX send ring RCBs and the RX return
1982 * ring RCBs, plus other things which live in NIC memory.
1983 */
1984 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1985
1986 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1987
1988 if (!(BGE_IS_5705_PLUS(sc))) {
1989 /* Configure mbuf memory pool */
1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1991 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1992 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1993 else
1994 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1995
1996 /* Configure DMA resource pool */
1997 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1998 BGE_DMA_DESCRIPTORS);
1999 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2000 }
2001
2002 /* Configure mbuf pool watermarks */
2003 if (BGE_IS_5717_PLUS(sc)) {
2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2005 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2008 } else {
2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2011 }
2012 } else if (!BGE_IS_5705_PLUS(sc)) {
2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2016 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2018 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2019 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2020 } else {
2021 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2022 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2023 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2024 }
2025
2026 /* Configure DMA resource watermarks */
2027 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2028 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2029
2030 /* Enable buffer manager */
2031 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2032 /*
2033 * Change the arbitration algorithm of TXMBUF read request to
2034 * round-robin instead of priority based for BCM5719. When
2035 * TXFIFO is almost empty, RDMA will hold its request until
2036 * TXFIFO is not almost empty.
2037 */
2038 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2039 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2040 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2041
2042 /* Poll for buffer manager start indication */
2043 for (i = 0; i < BGE_TIMEOUT; i++) {
2044 DELAY(10);
2045 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2046 break;
2047 }
2048
2049 if (i == BGE_TIMEOUT) {
2050 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2051 return (ENXIO);
2052 }
2053
2054 /* Enable flow-through queues */
2055 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2056 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2057
2058 /* Wait until queue initialization is complete */
2059 for (i = 0; i < BGE_TIMEOUT; i++) {
2060 DELAY(10);
2061 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2062 break;
2063 }
2064
2065 if (i == BGE_TIMEOUT) {
2066 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2067 return (ENXIO);
2068 }
2069
2070 /*
2071 * Summary of rings supported by the controller:
2072 *
2073 * Standard Receive Producer Ring
2074 * - This ring is used to feed receive buffers for "standard"
2075 * sized frames (typically 1536 bytes) to the controller.
2076 *
2077 * Jumbo Receive Producer Ring
2078 * - This ring is used to feed receive buffers for jumbo sized
2079 * frames (i.e. anything bigger than the "standard" frames)
2080 * to the controller.
2081 *
2082 * Mini Receive Producer Ring
2083 * - This ring is used to feed receive buffers for "mini"
2084 * sized frames to the controller.
2085 * - This feature required external memory for the controller
2086 * but was never used in a production system. Should always
2087 * be disabled.
2088 *
2089 * Receive Return Ring
2090 * - After the controller has placed an incoming frame into a
2091 * receive buffer that buffer is moved into a receive return
2092 * ring. The driver is then responsible to passing the
2093 * buffer up to the stack. Many versions of the controller
2094 * support multiple RR rings.
2095 *
2096 * Send Ring
2097 * - This ring is used for outgoing frames. Many versions of
2098 * the controller support multiple send rings.
2099 */
2100
2101 /* Initialize the standard receive producer ring control block. */
2102 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2103 rcb->bge_hostaddr.bge_addr_lo =
2104 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2105 rcb->bge_hostaddr.bge_addr_hi =
2106 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2107 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2108 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2109 if (BGE_IS_5717_PLUS(sc)) {
2110 /*
2111 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2112 * Bits 15-2 : Maximum RX frame size
2113 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2114 * Bit 0 : Reserved
2115 */
2116 rcb->bge_maxlen_flags =
2117 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2118 } else if (BGE_IS_5705_PLUS(sc)) {
2119 /*
2120 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2121 * Bits 15-2 : Reserved (should be 0)
2122 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2123 * Bit 0 : Reserved
2124 */
2125 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2126 } else {
2127 /*
2128 * Ring size is always XXX entries
2129 * Bits 31-16: Maximum RX frame size
2130 * Bits 15-2 : Reserved (should be 0)
2131 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2132 * Bit 0 : Reserved
2133 */
2134 rcb->bge_maxlen_flags =
2135 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2136 }
2137 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2138 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2139 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2140 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2141 else
2142 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2143 /* Write the standard receive producer ring control block. */
2144 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2145 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2146 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2147 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2148
2149 /* Reset the standard receive producer ring producer index. */
2150 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2151
2152 /*
2153 * Initialize the jumbo RX producer ring control
2154 * block. We set the 'ring disabled' bit in the
2155 * flags field until we're actually ready to start
2156 * using this ring (i.e. once we set the MTU
2157 * high enough to require it).
2158 */
2159 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2160 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2161 /* Get the jumbo receive producer ring RCB parameters. */
2162 rcb->bge_hostaddr.bge_addr_lo =
2163 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2164 rcb->bge_hostaddr.bge_addr_hi =
2165 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2166 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2167 sc->bge_cdata.bge_rx_jumbo_ring_map,
2168 BUS_DMASYNC_PREREAD);
2169 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2170 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2171 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2172 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2173 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2174 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2175 else
2176 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2177 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2178 rcb->bge_hostaddr.bge_addr_hi);
2179 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2180 rcb->bge_hostaddr.bge_addr_lo);
2181 /* Program the jumbo receive producer ring RCB parameters. */
2182 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2183 rcb->bge_maxlen_flags);
2184 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2185 /* Reset the jumbo receive producer ring producer index. */
2186 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2187 }
2188
2189 /* Disable the mini receive producer ring RCB. */
2190 if (BGE_IS_5700_FAMILY(sc)) {
2191 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2192 rcb->bge_maxlen_flags =
2193 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2194 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2195 rcb->bge_maxlen_flags);
2196 /* Reset the mini receive producer ring producer index. */
2197 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2198 }
2199
2200 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2201 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2202 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2203 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2204 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2205 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2206 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2207 }
2208 /*
2209 * The BD ring replenish thresholds control how often the
2210 * hardware fetches new BD's from the producer rings in host
2211 * memory. Setting the value too low on a busy system can
2212 * starve the hardware and recue the throughpout.
2213 *
2214 * Set the BD ring replentish thresholds. The recommended
2215 * values are 1/8th the number of descriptors allocated to
2216 * each ring.
2217 * XXX The 5754 requires a lower threshold, so it might be a
2218 * requirement of all 575x family chips. The Linux driver sets
2219 * the lower threshold for all 5705 family chips as well, but there
2220 * are reports that it might not need to be so strict.
2221 *
2222 * XXX Linux does some extra fiddling here for the 5906 parts as
2223 * well.
2224 */
2225 if (BGE_IS_5705_PLUS(sc))
2226 val = 8;
2227 else
2228 val = BGE_STD_RX_RING_CNT / 8;
2229 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2230 if (BGE_IS_JUMBO_CAPABLE(sc))
2231 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2232 BGE_JUMBO_RX_RING_CNT/8);
2233 if (BGE_IS_5717_PLUS(sc)) {
2234 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2235 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2236 }
2237
2238 /*
2239 * Disable all send rings by setting the 'ring disabled' bit
2240 * in the flags field of all the TX send ring control blocks,
2241 * located in NIC memory.
2242 */
2243 if (!BGE_IS_5705_PLUS(sc))
2244 /* 5700 to 5704 had 16 send rings. */
2245 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2246 else if (BGE_IS_57765_PLUS(sc) ||
2247 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2248 limit = 2;
2249 else if (BGE_IS_5717_PLUS(sc))
2250 limit = 4;
2251 else
2252 limit = 1;
2253 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2254 for (i = 0; i < limit; i++) {
2255 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2256 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2257 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2258 vrcb += sizeof(struct bge_rcb);
2259 }
2260
2261 /* Configure send ring RCB 0 (we use only the first ring) */
2262 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2263 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2264 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2266 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2267 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2268 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2269 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2270 else
2271 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2272 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2273 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2274 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2275
2276 /*
2277 * Disable all receive return rings by setting the
2278 * 'ring diabled' bit in the flags field of all the receive
2279 * return ring control blocks, located in NIC memory.
2280 */
2281 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2282 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2283 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2284 /* Should be 17, use 16 until we get an SRAM map. */
2285 limit = 16;
2286 } else if (!BGE_IS_5705_PLUS(sc))
2287 limit = BGE_RX_RINGS_MAX;
2288 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2289 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2290 BGE_IS_57765_PLUS(sc))
2291 limit = 4;
2292 else
2293 limit = 1;
2294 /* Disable all receive return rings. */
2295 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2296 for (i = 0; i < limit; i++) {
2297 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2298 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2299 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2300 BGE_RCB_FLAG_RING_DISABLED);
2301 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2302 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2303 (i * (sizeof(uint64_t))), 0);
2304 vrcb += sizeof(struct bge_rcb);
2305 }
2306
2307 /*
2308 * Set up receive return ring 0. Note that the NIC address
2309 * for RX return rings is 0x0. The return rings live entirely
2310 * within the host, so the nicaddr field in the RCB isn't used.
2311 */
2312 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2313 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2314 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2315 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2316 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2317 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2318 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2319
2320 /* Set random backoff seed for TX */
2321 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2322 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2323 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2324 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2325 BGE_TX_BACKOFF_SEED_MASK);
2326
2327 /* Set inter-packet gap */
2328 val = 0x2620;
2329 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2330 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2331 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2332 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2333 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2334
2335 /*
2336 * Specify which ring to use for packets that don't match
2337 * any RX rules.
2338 */
2339 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2340
2341 /*
2342 * Configure number of RX lists. One interrupt distribution
2343 * list, sixteen active lists, one bad frames class.
2344 */
2345 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2346
2347 /* Inialize RX list placement stats mask. */
2348 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2349 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2350
2351 /* Disable host coalescing until we get it set up */
2352 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2353
2354 /* Poll to make sure it's shut down. */
2355 for (i = 0; i < BGE_TIMEOUT; i++) {
2356 DELAY(10);
2357 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2358 break;
2359 }
2360
2361 if (i == BGE_TIMEOUT) {
2362 device_printf(sc->bge_dev,
2363 "host coalescing engine failed to idle\n");
2364 return (ENXIO);
2365 }
2366
2367 /* Set up host coalescing defaults */
2368 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2369 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2370 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2371 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2372 if (!(BGE_IS_5705_PLUS(sc))) {
2373 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2374 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2375 }
2376 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2377 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2378
2379 /* Set up address of statistics block */
2380 if (!(BGE_IS_5705_PLUS(sc))) {
2381 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2382 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2383 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2384 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2385 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2386 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2387 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2388 }
2389
2390 /* Set up address of status block */
2391 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2392 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2393 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2394 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2395
2396 /* Set up status block size. */
2397 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2398 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2399 val = BGE_STATBLKSZ_FULL;
2400 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2401 } else {
2402 val = BGE_STATBLKSZ_32BYTE;
2403 bzero(sc->bge_ldata.bge_status_block, 32);
2404 }
2405 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2406 sc->bge_cdata.bge_status_map,
2407 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2408
2409 /* Turn on host coalescing state machine */
2410 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2411
2412 /* Turn on RX BD completion state machine and enable attentions */
2413 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2414 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2415
2416 /* Turn on RX list placement state machine */
2417 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2418
2419 /* Turn on RX list selector state machine. */
2420 if (!(BGE_IS_5705_PLUS(sc)))
2421 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2422
2423 /* Turn on DMA, clear stats. */
2424 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2425 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2426 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2427 BGE_MACMODE_FRMHDR_DMA_ENB;
2428
2429 if (sc->bge_flags & BGE_FLAG_TBI)
2430 val |= BGE_PORTMODE_TBI;
2431 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2432 val |= BGE_PORTMODE_GMII;
2433 else
2434 val |= BGE_PORTMODE_MII;
2435
2436 /* Allow APE to send/receive frames. */
2437 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2438 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2439
2440 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2441 DELAY(40);
2442
2443 /* Set misc. local control, enable interrupts on attentions */
2444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2445
2446 #ifdef notdef
2447 /* Assert GPIO pins for PHY reset */
2448 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2449 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2450 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2451 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2452 #endif
2453
2454 /* Turn on DMA completion state machine */
2455 if (!(BGE_IS_5705_PLUS(sc)))
2456 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2457
2458 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2459
2460 /* Enable host coalescing bug fix. */
2461 if (BGE_IS_5755_PLUS(sc))
2462 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2463
2464 /* Request larger DMA burst size to get better performance. */
2465 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2466 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2467
2468 /* Turn on write DMA state machine */
2469 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2470 DELAY(40);
2471
2472 /* Turn on read DMA state machine */
2473 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2474
2475 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2476 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2477
2478 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2479 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2480 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2481 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2482 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2483 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2484 if (sc->bge_flags & BGE_FLAG_PCIE)
2485 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2486 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2487 val |= BGE_RDMAMODE_TSO4_ENABLE;
2488 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2489 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2490 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2491 val |= BGE_RDMAMODE_TSO6_ENABLE;
2492 }
2493
2494 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2495 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2496 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2497 BGE_RDMAMODE_H2BNC_VLAN_DET;
2498 /*
2499 * Allow multiple outstanding read requests from
2500 * non-LSO read DMA engine.
2501 */
2502 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2503 }
2504
2505 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2506 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2507 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2508 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2509 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2510 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2511 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2512 else
2513 rdmareg = BGE_RDMA_RSRVCTRL;
2514 dmactl = CSR_READ_4(sc, rdmareg);
2515 /*
2516 * Adjust tx margin to prevent TX data corruption and
2517 * fix internal FIFO overflow.
2518 */
2519 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2520 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2521 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2522 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2523 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2524 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2525 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2526 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2527 }
2528 /*
2529 * Enable fix for read DMA FIFO overruns.
2530 * The fix is to limit the number of RX BDs
2531 * the hardware would fetch at a fime.
2532 */
2533 CSR_WRITE_4(sc, rdmareg, dmactl |
2534 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2535 }
2536
2537 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2538 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2539 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2540 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2541 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2542 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2543 /*
2544 * Allow 4KB burst length reads for non-LSO frames.
2545 * Enable 512B burst length reads for buffer descriptors.
2546 */
2547 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2548 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2549 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2550 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2551 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2552 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2553 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2554 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2555 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2556 }
2557
2558 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2559 DELAY(40);
2560
2561 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2562 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2563 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2564 if ((val & 0xFFFF) > BGE_FRAMELEN)
2565 break;
2566 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2567 break;
2568 }
2569 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2570 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2571 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2572 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2573 else
2574 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2575 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2576 }
2577 }
2578
2579 /* Turn on RX data completion state machine */
2580 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2581
2582 /* Turn on RX BD initiator state machine */
2583 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2584
2585 /* Turn on RX data and RX BD initiator state machine */
2586 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2587
2588 /* Turn on Mbuf cluster free state machine */
2589 if (!(BGE_IS_5705_PLUS(sc)))
2590 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2591
2592 /* Turn on send BD completion state machine */
2593 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2594
2595 /* Turn on send data completion state machine */
2596 val = BGE_SDCMODE_ENABLE;
2597 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2598 val |= BGE_SDCMODE_CDELAY;
2599 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2600
2601 /* Turn on send data initiator state machine */
2602 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2603 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2604 BGE_SDIMODE_HW_LSO_PRE_DMA);
2605 else
2606 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2607
2608 /* Turn on send BD initiator state machine */
2609 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2610
2611 /* Turn on send BD selector state machine */
2612 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2613
2614 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2615 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2616 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2617
2618 /* ack/clear link change events */
2619 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2620 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2621 BGE_MACSTAT_LINK_CHANGED);
2622 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2623
2624 /*
2625 * Enable attention when the link has changed state for
2626 * devices that use auto polling.
2627 */
2628 if (sc->bge_flags & BGE_FLAG_TBI) {
2629 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2630 } else {
2631 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2632 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2633 DELAY(80);
2634 }
2635 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2636 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2637 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2638 BGE_EVTENB_MI_INTERRUPT);
2639 }
2640
2641 /*
2642 * Clear any pending link state attention.
2643 * Otherwise some link state change events may be lost until attention
2644 * is cleared by bge_intr() -> bge_link_upd() sequence.
2645 * It's not necessary on newer BCM chips - perhaps enabling link
2646 * state change attentions implies clearing pending attention.
2647 */
2648 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2649 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2650 BGE_MACSTAT_LINK_CHANGED);
2651
2652 /* Enable link state change attentions. */
2653 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2654
2655 return (0);
2656 }
2657
2658 static const struct bge_revision *
bge_lookup_rev(uint32_t chipid)2659 bge_lookup_rev(uint32_t chipid)
2660 {
2661 const struct bge_revision *br;
2662
2663 for (br = bge_revisions; br->br_name != NULL; br++) {
2664 if (br->br_chipid == chipid)
2665 return (br);
2666 }
2667
2668 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2669 if (br->br_chipid == BGE_ASICREV(chipid))
2670 return (br);
2671 }
2672
2673 return (NULL);
2674 }
2675
2676 static const struct bge_vendor *
bge_lookup_vendor(uint16_t vid)2677 bge_lookup_vendor(uint16_t vid)
2678 {
2679 const struct bge_vendor *v;
2680
2681 for (v = bge_vendors; v->v_name != NULL; v++)
2682 if (v->v_id == vid)
2683 return (v);
2684
2685 return (NULL);
2686 }
2687
2688 static uint32_t
bge_chipid(device_t dev)2689 bge_chipid(device_t dev)
2690 {
2691 uint32_t id;
2692
2693 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2694 BGE_PCIMISCCTL_ASICREV_SHIFT;
2695 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2696 /*
2697 * Find the ASCI revision. Different chips use different
2698 * registers.
2699 */
2700 switch (pci_get_device(dev)) {
2701 case BCOM_DEVICEID_BCM5717:
2702 case BCOM_DEVICEID_BCM5718:
2703 case BCOM_DEVICEID_BCM5719:
2704 case BCOM_DEVICEID_BCM5720:
2705 case BCOM_DEVICEID_BCM5725:
2706 case BCOM_DEVICEID_BCM5727:
2707 case BCOM_DEVICEID_BCM5762:
2708 case BCOM_DEVICEID_BCM57764:
2709 case BCOM_DEVICEID_BCM57767:
2710 case BCOM_DEVICEID_BCM57787:
2711 id = pci_read_config(dev,
2712 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2713 break;
2714 case BCOM_DEVICEID_BCM57761:
2715 case BCOM_DEVICEID_BCM57762:
2716 case BCOM_DEVICEID_BCM57765:
2717 case BCOM_DEVICEID_BCM57766:
2718 case BCOM_DEVICEID_BCM57781:
2719 case BCOM_DEVICEID_BCM57782:
2720 case BCOM_DEVICEID_BCM57785:
2721 case BCOM_DEVICEID_BCM57786:
2722 case BCOM_DEVICEID_BCM57791:
2723 case BCOM_DEVICEID_BCM57795:
2724 id = pci_read_config(dev,
2725 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2726 break;
2727 default:
2728 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2729 }
2730 }
2731 return (id);
2732 }
2733
2734 /*
2735 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2736 * against our list and return its name if we find a match.
2737 *
2738 * Note that since the Broadcom controller contains VPD support, we
2739 * try to get the device name string from the controller itself instead
2740 * of the compiled-in string. It guarantees we'll always announce the
2741 * right product name. We fall back to the compiled-in string when
2742 * VPD is unavailable or corrupt.
2743 */
2744 static int
bge_probe(device_t dev)2745 bge_probe(device_t dev)
2746 {
2747 char buf[96];
2748 char model[64];
2749 const struct bge_revision *br;
2750 const char *pname;
2751 struct bge_softc *sc;
2752 const struct bge_type *t = bge_devs;
2753 const struct bge_vendor *v;
2754 uint32_t id;
2755 uint16_t did, vid;
2756
2757 sc = device_get_softc(dev);
2758 sc->bge_dev = dev;
2759 vid = pci_get_vendor(dev);
2760 did = pci_get_device(dev);
2761 while(t->bge_vid != 0) {
2762 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2763 id = bge_chipid(dev);
2764 br = bge_lookup_rev(id);
2765 if (bge_has_eaddr(sc) &&
2766 pci_get_vpd_ident(dev, &pname) == 0)
2767 snprintf(model, sizeof(model), "%s", pname);
2768 else {
2769 v = bge_lookup_vendor(vid);
2770 snprintf(model, sizeof(model), "%s %s",
2771 v != NULL ? v->v_name : "Unknown",
2772 br != NULL ? br->br_name :
2773 "NetXtreme/NetLink Ethernet Controller");
2774 }
2775 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2776 model, br != NULL ? "" : "unknown ", id);
2777 device_set_desc_copy(dev, buf);
2778 return (BUS_PROBE_DEFAULT);
2779 }
2780 t++;
2781 }
2782
2783 return (ENXIO);
2784 }
2785
2786 static void
bge_dma_free(struct bge_softc * sc)2787 bge_dma_free(struct bge_softc *sc)
2788 {
2789 int i;
2790
2791 /* Destroy DMA maps for RX buffers. */
2792 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2793 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2794 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2795 sc->bge_cdata.bge_rx_std_dmamap[i]);
2796 }
2797 if (sc->bge_cdata.bge_rx_std_sparemap)
2798 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2799 sc->bge_cdata.bge_rx_std_sparemap);
2800
2801 /* Destroy DMA maps for jumbo RX buffers. */
2802 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2803 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2804 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2805 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2806 }
2807 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2808 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2809 sc->bge_cdata.bge_rx_jumbo_sparemap);
2810
2811 /* Destroy DMA maps for TX buffers. */
2812 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2813 if (sc->bge_cdata.bge_tx_dmamap[i])
2814 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2815 sc->bge_cdata.bge_tx_dmamap[i]);
2816 }
2817
2818 if (sc->bge_cdata.bge_rx_mtag)
2819 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2820 if (sc->bge_cdata.bge_mtag_jumbo)
2821 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2822 if (sc->bge_cdata.bge_tx_mtag)
2823 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2824
2825 /* Destroy standard RX ring. */
2826 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2827 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2828 sc->bge_cdata.bge_rx_std_ring_map);
2829 if (sc->bge_ldata.bge_rx_std_ring)
2830 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2831 sc->bge_ldata.bge_rx_std_ring,
2832 sc->bge_cdata.bge_rx_std_ring_map);
2833
2834 if (sc->bge_cdata.bge_rx_std_ring_tag)
2835 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2836
2837 /* Destroy jumbo RX ring. */
2838 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2839 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2840 sc->bge_cdata.bge_rx_jumbo_ring_map);
2841
2842 if (sc->bge_ldata.bge_rx_jumbo_ring)
2843 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2844 sc->bge_ldata.bge_rx_jumbo_ring,
2845 sc->bge_cdata.bge_rx_jumbo_ring_map);
2846
2847 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2848 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2849
2850 /* Destroy RX return ring. */
2851 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2852 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2853 sc->bge_cdata.bge_rx_return_ring_map);
2854
2855 if (sc->bge_ldata.bge_rx_return_ring)
2856 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2857 sc->bge_ldata.bge_rx_return_ring,
2858 sc->bge_cdata.bge_rx_return_ring_map);
2859
2860 if (sc->bge_cdata.bge_rx_return_ring_tag)
2861 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2862
2863 /* Destroy TX ring. */
2864 if (sc->bge_ldata.bge_tx_ring_paddr)
2865 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2866 sc->bge_cdata.bge_tx_ring_map);
2867
2868 if (sc->bge_ldata.bge_tx_ring)
2869 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2870 sc->bge_ldata.bge_tx_ring,
2871 sc->bge_cdata.bge_tx_ring_map);
2872
2873 if (sc->bge_cdata.bge_tx_ring_tag)
2874 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2875
2876 /* Destroy status block. */
2877 if (sc->bge_ldata.bge_status_block_paddr)
2878 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2879 sc->bge_cdata.bge_status_map);
2880
2881 if (sc->bge_ldata.bge_status_block)
2882 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2883 sc->bge_ldata.bge_status_block,
2884 sc->bge_cdata.bge_status_map);
2885
2886 if (sc->bge_cdata.bge_status_tag)
2887 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2888
2889 /* Destroy statistics block. */
2890 if (sc->bge_ldata.bge_stats_paddr)
2891 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2892 sc->bge_cdata.bge_stats_map);
2893
2894 if (sc->bge_ldata.bge_stats)
2895 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2896 sc->bge_ldata.bge_stats,
2897 sc->bge_cdata.bge_stats_map);
2898
2899 if (sc->bge_cdata.bge_stats_tag)
2900 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2901
2902 if (sc->bge_cdata.bge_buffer_tag)
2903 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2904
2905 /* Destroy the parent tag. */
2906 if (sc->bge_cdata.bge_parent_tag)
2907 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2908 }
2909
2910 static int
bge_dma_ring_alloc(struct bge_softc * sc,bus_size_t alignment,bus_size_t maxsize,bus_dma_tag_t * tag,uint8_t ** ring,bus_dmamap_t * map,bus_addr_t * paddr,const char * msg)2911 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2912 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2913 bus_addr_t *paddr, const char *msg)
2914 {
2915 struct bge_dmamap_arg ctx;
2916 int error;
2917
2918 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2919 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2920 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2921 if (error != 0) {
2922 device_printf(sc->bge_dev,
2923 "could not create %s dma tag\n", msg);
2924 return (ENOMEM);
2925 }
2926 /* Allocate DMA'able memory for ring. */
2927 error = bus_dmamem_alloc(*tag, (void **)ring,
2928 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2929 if (error != 0) {
2930 device_printf(sc->bge_dev,
2931 "could not allocate DMA'able memory for %s\n", msg);
2932 return (ENOMEM);
2933 }
2934 /* Load the address of the ring. */
2935 ctx.bge_busaddr = 0;
2936 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2937 &ctx, BUS_DMA_NOWAIT);
2938 if (error != 0) {
2939 device_printf(sc->bge_dev,
2940 "could not load DMA'able memory for %s\n", msg);
2941 return (ENOMEM);
2942 }
2943 *paddr = ctx.bge_busaddr;
2944 return (0);
2945 }
2946
2947 static int
bge_dma_alloc(struct bge_softc * sc)2948 bge_dma_alloc(struct bge_softc *sc)
2949 {
2950 bus_addr_t lowaddr;
2951 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2952 int i, error;
2953
2954 lowaddr = BUS_SPACE_MAXADDR;
2955 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2956 lowaddr = BGE_DMA_MAXADDR;
2957 /*
2958 * Allocate the parent bus DMA tag appropriate for PCI.
2959 */
2960 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2961 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2962 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2963 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2964 if (error != 0) {
2965 device_printf(sc->bge_dev,
2966 "could not allocate parent dma tag\n");
2967 return (ENOMEM);
2968 }
2969
2970 /* Create tag for standard RX ring. */
2971 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2972 &sc->bge_cdata.bge_rx_std_ring_tag,
2973 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2974 &sc->bge_cdata.bge_rx_std_ring_map,
2975 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2976 if (error)
2977 return (error);
2978
2979 /* Create tag for RX return ring. */
2980 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2981 &sc->bge_cdata.bge_rx_return_ring_tag,
2982 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2983 &sc->bge_cdata.bge_rx_return_ring_map,
2984 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2985 if (error)
2986 return (error);
2987
2988 /* Create tag for TX ring. */
2989 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2990 &sc->bge_cdata.bge_tx_ring_tag,
2991 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2992 &sc->bge_cdata.bge_tx_ring_map,
2993 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2994 if (error)
2995 return (error);
2996
2997 /*
2998 * Create tag for status block.
2999 * Because we only use single Tx/Rx/Rx return ring, use
3000 * minimum status block size except BCM5700 AX/BX which
3001 * seems to want to see full status block size regardless
3002 * of configured number of ring.
3003 */
3004 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3005 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3006 sbsz = BGE_STATUS_BLK_SZ;
3007 else
3008 sbsz = 32;
3009 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3010 &sc->bge_cdata.bge_status_tag,
3011 (uint8_t **)&sc->bge_ldata.bge_status_block,
3012 &sc->bge_cdata.bge_status_map,
3013 &sc->bge_ldata.bge_status_block_paddr, "status block");
3014 if (error)
3015 return (error);
3016
3017 /* Create tag for statistics block. */
3018 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3019 &sc->bge_cdata.bge_stats_tag,
3020 (uint8_t **)&sc->bge_ldata.bge_stats,
3021 &sc->bge_cdata.bge_stats_map,
3022 &sc->bge_ldata.bge_stats_paddr, "statistics block");
3023 if (error)
3024 return (error);
3025
3026 /* Create tag for jumbo RX ring. */
3027 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3028 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3029 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3030 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3031 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3032 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3033 if (error)
3034 return (error);
3035 }
3036
3037 /* Create parent tag for buffers. */
3038 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3039 /*
3040 * XXX
3041 * watchdog timeout issue was observed on BCM5704 which
3042 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3043 * Both limiting DMA address space to 32bits and flushing
3044 * mailbox write seem to address the issue.
3045 */
3046 if (sc->bge_pcixcap != 0)
3047 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3048 }
3049 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3050 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3051 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3052 &sc->bge_cdata.bge_buffer_tag);
3053 if (error != 0) {
3054 device_printf(sc->bge_dev,
3055 "could not allocate buffer dma tag\n");
3056 return (ENOMEM);
3057 }
3058 /* Create tag for Tx mbufs. */
3059 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3060 txsegsz = BGE_TSOSEG_SZ;
3061 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3062 } else {
3063 txsegsz = MCLBYTES;
3064 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3065 }
3066 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3067 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3068 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3069 &sc->bge_cdata.bge_tx_mtag);
3070
3071 if (error) {
3072 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3073 return (ENOMEM);
3074 }
3075
3076 /* Create tag for Rx mbufs. */
3077 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3078 rxmaxsegsz = MJUM9BYTES;
3079 else
3080 rxmaxsegsz = MCLBYTES;
3081 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3082 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3083 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3084
3085 if (error) {
3086 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3087 return (ENOMEM);
3088 }
3089
3090 /* Create DMA maps for RX buffers. */
3091 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3092 &sc->bge_cdata.bge_rx_std_sparemap);
3093 if (error) {
3094 device_printf(sc->bge_dev,
3095 "can't create spare DMA map for RX\n");
3096 return (ENOMEM);
3097 }
3098 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3099 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3100 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3101 if (error) {
3102 device_printf(sc->bge_dev,
3103 "can't create DMA map for RX\n");
3104 return (ENOMEM);
3105 }
3106 }
3107
3108 /* Create DMA maps for TX buffers. */
3109 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3110 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3111 &sc->bge_cdata.bge_tx_dmamap[i]);
3112 if (error) {
3113 device_printf(sc->bge_dev,
3114 "can't create DMA map for TX\n");
3115 return (ENOMEM);
3116 }
3117 }
3118
3119 /* Create tags for jumbo RX buffers. */
3120 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3121 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3122 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3123 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3124 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3125 if (error) {
3126 device_printf(sc->bge_dev,
3127 "could not allocate jumbo dma tag\n");
3128 return (ENOMEM);
3129 }
3130 /* Create DMA maps for jumbo RX buffers. */
3131 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3132 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3133 if (error) {
3134 device_printf(sc->bge_dev,
3135 "can't create spare DMA map for jumbo RX\n");
3136 return (ENOMEM);
3137 }
3138 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3139 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3140 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3141 if (error) {
3142 device_printf(sc->bge_dev,
3143 "can't create DMA map for jumbo RX\n");
3144 return (ENOMEM);
3145 }
3146 }
3147 }
3148
3149 return (0);
3150 }
3151
3152 /*
3153 * Return true if this device has more than one port.
3154 */
3155 static int
bge_has_multiple_ports(struct bge_softc * sc)3156 bge_has_multiple_ports(struct bge_softc *sc)
3157 {
3158 device_t dev = sc->bge_dev;
3159 u_int b, d, f, fscan, s;
3160
3161 d = pci_get_domain(dev);
3162 b = pci_get_bus(dev);
3163 s = pci_get_slot(dev);
3164 f = pci_get_function(dev);
3165 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3166 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3167 return (1);
3168 return (0);
3169 }
3170
3171 /*
3172 * Return true if MSI can be used with this device.
3173 */
3174 static int
bge_can_use_msi(struct bge_softc * sc)3175 bge_can_use_msi(struct bge_softc *sc)
3176 {
3177 int can_use_msi = 0;
3178
3179 if (sc->bge_msi == 0)
3180 return (0);
3181
3182 /* Disable MSI for polling(4). */
3183 #ifdef DEVICE_POLLING
3184 return (0);
3185 #endif
3186 switch (sc->bge_asicrev) {
3187 case BGE_ASICREV_BCM5714_A0:
3188 case BGE_ASICREV_BCM5714:
3189 /*
3190 * Apparently, MSI doesn't work when these chips are
3191 * configured in single-port mode.
3192 */
3193 if (bge_has_multiple_ports(sc))
3194 can_use_msi = 1;
3195 break;
3196 case BGE_ASICREV_BCM5750:
3197 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3198 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3199 can_use_msi = 1;
3200 break;
3201 default:
3202 if (BGE_IS_575X_PLUS(sc))
3203 can_use_msi = 1;
3204 }
3205 return (can_use_msi);
3206 }
3207
3208 static int
bge_mbox_reorder(struct bge_softc * sc)3209 bge_mbox_reorder(struct bge_softc *sc)
3210 {
3211 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3212 static const struct mbox_reorder {
3213 const uint16_t vendor;
3214 const uint16_t device;
3215 const char *desc;
3216 } mbox_reorder_lists[] = {
3217 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3218 };
3219 devclass_t pci, pcib;
3220 device_t bus, dev;
3221 int i;
3222
3223 pci = devclass_find("pci");
3224 pcib = devclass_find("pcib");
3225 dev = sc->bge_dev;
3226 bus = device_get_parent(dev);
3227 for (;;) {
3228 dev = device_get_parent(bus);
3229 bus = device_get_parent(dev);
3230 if (device_get_devclass(dev) != pcib)
3231 break;
3232 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3233 if (pci_get_vendor(dev) ==
3234 mbox_reorder_lists[i].vendor &&
3235 pci_get_device(dev) ==
3236 mbox_reorder_lists[i].device) {
3237 device_printf(sc->bge_dev,
3238 "enabling MBOX workaround for %s\n",
3239 mbox_reorder_lists[i].desc);
3240 return (1);
3241 }
3242 }
3243 if (device_get_devclass(bus) != pci)
3244 break;
3245 }
3246 return (0);
3247 }
3248
3249 static void
bge_devinfo(struct bge_softc * sc)3250 bge_devinfo(struct bge_softc *sc)
3251 {
3252 uint32_t cfg, clk;
3253
3254 device_printf(sc->bge_dev,
3255 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3256 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3257 if (sc->bge_flags & BGE_FLAG_PCIE)
3258 printf("PCI-E\n");
3259 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3260 printf("PCI-X ");
3261 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3262 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3263 clk = 133;
3264 else {
3265 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3266 switch (clk) {
3267 case 0:
3268 clk = 33;
3269 break;
3270 case 2:
3271 clk = 50;
3272 break;
3273 case 4:
3274 clk = 66;
3275 break;
3276 case 6:
3277 clk = 100;
3278 break;
3279 case 7:
3280 clk = 133;
3281 break;
3282 }
3283 }
3284 printf("%u MHz\n", clk);
3285 } else {
3286 if (sc->bge_pcixcap != 0)
3287 printf("PCI on PCI-X ");
3288 else
3289 printf("PCI ");
3290 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3291 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3292 clk = 66;
3293 else
3294 clk = 33;
3295 if (cfg & BGE_PCISTATE_32BIT_BUS)
3296 printf("%u MHz; 32bit\n", clk);
3297 else
3298 printf("%u MHz; 64bit\n", clk);
3299 }
3300 }
3301
3302 static int
bge_attach(device_t dev)3303 bge_attach(device_t dev)
3304 {
3305 if_t ifp;
3306 struct bge_softc *sc;
3307 uint32_t hwcfg = 0, misccfg, pcistate;
3308 u_char eaddr[ETHER_ADDR_LEN];
3309 int capmask, error, reg, rid, trys;
3310
3311 sc = device_get_softc(dev);
3312 sc->bge_dev = dev;
3313
3314 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3315 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3316 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3317
3318 pci_enable_busmaster(dev);
3319
3320 /*
3321 * Allocate control/status registers.
3322 */
3323 rid = PCIR_BAR(0);
3324 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3325 RF_ACTIVE);
3326
3327 if (sc->bge_res == NULL) {
3328 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3329 error = ENXIO;
3330 goto fail;
3331 }
3332
3333 /* Save various chip information. */
3334 sc->bge_func_addr = pci_get_function(dev);
3335 sc->bge_chipid = bge_chipid(dev);
3336 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3337 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3338
3339 /* Set default PHY address. */
3340 sc->bge_phy_addr = 1;
3341 /*
3342 * PHY address mapping for various devices.
3343 *
3344 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3345 * ---------+-------+-------+-------+-------+
3346 * BCM57XX | 1 | X | X | X |
3347 * BCM5704 | 1 | X | 1 | X |
3348 * BCM5717 | 1 | 8 | 2 | 9 |
3349 * BCM5719 | 1 | 8 | 2 | 9 |
3350 * BCM5720 | 1 | 8 | 2 | 9 |
3351 *
3352 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3353 * ---------+-------+-------+-------+-------+
3354 * BCM57XX | X | X | X | X |
3355 * BCM5704 | X | X | X | X |
3356 * BCM5717 | X | X | X | X |
3357 * BCM5719 | 3 | 10 | 4 | 11 |
3358 * BCM5720 | X | X | X | X |
3359 *
3360 * Other addresses may respond but they are not
3361 * IEEE compliant PHYs and should be ignored.
3362 */
3363 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3364 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3365 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3366 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3367 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3368 BGE_SGDIGSTS_IS_SERDES)
3369 sc->bge_phy_addr = sc->bge_func_addr + 8;
3370 else
3371 sc->bge_phy_addr = sc->bge_func_addr + 1;
3372 } else {
3373 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3374 BGE_CPMU_PHY_STRAP_IS_SERDES)
3375 sc->bge_phy_addr = sc->bge_func_addr + 8;
3376 else
3377 sc->bge_phy_addr = sc->bge_func_addr + 1;
3378 }
3379 }
3380
3381 if (bge_has_eaddr(sc))
3382 sc->bge_flags |= BGE_FLAG_EADDR;
3383
3384 /* Save chipset family. */
3385 switch (sc->bge_asicrev) {
3386 case BGE_ASICREV_BCM5762:
3387 case BGE_ASICREV_BCM57765:
3388 case BGE_ASICREV_BCM57766:
3389 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3390 /* FALLTHROUGH */
3391 case BGE_ASICREV_BCM5717:
3392 case BGE_ASICREV_BCM5719:
3393 case BGE_ASICREV_BCM5720:
3394 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3395 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3396 BGE_FLAG_JUMBO_FRAME;
3397 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3398 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3399 /*
3400 * Enable work around for DMA engine miscalculation
3401 * of TXMBUF available space.
3402 */
3403 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3404 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3405 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3406 /* Jumbo frame on BCM5719 A0 does not work. */
3407 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3408 }
3409 }
3410 break;
3411 case BGE_ASICREV_BCM5755:
3412 case BGE_ASICREV_BCM5761:
3413 case BGE_ASICREV_BCM5784:
3414 case BGE_ASICREV_BCM5785:
3415 case BGE_ASICREV_BCM5787:
3416 case BGE_ASICREV_BCM57780:
3417 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3418 BGE_FLAG_5705_PLUS;
3419 break;
3420 case BGE_ASICREV_BCM5700:
3421 case BGE_ASICREV_BCM5701:
3422 case BGE_ASICREV_BCM5703:
3423 case BGE_ASICREV_BCM5704:
3424 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3425 break;
3426 case BGE_ASICREV_BCM5714_A0:
3427 case BGE_ASICREV_BCM5780:
3428 case BGE_ASICREV_BCM5714:
3429 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3430 /* FALLTHROUGH */
3431 case BGE_ASICREV_BCM5750:
3432 case BGE_ASICREV_BCM5752:
3433 case BGE_ASICREV_BCM5906:
3434 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3435 /* FALLTHROUGH */
3436 case BGE_ASICREV_BCM5705:
3437 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3438 break;
3439 }
3440
3441 /* Identify chips with APE processor. */
3442 switch (sc->bge_asicrev) {
3443 case BGE_ASICREV_BCM5717:
3444 case BGE_ASICREV_BCM5719:
3445 case BGE_ASICREV_BCM5720:
3446 case BGE_ASICREV_BCM5761:
3447 case BGE_ASICREV_BCM5762:
3448 sc->bge_flags |= BGE_FLAG_APE;
3449 break;
3450 }
3451
3452 /* Chips with APE need BAR2 access for APE registers/memory. */
3453 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3454 rid = PCIR_BAR(2);
3455 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3456 RF_ACTIVE);
3457 if (sc->bge_res2 == NULL) {
3458 device_printf (sc->bge_dev,
3459 "couldn't map BAR2 memory\n");
3460 error = ENXIO;
3461 goto fail;
3462 }
3463
3464 /* Enable APE register/memory access by host driver. */
3465 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3466 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3467 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3468 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3469 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3470
3471 bge_ape_lock_init(sc);
3472 bge_ape_read_fw_ver(sc);
3473 }
3474
3475 /* Add SYSCTLs, requires the chipset family to be set. */
3476 bge_add_sysctls(sc);
3477
3478 /* Identify the chips that use an CPMU. */
3479 if (BGE_IS_5717_PLUS(sc) ||
3480 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3481 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3482 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3483 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3484 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3485 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3486 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3487 else
3488 sc->bge_mi_mode = BGE_MIMODE_BASE;
3489 /* Enable auto polling for BCM570[0-5]. */
3490 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3491 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3492
3493 /*
3494 * All Broadcom controllers have 4GB boundary DMA bug.
3495 * Whenever an address crosses a multiple of the 4GB boundary
3496 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3497 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3498 * state machine will lockup and cause the device to hang.
3499 */
3500 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3501
3502 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3503 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3504 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3505
3506 /*
3507 * BCM5719 cannot handle DMA requests for DMA segments that
3508 * have larger than 4KB in size. However the maximum DMA
3509 * segment size created in DMA tag is 4KB for TSO, so we
3510 * wouldn't encounter the issue here.
3511 */
3512 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3513 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3514
3515 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3516 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3517 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3518 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3519 sc->bge_flags |= BGE_FLAG_5788;
3520 }
3521
3522 capmask = BMSR_DEFCAPMASK;
3523 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3524 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3525 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3526 pci_get_vendor(dev) == BCOM_VENDORID &&
3527 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3528 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3529 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3530 (pci_get_vendor(dev) == BCOM_VENDORID &&
3531 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3532 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3533 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3534 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3535 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3536 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3537 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3538 /* These chips are 10/100 only. */
3539 capmask &= ~BMSR_EXTSTAT;
3540 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3541 }
3542
3543 /*
3544 * Some controllers seem to require a special firmware to use
3545 * TSO. But the firmware is not available to FreeBSD and Linux
3546 * claims that the TSO performed by the firmware is slower than
3547 * hardware based TSO. Moreover the firmware based TSO has one
3548 * known bug which can't handle TSO if Ethernet header + IP/TCP
3549 * header is greater than 80 bytes. A workaround for the TSO
3550 * bug exist but it seems it's too expensive than not using
3551 * TSO at all. Some hardwares also have the TSO bug so limit
3552 * the TSO to the controllers that are not affected TSO issues
3553 * (e.g. 5755 or higher).
3554 */
3555 if (BGE_IS_5717_PLUS(sc)) {
3556 /* BCM5717 requires different TSO configuration. */
3557 sc->bge_flags |= BGE_FLAG_TSO3;
3558 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3559 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3560 /* TSO on BCM5719 A0 does not work. */
3561 sc->bge_flags &= ~BGE_FLAG_TSO3;
3562 }
3563 } else if (BGE_IS_5755_PLUS(sc)) {
3564 /*
3565 * BCM5754 and BCM5787 shares the same ASIC id so
3566 * explicit device id check is required.
3567 * Due to unknown reason TSO does not work on BCM5755M.
3568 */
3569 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3570 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3571 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3572 sc->bge_flags |= BGE_FLAG_TSO;
3573 }
3574
3575 /*
3576 * Check if this is a PCI-X or PCI Express device.
3577 */
3578 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3579 /*
3580 * Found a PCI Express capabilities register, this
3581 * must be a PCI Express device.
3582 */
3583 sc->bge_flags |= BGE_FLAG_PCIE;
3584 sc->bge_expcap = reg;
3585 /* Extract supported maximum payload size. */
3586 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3587 PCIER_DEVICE_CAP, 2);
3588 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3589 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3590 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3591 sc->bge_expmrq = 2048;
3592 else
3593 sc->bge_expmrq = 4096;
3594 pci_set_max_read_req(dev, sc->bge_expmrq);
3595 } else {
3596 /*
3597 * Check if the device is in PCI-X Mode.
3598 * (This bit is not valid on PCI Express controllers.)
3599 */
3600 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3601 sc->bge_pcixcap = reg;
3602 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3603 BGE_PCISTATE_PCI_BUSMODE) == 0)
3604 sc->bge_flags |= BGE_FLAG_PCIX;
3605 }
3606
3607 /*
3608 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3609 * not actually a MAC controller bug but an issue with the embedded
3610 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3611 */
3612 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3613 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3614 /*
3615 * Some PCI-X bridges are known to trigger write reordering to
3616 * the mailbox registers. Typical phenomena is watchdog timeouts
3617 * caused by out-of-order TX completions. Enable workaround for
3618 * PCI-X devices that live behind these bridges.
3619 * Note, PCI-X controllers can run in PCI mode so we can't use
3620 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3621 */
3622 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3623 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3624 /*
3625 * Allocate the interrupt, using MSI if possible. These devices
3626 * support 8 MSI messages, but only the first one is used in
3627 * normal operation.
3628 */
3629 rid = 0;
3630 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3631 sc->bge_msicap = reg;
3632 reg = 1;
3633 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3634 rid = 1;
3635 sc->bge_flags |= BGE_FLAG_MSI;
3636 }
3637 }
3638
3639 /*
3640 * All controllers except BCM5700 supports tagged status but
3641 * we use tagged status only for MSI case on BCM5717. Otherwise
3642 * MSI on BCM5717 does not work.
3643 */
3644 #ifndef DEVICE_POLLING
3645 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3646 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3647 #endif
3648
3649 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3650 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3651
3652 if (sc->bge_irq == NULL) {
3653 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3654 error = ENXIO;
3655 goto fail;
3656 }
3657
3658 bge_devinfo(sc);
3659
3660 sc->bge_asf_mode = 0;
3661 /* No ASF if APE present. */
3662 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3663 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3664 BGE_SRAM_DATA_SIG_MAGIC)) {
3665 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3666 BGE_HWCFG_ASF) {
3667 sc->bge_asf_mode |= ASF_ENABLE;
3668 sc->bge_asf_mode |= ASF_STACKUP;
3669 if (BGE_IS_575X_PLUS(sc))
3670 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3671 }
3672 }
3673 }
3674
3675 bge_stop_fw(sc);
3676 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3677 if (bge_reset(sc)) {
3678 device_printf(sc->bge_dev, "chip reset failed\n");
3679 error = ENXIO;
3680 goto fail;
3681 }
3682
3683 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3684 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3685
3686 if (bge_chipinit(sc)) {
3687 device_printf(sc->bge_dev, "chip initialization failed\n");
3688 error = ENXIO;
3689 goto fail;
3690 }
3691
3692 error = bge_get_eaddr(sc, eaddr);
3693 if (error) {
3694 device_printf(sc->bge_dev,
3695 "failed to read station address\n");
3696 error = ENXIO;
3697 goto fail;
3698 }
3699
3700 /* 5705 limits RX return ring to 512 entries. */
3701 if (BGE_IS_5717_PLUS(sc))
3702 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3703 else if (BGE_IS_5705_PLUS(sc))
3704 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3705 else
3706 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3707
3708 if (bge_dma_alloc(sc)) {
3709 device_printf(sc->bge_dev,
3710 "failed to allocate DMA resources\n");
3711 error = ENXIO;
3712 goto fail;
3713 }
3714
3715 /* Set default tuneable values. */
3716 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3717 sc->bge_rx_coal_ticks = 150;
3718 sc->bge_tx_coal_ticks = 150;
3719 sc->bge_rx_max_coal_bds = 10;
3720 sc->bge_tx_max_coal_bds = 10;
3721
3722 /* Initialize checksum features to use. */
3723 sc->bge_csum_features = BGE_CSUM_FEATURES;
3724 if (sc->bge_forced_udpcsum != 0)
3725 sc->bge_csum_features |= CSUM_UDP;
3726
3727 /* Set up ifnet structure */
3728 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3729 if (ifp == NULL) {
3730 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3731 error = ENXIO;
3732 goto fail;
3733 }
3734 if_setsoftc(ifp, sc);
3735 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3736 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3737 if_setioctlfn(ifp, bge_ioctl);
3738 if_setstartfn(ifp, bge_start);
3739 if_setinitfn(ifp, bge_init);
3740 if_setgetcounterfn(ifp, bge_get_counter);
3741 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3742 if_setsendqready(ifp);
3743 if_sethwassist(ifp, sc->bge_csum_features);
3744 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3745 IFCAP_VLAN_MTU);
3746 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3747 if_sethwassistbits(ifp, CSUM_TSO, 0);
3748 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3749 }
3750 #ifdef IFCAP_VLAN_HWCSUM
3751 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3752 #endif
3753 if_setcapenable(ifp, if_getcapabilities(ifp));
3754 #ifdef DEVICE_POLLING
3755 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3756 #endif
3757
3758 /*
3759 * 5700 B0 chips do not support checksumming correctly due
3760 * to hardware bugs.
3761 */
3762 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3763 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3764 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3765 if_sethwassist(ifp, 0);
3766 }
3767
3768 /*
3769 * Figure out what sort of media we have by checking the
3770 * hardware config word in the first 32k of NIC internal memory,
3771 * or fall back to examining the EEPROM if necessary.
3772 * Note: on some BCM5700 cards, this value appears to be unset.
3773 * If that's the case, we have to rely on identifying the NIC
3774 * by its PCI subsystem ID, as we do below for the SysKonnect
3775 * SK-9D41.
3776 */
3777 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3778 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3779 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3780 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3781 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3782 sizeof(hwcfg))) {
3783 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3784 error = ENXIO;
3785 goto fail;
3786 }
3787 hwcfg = ntohl(hwcfg);
3788 }
3789
3790 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3791 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3792 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3793 if (BGE_IS_5705_PLUS(sc)) {
3794 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3795 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3796 } else
3797 sc->bge_flags |= BGE_FLAG_TBI;
3798 }
3799
3800 /* Set various PHY bug flags. */
3801 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3802 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3803 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3804 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3805 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3806 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3807 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3808 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3809 if (pci_get_subvendor(dev) == DELL_VENDORID)
3810 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3811 if ((BGE_IS_5705_PLUS(sc)) &&
3812 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3813 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3814 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3815 !BGE_IS_5717_PLUS(sc)) {
3816 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3817 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3818 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3819 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3820 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3821 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3822 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3823 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3824 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3825 } else
3826 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3827 }
3828
3829 /*
3830 * Don't enable Ethernet@WireSpeed for the 5700 or the
3831 * 5705 A0 and A1 chips.
3832 */
3833 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3834 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3835 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3836 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3837 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3838
3839 if (sc->bge_flags & BGE_FLAG_TBI) {
3840 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3841 bge_ifmedia_sts);
3842 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3843 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3844 0, NULL);
3845 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3846 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3847 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3848 } else {
3849 /*
3850 * Do transceiver setup and tell the firmware the
3851 * driver is down so we can try to get access the
3852 * probe if ASF is running. Retry a couple of times
3853 * if we get a conflict with the ASF firmware accessing
3854 * the PHY.
3855 */
3856 trys = 0;
3857 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3858 again:
3859 bge_asf_driver_up(sc);
3860
3861 error = mii_attach(dev, &sc->bge_miibus, ifp,
3862 (ifm_change_cb_t)bge_ifmedia_upd,
3863 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3864 MII_OFFSET_ANY, MIIF_DOPAUSE);
3865 if (error != 0) {
3866 if (trys++ < 4) {
3867 device_printf(sc->bge_dev, "Try again\n");
3868 bge_miibus_writereg(sc->bge_dev,
3869 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3870 goto again;
3871 }
3872 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3873 goto fail;
3874 }
3875
3876 /*
3877 * Now tell the firmware we are going up after probing the PHY
3878 */
3879 if (sc->bge_asf_mode & ASF_STACKUP)
3880 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3881 }
3882
3883 /*
3884 * When using the BCM5701 in PCI-X mode, data corruption has
3885 * been observed in the first few bytes of some received packets.
3886 * Aligning the packet buffer in memory eliminates the corruption.
3887 * Unfortunately, this misaligns the packet payloads. On platforms
3888 * which do not support unaligned accesses, we will realign the
3889 * payloads by copying the received packets.
3890 */
3891 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3892 sc->bge_flags & BGE_FLAG_PCIX)
3893 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3894
3895 /*
3896 * Call MI attach routine.
3897 */
3898 ether_ifattach(ifp, eaddr);
3899
3900 /* Tell upper layer we support long frames. */
3901 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3902
3903 /*
3904 * Hookup IRQ last.
3905 */
3906 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3907 /* Take advantage of single-shot MSI. */
3908 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3909 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3910 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3911 taskqueue_thread_enqueue, &sc->bge_tq);
3912 if (sc->bge_tq == NULL) {
3913 device_printf(dev, "could not create taskqueue.\n");
3914 ether_ifdetach(ifp);
3915 error = ENOMEM;
3916 goto fail;
3917 }
3918 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3919 "%s taskq", device_get_nameunit(sc->bge_dev));
3920 if (error != 0) {
3921 device_printf(dev, "could not start threads.\n");
3922 ether_ifdetach(ifp);
3923 goto fail;
3924 }
3925 error = bus_setup_intr(dev, sc->bge_irq,
3926 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3927 &sc->bge_intrhand);
3928 } else
3929 error = bus_setup_intr(dev, sc->bge_irq,
3930 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3931 &sc->bge_intrhand);
3932
3933 if (error) {
3934 ether_ifdetach(ifp);
3935 device_printf(sc->bge_dev, "couldn't set up irq\n");
3936 }
3937
3938 fail:
3939 if (error)
3940 bge_detach(dev);
3941 return (error);
3942 }
3943
3944 static int
bge_detach(device_t dev)3945 bge_detach(device_t dev)
3946 {
3947 struct bge_softc *sc;
3948 if_t ifp;
3949
3950 sc = device_get_softc(dev);
3951 ifp = sc->bge_ifp;
3952
3953 #ifdef DEVICE_POLLING
3954 if (if_getcapenable(ifp) & IFCAP_POLLING)
3955 ether_poll_deregister(ifp);
3956 #endif
3957
3958 if (device_is_attached(dev)) {
3959 ether_ifdetach(ifp);
3960 BGE_LOCK(sc);
3961 bge_stop(sc);
3962 BGE_UNLOCK(sc);
3963 callout_drain(&sc->bge_stat_ch);
3964 }
3965
3966 if (sc->bge_tq)
3967 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3968
3969 if (sc->bge_flags & BGE_FLAG_TBI)
3970 ifmedia_removeall(&sc->bge_ifmedia);
3971 else if (sc->bge_miibus != NULL) {
3972 bus_generic_detach(dev);
3973 device_delete_child(dev, sc->bge_miibus);
3974 }
3975
3976 bge_release_resources(sc);
3977
3978 return (0);
3979 }
3980
3981 static void
bge_release_resources(struct bge_softc * sc)3982 bge_release_resources(struct bge_softc *sc)
3983 {
3984 device_t dev;
3985
3986 dev = sc->bge_dev;
3987
3988 if (sc->bge_tq != NULL)
3989 taskqueue_free(sc->bge_tq);
3990
3991 if (sc->bge_intrhand != NULL)
3992 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3993
3994 if (sc->bge_irq != NULL) {
3995 bus_release_resource(dev, SYS_RES_IRQ,
3996 rman_get_rid(sc->bge_irq), sc->bge_irq);
3997 pci_release_msi(dev);
3998 }
3999
4000 if (sc->bge_res != NULL)
4001 bus_release_resource(dev, SYS_RES_MEMORY,
4002 rman_get_rid(sc->bge_res), sc->bge_res);
4003
4004 if (sc->bge_res2 != NULL)
4005 bus_release_resource(dev, SYS_RES_MEMORY,
4006 rman_get_rid(sc->bge_res2), sc->bge_res2);
4007
4008 if (sc->bge_ifp != NULL)
4009 if_free(sc->bge_ifp);
4010
4011 bge_dma_free(sc);
4012
4013 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
4014 BGE_LOCK_DESTROY(sc);
4015 }
4016
4017 static int
bge_reset(struct bge_softc * sc)4018 bge_reset(struct bge_softc *sc)
4019 {
4020 device_t dev;
4021 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4022 void (*write_op)(struct bge_softc *, int, int);
4023 uint16_t devctl;
4024 int i;
4025
4026 dev = sc->bge_dev;
4027
4028 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4029 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4030 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4031 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4032
4033 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4034 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4035 if (sc->bge_flags & BGE_FLAG_PCIE)
4036 write_op = bge_writemem_direct;
4037 else
4038 write_op = bge_writemem_ind;
4039 } else
4040 write_op = bge_writereg_ind;
4041
4042 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4043 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4044 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4045 for (i = 0; i < 8000; i++) {
4046 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4047 BGE_NVRAMSWARB_GNT1)
4048 break;
4049 DELAY(20);
4050 }
4051 if (i == 8000) {
4052 if (bootverbose)
4053 device_printf(dev, "NVRAM lock timedout!\n");
4054 }
4055 }
4056 /* Take APE lock when performing reset. */
4057 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4058
4059 /* Save some important PCI state. */
4060 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4061 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4062
4063 pci_write_config(dev, BGE_PCI_MISC_CTL,
4064 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4065 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4066
4067 /* Disable fastboot on controllers that support it. */
4068 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4069 BGE_IS_5755_PLUS(sc)) {
4070 if (bootverbose)
4071 device_printf(dev, "Disabling fastboot\n");
4072 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4073 }
4074
4075 /*
4076 * Write the magic number to SRAM at offset 0xB50.
4077 * When firmware finishes its initialization it will
4078 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4079 */
4080 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4081
4082 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4083
4084 /* XXX: Broadcom Linux driver. */
4085 if (sc->bge_flags & BGE_FLAG_PCIE) {
4086 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4087 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4088 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4089 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4090 }
4091 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4092 /* Prevent PCIE link training during global reset */
4093 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4094 reset |= 1 << 29;
4095 }
4096 }
4097
4098 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4099 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4100 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4101 val | BGE_VCPU_STATUS_DRV_RESET);
4102 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4103 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4104 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4105 }
4106
4107 /*
4108 * Set GPHY Power Down Override to leave GPHY
4109 * powered up in D0 uninitialized.
4110 */
4111 if (BGE_IS_5705_PLUS(sc) &&
4112 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4113 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4114
4115 /* Issue global reset */
4116 write_op(sc, BGE_MISC_CFG, reset);
4117
4118 if (sc->bge_flags & BGE_FLAG_PCIE)
4119 DELAY(100 * 1000);
4120 else
4121 DELAY(1000);
4122
4123 /* XXX: Broadcom Linux driver. */
4124 if (sc->bge_flags & BGE_FLAG_PCIE) {
4125 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4126 DELAY(500000); /* wait for link training to complete */
4127 val = pci_read_config(dev, 0xC4, 4);
4128 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4129 }
4130 devctl = pci_read_config(dev,
4131 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4132 /* Clear enable no snoop and disable relaxed ordering. */
4133 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4134 PCIEM_CTL_NOSNOOP_ENABLE);
4135 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4136 devctl, 2);
4137 pci_set_max_read_req(dev, sc->bge_expmrq);
4138 /* Clear error status. */
4139 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4140 PCIEM_STA_CORRECTABLE_ERROR |
4141 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4142 PCIEM_STA_UNSUPPORTED_REQ, 2);
4143 }
4144
4145 /* Reset some of the PCI state that got zapped by reset. */
4146 pci_write_config(dev, BGE_PCI_MISC_CTL,
4147 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4148 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4149 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4150 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4151 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4152 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4154 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4155 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4156 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4157 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4158 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4159 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4160 /*
4161 * Disable PCI-X relaxed ordering to ensure status block update
4162 * comes first then packet buffer DMA. Otherwise driver may
4163 * read stale status block.
4164 */
4165 if (sc->bge_flags & BGE_FLAG_PCIX) {
4166 devctl = pci_read_config(dev,
4167 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4168 devctl &= ~PCIXM_COMMAND_ERO;
4169 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4170 devctl &= ~PCIXM_COMMAND_MAX_READ;
4171 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4172 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4173 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4174 PCIXM_COMMAND_MAX_READ);
4175 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4176 }
4177 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4178 devctl, 2);
4179 }
4180 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4181 if (BGE_IS_5714_FAMILY(sc)) {
4182 /* This chip disables MSI on reset. */
4183 if (sc->bge_flags & BGE_FLAG_MSI) {
4184 val = pci_read_config(dev,
4185 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4186 pci_write_config(dev,
4187 sc->bge_msicap + PCIR_MSI_CTRL,
4188 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4189 val = CSR_READ_4(sc, BGE_MSI_MODE);
4190 CSR_WRITE_4(sc, BGE_MSI_MODE,
4191 val | BGE_MSIMODE_ENABLE);
4192 }
4193 val = CSR_READ_4(sc, BGE_MARB_MODE);
4194 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4195 } else
4196 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4197
4198 /* Fix up byte swapping. */
4199 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4200
4201 val = CSR_READ_4(sc, BGE_MAC_MODE);
4202 val = (val & ~mac_mode_mask) | mac_mode;
4203 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4204 DELAY(40);
4205
4206 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4207
4208 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4209 for (i = 0; i < BGE_TIMEOUT; i++) {
4210 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4211 if (val & BGE_VCPU_STATUS_INIT_DONE)
4212 break;
4213 DELAY(100);
4214 }
4215 if (i == BGE_TIMEOUT) {
4216 device_printf(dev, "reset timed out\n");
4217 return (1);
4218 }
4219 } else {
4220 /*
4221 * Poll until we see the 1's complement of the magic number.
4222 * This indicates that the firmware initialization is complete.
4223 * We expect this to fail if no chip containing the Ethernet
4224 * address is fitted though.
4225 */
4226 for (i = 0; i < BGE_TIMEOUT; i++) {
4227 DELAY(10);
4228 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4229 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4230 break;
4231 }
4232
4233 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4234 device_printf(dev,
4235 "firmware handshake timed out, found 0x%08x\n",
4236 val);
4237 /* BCM57765 A0 needs additional time before accessing. */
4238 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4239 DELAY(10 * 1000); /* XXX */
4240 }
4241
4242 /*
4243 * The 5704 in TBI mode apparently needs some special
4244 * adjustment to insure the SERDES drive level is set
4245 * to 1.2V.
4246 */
4247 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4248 sc->bge_flags & BGE_FLAG_TBI) {
4249 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4250 val = (val & ~0xFFF) | 0x880;
4251 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4252 }
4253
4254 /* XXX: Broadcom Linux driver. */
4255 if (sc->bge_flags & BGE_FLAG_PCIE &&
4256 !BGE_IS_5717_PLUS(sc) &&
4257 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4258 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4259 /* Enable Data FIFO protection. */
4260 val = CSR_READ_4(sc, 0x7C00);
4261 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4262 }
4263
4264 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4265 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4266 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4267
4268 return (0);
4269 }
4270
4271 static __inline void
bge_rxreuse_std(struct bge_softc * sc,int i)4272 bge_rxreuse_std(struct bge_softc *sc, int i)
4273 {
4274 struct bge_rx_bd *r;
4275
4276 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4277 r->bge_flags = BGE_RXBDFLAG_END;
4278 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4279 r->bge_idx = i;
4280 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4281 }
4282
4283 static __inline void
bge_rxreuse_jumbo(struct bge_softc * sc,int i)4284 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4285 {
4286 struct bge_extrx_bd *r;
4287
4288 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4289 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4290 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4291 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4292 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4293 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4294 r->bge_idx = i;
4295 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4296 }
4297
4298 /*
4299 * Frame reception handling. This is called if there's a frame
4300 * on the receive return list.
4301 *
4302 * Note: we have to be able to handle two possibilities here:
4303 * 1) the frame is from the jumbo receive ring
4304 * 2) the frame is from the standard receive ring
4305 */
4306
4307 static int
bge_rxeof(struct bge_softc * sc,uint16_t rx_prod,int holdlck)4308 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4309 {
4310 if_t ifp;
4311 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4312 uint16_t rx_cons;
4313
4314 rx_cons = sc->bge_rx_saved_considx;
4315
4316 /* Nothing to do. */
4317 if (rx_cons == rx_prod)
4318 return (rx_npkts);
4319
4320 ifp = sc->bge_ifp;
4321
4322 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4323 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4324 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4325 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4326 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4327 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4328 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4329 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4330 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4331
4332 while (rx_cons != rx_prod) {
4333 struct bge_rx_bd *cur_rx;
4334 uint32_t rxidx;
4335 struct mbuf *m = NULL;
4336 uint16_t vlan_tag = 0;
4337 int have_tag = 0;
4338
4339 #ifdef DEVICE_POLLING
4340 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4341 if (sc->rxcycles <= 0)
4342 break;
4343 sc->rxcycles--;
4344 }
4345 #endif
4346
4347 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4348
4349 rxidx = cur_rx->bge_idx;
4350 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4351
4352 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4353 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4354 have_tag = 1;
4355 vlan_tag = cur_rx->bge_vlan_tag;
4356 }
4357
4358 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4359 jumbocnt++;
4360 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4361 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4362 bge_rxreuse_jumbo(sc, rxidx);
4363 continue;
4364 }
4365 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4366 bge_rxreuse_jumbo(sc, rxidx);
4367 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4368 continue;
4369 }
4370 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4371 } else {
4372 stdcnt++;
4373 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4374 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4375 bge_rxreuse_std(sc, rxidx);
4376 continue;
4377 }
4378 if (bge_newbuf_std(sc, rxidx) != 0) {
4379 bge_rxreuse_std(sc, rxidx);
4380 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4381 continue;
4382 }
4383 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4384 }
4385
4386 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4387 #ifndef __NO_STRICT_ALIGNMENT
4388 /*
4389 * For architectures with strict alignment we must make sure
4390 * the payload is aligned.
4391 */
4392 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4393 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4394 cur_rx->bge_len);
4395 m->m_data += ETHER_ALIGN;
4396 }
4397 #endif
4398 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4399 m->m_pkthdr.rcvif = ifp;
4400
4401 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4402 bge_rxcsum(sc, cur_rx, m);
4403
4404 /*
4405 * If we received a packet with a vlan tag,
4406 * attach that information to the packet.
4407 */
4408 if (have_tag) {
4409 m->m_pkthdr.ether_vtag = vlan_tag;
4410 m->m_flags |= M_VLANTAG;
4411 }
4412
4413 if (holdlck != 0) {
4414 BGE_UNLOCK(sc);
4415 if_input(ifp, m);
4416 BGE_LOCK(sc);
4417 } else
4418 if_input(ifp, m);
4419 rx_npkts++;
4420
4421 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4422 return (rx_npkts);
4423 }
4424
4425 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4426 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4427 if (stdcnt > 0)
4428 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4429 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4430
4431 if (jumbocnt > 0)
4432 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4433 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4434
4435 sc->bge_rx_saved_considx = rx_cons;
4436 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4437 if (stdcnt)
4438 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4439 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4440 if (jumbocnt)
4441 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4442 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4443 #ifdef notyet
4444 /*
4445 * This register wraps very quickly under heavy packet drops.
4446 * If you need correct statistics, you can enable this check.
4447 */
4448 if (BGE_IS_5705_PLUS(sc))
4449 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4450 #endif
4451 return (rx_npkts);
4452 }
4453
4454 static void
bge_rxcsum(struct bge_softc * sc,struct bge_rx_bd * cur_rx,struct mbuf * m)4455 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4456 {
4457
4458 if (BGE_IS_5717_PLUS(sc)) {
4459 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4460 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4461 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4462 if ((cur_rx->bge_error_flag &
4463 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4464 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4465 }
4466 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4467 m->m_pkthdr.csum_data =
4468 cur_rx->bge_tcp_udp_csum;
4469 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4470 CSUM_PSEUDO_HDR;
4471 }
4472 }
4473 } else {
4474 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4475 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4476 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4477 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4478 }
4479 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4480 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4481 m->m_pkthdr.csum_data =
4482 cur_rx->bge_tcp_udp_csum;
4483 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4484 CSUM_PSEUDO_HDR;
4485 }
4486 }
4487 }
4488
4489 static void
bge_txeof(struct bge_softc * sc,uint16_t tx_cons)4490 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4491 {
4492 struct bge_tx_bd *cur_tx;
4493 if_t ifp;
4494
4495 BGE_LOCK_ASSERT(sc);
4496
4497 /* Nothing to do. */
4498 if (sc->bge_tx_saved_considx == tx_cons)
4499 return;
4500
4501 ifp = sc->bge_ifp;
4502
4503 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4504 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4505 /*
4506 * Go through our tx ring and free mbufs for those
4507 * frames that have been sent.
4508 */
4509 while (sc->bge_tx_saved_considx != tx_cons) {
4510 uint32_t idx;
4511
4512 idx = sc->bge_tx_saved_considx;
4513 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4514 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4515 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4516 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4517 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4518 sc->bge_cdata.bge_tx_dmamap[idx],
4519 BUS_DMASYNC_POSTWRITE);
4520 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4521 sc->bge_cdata.bge_tx_dmamap[idx]);
4522 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4523 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4524 }
4525 sc->bge_txcnt--;
4526 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4527 }
4528
4529 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4530 if (sc->bge_txcnt == 0)
4531 sc->bge_timer = 0;
4532 }
4533
4534 #ifdef DEVICE_POLLING
4535 static int
bge_poll(if_t ifp,enum poll_cmd cmd,int count)4536 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4537 {
4538 struct bge_softc *sc = if_getsoftc(ifp);
4539 uint16_t rx_prod, tx_cons;
4540 uint32_t statusword;
4541 int rx_npkts = 0;
4542
4543 BGE_LOCK(sc);
4544 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4545 BGE_UNLOCK(sc);
4546 return (rx_npkts);
4547 }
4548
4549 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4550 sc->bge_cdata.bge_status_map,
4551 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4552 /* Fetch updates from the status block. */
4553 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4554 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4555
4556 statusword = sc->bge_ldata.bge_status_block->bge_status;
4557 /* Clear the status so the next pass only sees the changes. */
4558 sc->bge_ldata.bge_status_block->bge_status = 0;
4559
4560 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4561 sc->bge_cdata.bge_status_map,
4562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4563
4564 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4565 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4566 sc->bge_link_evt++;
4567
4568 if (cmd == POLL_AND_CHECK_STATUS)
4569 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4570 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4571 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4572 bge_link_upd(sc);
4573
4574 sc->rxcycles = count;
4575 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4576 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4577 BGE_UNLOCK(sc);
4578 return (rx_npkts);
4579 }
4580 bge_txeof(sc, tx_cons);
4581 if (!if_sendq_empty(ifp))
4582 bge_start_locked(ifp);
4583
4584 BGE_UNLOCK(sc);
4585 return (rx_npkts);
4586 }
4587 #endif /* DEVICE_POLLING */
4588
4589 static int
bge_msi_intr(void * arg)4590 bge_msi_intr(void *arg)
4591 {
4592 struct bge_softc *sc;
4593
4594 sc = (struct bge_softc *)arg;
4595 /*
4596 * This interrupt is not shared and controller already
4597 * disabled further interrupt.
4598 */
4599 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4600 return (FILTER_HANDLED);
4601 }
4602
4603 static void
bge_intr_task(void * arg,int pending)4604 bge_intr_task(void *arg, int pending)
4605 {
4606 struct bge_softc *sc;
4607 if_t ifp;
4608 uint32_t status, status_tag;
4609 uint16_t rx_prod, tx_cons;
4610
4611 sc = (struct bge_softc *)arg;
4612 ifp = sc->bge_ifp;
4613
4614 BGE_LOCK(sc);
4615 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4616 BGE_UNLOCK(sc);
4617 return;
4618 }
4619
4620 /* Get updated status block. */
4621 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4622 sc->bge_cdata.bge_status_map,
4623 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4624
4625 /* Save producer/consumer indices. */
4626 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4627 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4628 status = sc->bge_ldata.bge_status_block->bge_status;
4629 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4630 /* Dirty the status flag. */
4631 sc->bge_ldata.bge_status_block->bge_status = 0;
4632 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4633 sc->bge_cdata.bge_status_map,
4634 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4635 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4636 status_tag = 0;
4637
4638 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4639 bge_link_upd(sc);
4640
4641 /* Let controller work. */
4642 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4643
4644 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4645 sc->bge_rx_saved_considx != rx_prod) {
4646 /* Check RX return ring producer/consumer. */
4647 BGE_UNLOCK(sc);
4648 bge_rxeof(sc, rx_prod, 0);
4649 BGE_LOCK(sc);
4650 }
4651 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4652 /* Check TX ring producer/consumer. */
4653 bge_txeof(sc, tx_cons);
4654 if (!if_sendq_empty(ifp))
4655 bge_start_locked(ifp);
4656 }
4657 BGE_UNLOCK(sc);
4658 }
4659
4660 static void
bge_intr(void * xsc)4661 bge_intr(void *xsc)
4662 {
4663 struct bge_softc *sc;
4664 if_t ifp;
4665 uint32_t statusword;
4666 uint16_t rx_prod, tx_cons;
4667
4668 sc = xsc;
4669
4670 BGE_LOCK(sc);
4671
4672 ifp = sc->bge_ifp;
4673
4674 #ifdef DEVICE_POLLING
4675 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4676 BGE_UNLOCK(sc);
4677 return;
4678 }
4679 #endif
4680
4681 /*
4682 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4683 * disable interrupts by writing nonzero like we used to, since with
4684 * our current organization this just gives complications and
4685 * pessimizations for re-enabling interrupts. We used to have races
4686 * instead of the necessary complications. Disabling interrupts
4687 * would just reduce the chance of a status update while we are
4688 * running (by switching to the interrupt-mode coalescence
4689 * parameters), but this chance is already very low so it is more
4690 * efficient to get another interrupt than prevent it.
4691 *
4692 * We do the ack first to ensure another interrupt if there is a
4693 * status update after the ack. We don't check for the status
4694 * changing later because it is more efficient to get another
4695 * interrupt than prevent it, not quite as above (not checking is
4696 * a smaller optimization than not toggling the interrupt enable,
4697 * since checking doesn't involve PCI accesses and toggling require
4698 * the status check). So toggling would probably be a pessimization
4699 * even with MSI. It would only be needed for using a task queue.
4700 */
4701 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4702
4703 /*
4704 * Do the mandatory PCI flush as well as get the link status.
4705 */
4706 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4707
4708 /* Make sure the descriptor ring indexes are coherent. */
4709 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4710 sc->bge_cdata.bge_status_map,
4711 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4712 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4713 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4714 sc->bge_ldata.bge_status_block->bge_status = 0;
4715 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4716 sc->bge_cdata.bge_status_map,
4717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4718
4719 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4720 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4721 statusword || sc->bge_link_evt)
4722 bge_link_upd(sc);
4723
4724 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4725 /* Check RX return ring producer/consumer. */
4726 bge_rxeof(sc, rx_prod, 1);
4727 }
4728
4729 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4730 /* Check TX ring producer/consumer. */
4731 bge_txeof(sc, tx_cons);
4732 }
4733
4734 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4735 !if_sendq_empty(ifp))
4736 bge_start_locked(ifp);
4737
4738 BGE_UNLOCK(sc);
4739 }
4740
4741 static void
bge_asf_driver_up(struct bge_softc * sc)4742 bge_asf_driver_up(struct bge_softc *sc)
4743 {
4744 if (sc->bge_asf_mode & ASF_STACKUP) {
4745 /* Send ASF heartbeat aprox. every 2s */
4746 if (sc->bge_asf_count)
4747 sc->bge_asf_count --;
4748 else {
4749 sc->bge_asf_count = 2;
4750 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4751 BGE_FW_CMD_DRV_ALIVE);
4752 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4753 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4754 BGE_FW_HB_TIMEOUT_SEC);
4755 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4756 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4757 BGE_RX_CPU_DRV_EVENT);
4758 }
4759 }
4760 }
4761
4762 static void
bge_tick(void * xsc)4763 bge_tick(void *xsc)
4764 {
4765 struct bge_softc *sc = xsc;
4766 struct mii_data *mii = NULL;
4767
4768 BGE_LOCK_ASSERT(sc);
4769
4770 /* Synchronize with possible callout reset/stop. */
4771 if (callout_pending(&sc->bge_stat_ch) ||
4772 !callout_active(&sc->bge_stat_ch))
4773 return;
4774
4775 if (BGE_IS_5705_PLUS(sc))
4776 bge_stats_update_regs(sc);
4777 else
4778 bge_stats_update(sc);
4779
4780 /* XXX Add APE heartbeat check here? */
4781
4782 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4783 mii = device_get_softc(sc->bge_miibus);
4784 /*
4785 * Do not touch PHY if we have link up. This could break
4786 * IPMI/ASF mode or produce extra input errors
4787 * (extra errors was reported for bcm5701 & bcm5704).
4788 */
4789 if (!sc->bge_link)
4790 mii_tick(mii);
4791 } else {
4792 /*
4793 * Since in TBI mode auto-polling can't be used we should poll
4794 * link status manually. Here we register pending link event
4795 * and trigger interrupt.
4796 */
4797 #ifdef DEVICE_POLLING
4798 /* In polling mode we poll link state in bge_poll(). */
4799 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4800 #endif
4801 {
4802 sc->bge_link_evt++;
4803 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4804 sc->bge_flags & BGE_FLAG_5788)
4805 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4806 else
4807 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4808 }
4809 }
4810
4811 bge_asf_driver_up(sc);
4812 bge_watchdog(sc);
4813
4814 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4815 }
4816
4817 static void
bge_stats_update_regs(struct bge_softc * sc)4818 bge_stats_update_regs(struct bge_softc *sc)
4819 {
4820 if_t ifp;
4821 struct bge_mac_stats *stats;
4822 uint32_t val;
4823
4824 ifp = sc->bge_ifp;
4825 stats = &sc->bge_mac_stats;
4826
4827 stats->ifHCOutOctets +=
4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4829 stats->etherStatsCollisions +=
4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4831 stats->outXonSent +=
4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4833 stats->outXoffSent +=
4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4835 stats->dot3StatsInternalMacTransmitErrors +=
4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4837 stats->dot3StatsSingleCollisionFrames +=
4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4839 stats->dot3StatsMultipleCollisionFrames +=
4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4841 stats->dot3StatsDeferredTransmissions +=
4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4843 stats->dot3StatsExcessiveCollisions +=
4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4845 stats->dot3StatsLateCollisions +=
4846 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4847 stats->ifHCOutUcastPkts +=
4848 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4849 stats->ifHCOutMulticastPkts +=
4850 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4851 stats->ifHCOutBroadcastPkts +=
4852 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4853
4854 stats->ifHCInOctets +=
4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4856 stats->etherStatsFragments +=
4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4858 stats->ifHCInUcastPkts +=
4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4860 stats->ifHCInMulticastPkts +=
4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4862 stats->ifHCInBroadcastPkts +=
4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4864 stats->dot3StatsFCSErrors +=
4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4866 stats->dot3StatsAlignmentErrors +=
4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4868 stats->xonPauseFramesReceived +=
4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4870 stats->xoffPauseFramesReceived +=
4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4872 stats->macControlFramesReceived +=
4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4874 stats->xoffStateEntered +=
4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4876 stats->dot3StatsFramesTooLong +=
4877 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4878 stats->etherStatsJabbers +=
4879 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4880 stats->etherStatsUndersizePkts +=
4881 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4882
4883 stats->FramesDroppedDueToFilters +=
4884 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4885 stats->DmaWriteQueueFull +=
4886 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4887 stats->DmaWriteHighPriQueueFull +=
4888 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4889 stats->NoMoreRxBDs +=
4890 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4891 /*
4892 * XXX
4893 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4894 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4895 * includes number of unwanted multicast frames. This comes
4896 * from silicon bug and known workaround to get rough(not
4897 * exact) counter is to enable interrupt on MBUF low water
4898 * attention. This can be accomplished by setting
4899 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4900 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4901 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4902 * However that change would generate more interrupts and
4903 * there are still possibilities of losing multiple frames
4904 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4905 * Given that the workaround still would not get correct
4906 * counter I don't think it's worth to implement it. So
4907 * ignore reading the counter on controllers that have the
4908 * silicon bug.
4909 */
4910 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4911 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4912 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4913 stats->InputDiscards +=
4914 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4915 stats->InputErrors +=
4916 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4917 stats->RecvThresholdHit +=
4918 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4919
4920 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4921 /*
4922 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4923 * frames, it's safe to disable workaround for DMA engine's
4924 * miscalculation of TXMBUF space.
4925 */
4926 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4927 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4928 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4929 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4930 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4931 else
4932 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4933 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4934 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4935 }
4936 }
4937 }
4938
4939 static void
bge_stats_clear_regs(struct bge_softc * sc)4940 bge_stats_clear_regs(struct bge_softc *sc)
4941 {
4942
4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4953 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4954 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4955 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4956
4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4968 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4969 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4970 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4971
4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4975 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4976 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4977 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4978 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4979 }
4980
4981 static void
bge_stats_update(struct bge_softc * sc)4982 bge_stats_update(struct bge_softc *sc)
4983 {
4984 if_t ifp;
4985 bus_size_t stats;
4986 uint32_t cnt; /* current register value */
4987
4988 ifp = sc->bge_ifp;
4989
4990 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4991
4992 #define READ_STAT(sc, stats, stat) \
4993 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4994
4995 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4996 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4997 sc->bge_tx_collisions = cnt;
4998
4999 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5000 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
5001 sc->bge_rx_nobds = cnt;
5002 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5003 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5004 sc->bge_rx_inerrs = cnt;
5005 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5006 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5007 sc->bge_rx_discards = cnt;
5008
5009 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5010 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5011 sc->bge_tx_discards = cnt;
5012
5013 #undef READ_STAT
5014 }
5015
5016 /*
5017 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5018 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5019 * but when such padded frames employ the bge IP/TCP checksum offload,
5020 * the hardware checksum assist gives incorrect results (possibly
5021 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5022 * If we pad such runts with zeros, the onboard checksum comes out correct.
5023 */
5024 static __inline int
bge_cksum_pad(struct mbuf * m)5025 bge_cksum_pad(struct mbuf *m)
5026 {
5027 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5028 struct mbuf *last;
5029
5030 /* If there's only the packet-header and we can pad there, use it. */
5031 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5032 M_TRAILINGSPACE(m) >= padlen) {
5033 last = m;
5034 } else {
5035 /*
5036 * Walk packet chain to find last mbuf. We will either
5037 * pad there, or append a new mbuf and pad it.
5038 */
5039 for (last = m; last->m_next != NULL; last = last->m_next);
5040 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5041 /* Allocate new empty mbuf, pad it. Compact later. */
5042 struct mbuf *n;
5043
5044 MGET(n, M_NOWAIT, MT_DATA);
5045 if (n == NULL)
5046 return (ENOBUFS);
5047 n->m_len = 0;
5048 last->m_next = n;
5049 last = n;
5050 }
5051 }
5052
5053 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5054 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5055 last->m_len += padlen;
5056 m->m_pkthdr.len += padlen;
5057
5058 return (0);
5059 }
5060
5061 static struct mbuf *
bge_check_short_dma(struct mbuf * m)5062 bge_check_short_dma(struct mbuf *m)
5063 {
5064 struct mbuf *n;
5065 int found;
5066
5067 /*
5068 * If device receive two back-to-back send BDs with less than
5069 * or equal to 8 total bytes then the device may hang. The two
5070 * back-to-back send BDs must in the same frame for this failure
5071 * to occur. Scan mbuf chains and see whether two back-to-back
5072 * send BDs are there. If this is the case, allocate new mbuf
5073 * and copy the frame to workaround the silicon bug.
5074 */
5075 for (n = m, found = 0; n != NULL; n = n->m_next) {
5076 if (n->m_len < 8) {
5077 found++;
5078 if (found > 1)
5079 break;
5080 continue;
5081 }
5082 found = 0;
5083 }
5084
5085 if (found > 1) {
5086 n = m_defrag(m, M_NOWAIT);
5087 if (n == NULL)
5088 m_freem(m);
5089 } else
5090 n = m;
5091 return (n);
5092 }
5093
5094 static struct mbuf *
bge_setup_tso(struct bge_softc * sc,struct mbuf * m,uint16_t * mss,uint16_t * flags)5095 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5096 uint16_t *flags)
5097 {
5098 struct ip *ip;
5099 struct tcphdr *tcp;
5100 struct mbuf *n;
5101 uint16_t hlen;
5102 uint32_t poff;
5103
5104 if (M_WRITABLE(m) == 0) {
5105 /* Get a writable copy. */
5106 n = m_dup(m, M_NOWAIT);
5107 m_freem(m);
5108 if (n == NULL)
5109 return (NULL);
5110 m = n;
5111 }
5112 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5113 if (m == NULL)
5114 return (NULL);
5115 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5116 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5117 m = m_pullup(m, poff + sizeof(struct tcphdr));
5118 if (m == NULL)
5119 return (NULL);
5120 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5121 m = m_pullup(m, poff + (tcp->th_off << 2));
5122 if (m == NULL)
5123 return (NULL);
5124 /*
5125 * It seems controller doesn't modify IP length and TCP pseudo
5126 * checksum. These checksum computed by upper stack should be 0.
5127 */
5128 *mss = m->m_pkthdr.tso_segsz;
5129 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5130 ip->ip_sum = 0;
5131 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5132 /* Clear pseudo checksum computed by TCP stack. */
5133 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5134 tcp->th_sum = 0;
5135 /*
5136 * Broadcom controllers uses different descriptor format for
5137 * TSO depending on ASIC revision. Due to TSO-capable firmware
5138 * license issue and lower performance of firmware based TSO
5139 * we only support hardware based TSO.
5140 */
5141 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5142 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5143 if (sc->bge_flags & BGE_FLAG_TSO3) {
5144 /*
5145 * For BCM5717 and newer controllers, hardware based TSO
5146 * uses the 14 lower bits of the bge_mss field to store the
5147 * MSS and the upper 2 bits to store the lowest 2 bits of
5148 * the IP/TCP header length. The upper 6 bits of the header
5149 * length are stored in the bge_flags[14:10,4] field. Jumbo
5150 * frames are supported.
5151 */
5152 *mss |= ((hlen & 0x3) << 14);
5153 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5154 } else {
5155 /*
5156 * For BCM5755 and newer controllers, hardware based TSO uses
5157 * the lower 11 bits to store the MSS and the upper 5 bits to
5158 * store the IP/TCP header length. Jumbo frames are not
5159 * supported.
5160 */
5161 *mss |= (hlen << 11);
5162 }
5163 return (m);
5164 }
5165
5166 /*
5167 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5168 * pointers to descriptors.
5169 */
5170 static int
bge_encap(struct bge_softc * sc,struct mbuf ** m_head,uint32_t * txidx)5171 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5172 {
5173 bus_dma_segment_t segs[BGE_NSEG_NEW];
5174 bus_dmamap_t map;
5175 struct bge_tx_bd *d;
5176 struct mbuf *m = *m_head;
5177 uint32_t idx = *txidx;
5178 uint16_t csum_flags, mss, vlan_tag;
5179 int nsegs, i, error;
5180
5181 csum_flags = 0;
5182 mss = 0;
5183 vlan_tag = 0;
5184 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5185 m->m_next != NULL) {
5186 *m_head = bge_check_short_dma(m);
5187 if (*m_head == NULL)
5188 return (ENOBUFS);
5189 m = *m_head;
5190 }
5191 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5192 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5193 if (*m_head == NULL)
5194 return (ENOBUFS);
5195 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5196 BGE_TXBDFLAG_CPU_POST_DMA;
5197 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5198 if (m->m_pkthdr.csum_flags & CSUM_IP)
5199 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5200 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5201 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5202 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5203 (error = bge_cksum_pad(m)) != 0) {
5204 m_freem(m);
5205 *m_head = NULL;
5206 return (error);
5207 }
5208 }
5209 }
5210
5211 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5212 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5213 m->m_pkthdr.len > ETHER_MAX_LEN)
5214 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5215 if (sc->bge_forced_collapse > 0 &&
5216 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5217 /*
5218 * Forcedly collapse mbuf chains to overcome hardware
5219 * limitation which only support a single outstanding
5220 * DMA read operation.
5221 */
5222 if (sc->bge_forced_collapse == 1)
5223 m = m_defrag(m, M_NOWAIT);
5224 else
5225 m = m_collapse(m, M_NOWAIT,
5226 sc->bge_forced_collapse);
5227 if (m == NULL)
5228 m = *m_head;
5229 *m_head = m;
5230 }
5231 }
5232
5233 map = sc->bge_cdata.bge_tx_dmamap[idx];
5234 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5235 &nsegs, BUS_DMA_NOWAIT);
5236 if (error == EFBIG) {
5237 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5238 if (m == NULL) {
5239 m_freem(*m_head);
5240 *m_head = NULL;
5241 return (ENOBUFS);
5242 }
5243 *m_head = m;
5244 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5245 m, segs, &nsegs, BUS_DMA_NOWAIT);
5246 if (error) {
5247 m_freem(m);
5248 *m_head = NULL;
5249 return (error);
5250 }
5251 } else if (error != 0)
5252 return (error);
5253
5254 /* Check if we have enough free send BDs. */
5255 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5256 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5257 return (ENOBUFS);
5258 }
5259
5260 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5261
5262 if (m->m_flags & M_VLANTAG) {
5263 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5264 vlan_tag = m->m_pkthdr.ether_vtag;
5265 }
5266
5267 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5268 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5269 /*
5270 * 5725 family of devices corrupts TSO packets when TSO DMA
5271 * buffers cross into regions which are within MSS bytes of
5272 * a 4GB boundary. If we encounter the condition, drop the
5273 * packet.
5274 */
5275 for (i = 0; ; i++) {
5276 d = &sc->bge_ldata.bge_tx_ring[idx];
5277 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5278 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5279 d->bge_len = segs[i].ds_len;
5280 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5281 d->bge_addr.bge_addr_lo)
5282 break;
5283 d->bge_flags = csum_flags;
5284 d->bge_vlan_tag = vlan_tag;
5285 d->bge_mss = mss;
5286 if (i == nsegs - 1)
5287 break;
5288 BGE_INC(idx, BGE_TX_RING_CNT);
5289 }
5290 if (i != nsegs - 1) {
5291 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5292 BUS_DMASYNC_POSTWRITE);
5293 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5294 m_freem(*m_head);
5295 *m_head = NULL;
5296 return (EIO);
5297 }
5298 } else {
5299 for (i = 0; ; i++) {
5300 d = &sc->bge_ldata.bge_tx_ring[idx];
5301 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5302 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5303 d->bge_len = segs[i].ds_len;
5304 d->bge_flags = csum_flags;
5305 d->bge_vlan_tag = vlan_tag;
5306 d->bge_mss = mss;
5307 if (i == nsegs - 1)
5308 break;
5309 BGE_INC(idx, BGE_TX_RING_CNT);
5310 }
5311 }
5312
5313 /* Mark the last segment as end of packet... */
5314 d->bge_flags |= BGE_TXBDFLAG_END;
5315
5316 /*
5317 * Insure that the map for this transmission
5318 * is placed at the array index of the last descriptor
5319 * in this chain.
5320 */
5321 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5322 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5323 sc->bge_cdata.bge_tx_chain[idx] = m;
5324 sc->bge_txcnt += nsegs;
5325
5326 BGE_INC(idx, BGE_TX_RING_CNT);
5327 *txidx = idx;
5328
5329 return (0);
5330 }
5331
5332 /*
5333 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5334 * to the mbuf data regions directly in the transmit descriptors.
5335 */
5336 static void
bge_start_locked(if_t ifp)5337 bge_start_locked(if_t ifp)
5338 {
5339 struct bge_softc *sc;
5340 struct mbuf *m_head;
5341 uint32_t prodidx;
5342 int count;
5343
5344 sc = if_getsoftc(ifp);
5345 BGE_LOCK_ASSERT(sc);
5346
5347 if (!sc->bge_link ||
5348 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5349 IFF_DRV_RUNNING)
5350 return;
5351
5352 prodidx = sc->bge_tx_prodidx;
5353
5354 for (count = 0; !if_sendq_empty(ifp);) {
5355 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5356 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5357 break;
5358 }
5359 m_head = if_dequeue(ifp);
5360 if (m_head == NULL)
5361 break;
5362
5363 /*
5364 * Pack the data into the transmit ring. If we
5365 * don't have room, set the OACTIVE flag and wait
5366 * for the NIC to drain the ring.
5367 */
5368 if (bge_encap(sc, &m_head, &prodidx)) {
5369 if (m_head == NULL)
5370 break;
5371 if_sendq_prepend(ifp, m_head);
5372 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5373 break;
5374 }
5375 ++count;
5376
5377 /*
5378 * If there's a BPF listener, bounce a copy of this frame
5379 * to him.
5380 */
5381 if_bpfmtap(ifp, m_head);
5382 }
5383
5384 if (count > 0) {
5385 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5386 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5387 /* Transmit. */
5388 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5389 /* 5700 b2 errata */
5390 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5391 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5392
5393 sc->bge_tx_prodidx = prodidx;
5394
5395 /*
5396 * Set a timeout in case the chip goes out to lunch.
5397 */
5398 sc->bge_timer = BGE_TX_TIMEOUT;
5399 }
5400 }
5401
5402 /*
5403 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5404 * to the mbuf data regions directly in the transmit descriptors.
5405 */
5406 static void
bge_start(if_t ifp)5407 bge_start(if_t ifp)
5408 {
5409 struct bge_softc *sc;
5410
5411 sc = if_getsoftc(ifp);
5412 BGE_LOCK(sc);
5413 bge_start_locked(ifp);
5414 BGE_UNLOCK(sc);
5415 }
5416
5417 static void
bge_init_locked(struct bge_softc * sc)5418 bge_init_locked(struct bge_softc *sc)
5419 {
5420 if_t ifp;
5421 uint16_t *m;
5422 uint32_t mode;
5423
5424 BGE_LOCK_ASSERT(sc);
5425
5426 ifp = sc->bge_ifp;
5427
5428 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5429 return;
5430
5431 /* Cancel pending I/O and flush buffers. */
5432 bge_stop(sc);
5433
5434 bge_stop_fw(sc);
5435 bge_sig_pre_reset(sc, BGE_RESET_START);
5436 bge_reset(sc);
5437 bge_sig_legacy(sc, BGE_RESET_START);
5438 bge_sig_post_reset(sc, BGE_RESET_START);
5439
5440 bge_chipinit(sc);
5441
5442 /*
5443 * Init the various state machines, ring
5444 * control blocks and firmware.
5445 */
5446 if (bge_blockinit(sc)) {
5447 device_printf(sc->bge_dev, "initialization failure\n");
5448 return;
5449 }
5450
5451 ifp = sc->bge_ifp;
5452
5453 /* Specify MTU. */
5454 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5455 ETHER_HDR_LEN + ETHER_CRC_LEN +
5456 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5457
5458 /* Load our MAC address. */
5459 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5460 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5461 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5462
5463 /* Program promiscuous mode. */
5464 bge_setpromisc(sc);
5465
5466 /* Program multicast filter. */
5467 bge_setmulti(sc);
5468
5469 /* Program VLAN tag stripping. */
5470 bge_setvlan(sc);
5471
5472 /* Override UDP checksum offloading. */
5473 if (sc->bge_forced_udpcsum == 0)
5474 sc->bge_csum_features &= ~CSUM_UDP;
5475 else
5476 sc->bge_csum_features |= CSUM_UDP;
5477 if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5478 if_getcapenable(ifp) & IFCAP_TXCSUM) {
5479 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5480 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5481 }
5482
5483 /* Init RX ring. */
5484 if (bge_init_rx_ring_std(sc) != 0) {
5485 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5486 bge_stop(sc);
5487 return;
5488 }
5489
5490 /*
5491 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5492 * memory to insure that the chip has in fact read the first
5493 * entry of the ring.
5494 */
5495 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5496 uint32_t v, i;
5497 for (i = 0; i < 10; i++) {
5498 DELAY(20);
5499 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5500 if (v == (MCLBYTES - ETHER_ALIGN))
5501 break;
5502 }
5503 if (i == 10)
5504 device_printf (sc->bge_dev,
5505 "5705 A0 chip failed to load RX ring\n");
5506 }
5507
5508 /* Init jumbo RX ring. */
5509 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5510 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5511 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5512 if (bge_init_rx_ring_jumbo(sc) != 0) {
5513 device_printf(sc->bge_dev,
5514 "no memory for jumbo Rx buffers.\n");
5515 bge_stop(sc);
5516 return;
5517 }
5518 }
5519
5520 /* Init our RX return ring index. */
5521 sc->bge_rx_saved_considx = 0;
5522
5523 /* Init our RX/TX stat counters. */
5524 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5525
5526 /* Init TX ring. */
5527 bge_init_tx_ring(sc);
5528
5529 /* Enable TX MAC state machine lockup fix. */
5530 mode = CSR_READ_4(sc, BGE_TX_MODE);
5531 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5532 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5533 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5534 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5535 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5536 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5537 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5538 }
5539 /* Turn on transmitter. */
5540 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5541 DELAY(100);
5542
5543 /* Turn on receiver. */
5544 mode = CSR_READ_4(sc, BGE_RX_MODE);
5545 if (BGE_IS_5755_PLUS(sc))
5546 mode |= BGE_RXMODE_IPV6_ENABLE;
5547 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5548 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5549 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5550 DELAY(10);
5551
5552 /*
5553 * Set the number of good frames to receive after RX MBUF
5554 * Low Watermark has been reached. After the RX MAC receives
5555 * this number of frames, it will drop subsequent incoming
5556 * frames until the MBUF High Watermark is reached.
5557 */
5558 if (BGE_IS_57765_PLUS(sc))
5559 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5560 else
5561 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5562
5563 /* Clear MAC statistics. */
5564 if (BGE_IS_5705_PLUS(sc))
5565 bge_stats_clear_regs(sc);
5566
5567 /* Tell firmware we're alive. */
5568 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5569
5570 #ifdef DEVICE_POLLING
5571 /* Disable interrupts if we are polling. */
5572 if (if_getcapenable(ifp) & IFCAP_POLLING) {
5573 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5574 BGE_PCIMISCCTL_MASK_PCI_INTR);
5575 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5576 } else
5577 #endif
5578
5579 /* Enable host interrupts. */
5580 {
5581 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5582 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5583 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5584 }
5585
5586 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5587 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5588
5589 bge_ifmedia_upd_locked(ifp);
5590
5591 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5592 }
5593
5594 static void
bge_init(void * xsc)5595 bge_init(void *xsc)
5596 {
5597 struct bge_softc *sc = xsc;
5598
5599 BGE_LOCK(sc);
5600 bge_init_locked(sc);
5601 BGE_UNLOCK(sc);
5602 }
5603
5604 /*
5605 * Set media options.
5606 */
5607 static int
bge_ifmedia_upd(if_t ifp)5608 bge_ifmedia_upd(if_t ifp)
5609 {
5610 struct bge_softc *sc = if_getsoftc(ifp);
5611 int res;
5612
5613 BGE_LOCK(sc);
5614 res = bge_ifmedia_upd_locked(ifp);
5615 BGE_UNLOCK(sc);
5616
5617 return (res);
5618 }
5619
5620 static int
bge_ifmedia_upd_locked(if_t ifp)5621 bge_ifmedia_upd_locked(if_t ifp)
5622 {
5623 struct bge_softc *sc = if_getsoftc(ifp);
5624 struct mii_data *mii;
5625 struct mii_softc *miisc;
5626 struct ifmedia *ifm;
5627
5628 BGE_LOCK_ASSERT(sc);
5629
5630 ifm = &sc->bge_ifmedia;
5631
5632 /* If this is a 1000baseX NIC, enable the TBI port. */
5633 if (sc->bge_flags & BGE_FLAG_TBI) {
5634 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5635 return (EINVAL);
5636 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5637 case IFM_AUTO:
5638 /*
5639 * The BCM5704 ASIC appears to have a special
5640 * mechanism for programming the autoneg
5641 * advertisement registers in TBI mode.
5642 */
5643 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5644 uint32_t sgdig;
5645 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5646 if (sgdig & BGE_SGDIGSTS_DONE) {
5647 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5648 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5649 sgdig |= BGE_SGDIGCFG_AUTO |
5650 BGE_SGDIGCFG_PAUSE_CAP |
5651 BGE_SGDIGCFG_ASYM_PAUSE;
5652 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5653 sgdig | BGE_SGDIGCFG_SEND);
5654 DELAY(5);
5655 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5656 }
5657 }
5658 break;
5659 case IFM_1000_SX:
5660 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5661 BGE_CLRBIT(sc, BGE_MAC_MODE,
5662 BGE_MACMODE_HALF_DUPLEX);
5663 } else {
5664 BGE_SETBIT(sc, BGE_MAC_MODE,
5665 BGE_MACMODE_HALF_DUPLEX);
5666 }
5667 DELAY(40);
5668 break;
5669 default:
5670 return (EINVAL);
5671 }
5672 return (0);
5673 }
5674
5675 sc->bge_link_evt++;
5676 mii = device_get_softc(sc->bge_miibus);
5677 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5678 PHY_RESET(miisc);
5679 mii_mediachg(mii);
5680
5681 /*
5682 * Force an interrupt so that we will call bge_link_upd
5683 * if needed and clear any pending link state attention.
5684 * Without this we are not getting any further interrupts
5685 * for link state changes and thus will not UP the link and
5686 * not be able to send in bge_start_locked. The only
5687 * way to get things working was to receive a packet and
5688 * get an RX intr.
5689 * bge_tick should help for fiber cards and we might not
5690 * need to do this here if BGE_FLAG_TBI is set but as
5691 * we poll for fiber anyway it should not harm.
5692 */
5693 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5694 sc->bge_flags & BGE_FLAG_5788)
5695 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5696 else
5697 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5698
5699 return (0);
5700 }
5701
5702 /*
5703 * Report current media status.
5704 */
5705 static void
bge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)5706 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5707 {
5708 struct bge_softc *sc = if_getsoftc(ifp);
5709 struct mii_data *mii;
5710
5711 BGE_LOCK(sc);
5712
5713 if ((if_getflags(ifp) & IFF_UP) == 0) {
5714 BGE_UNLOCK(sc);
5715 return;
5716 }
5717 if (sc->bge_flags & BGE_FLAG_TBI) {
5718 ifmr->ifm_status = IFM_AVALID;
5719 ifmr->ifm_active = IFM_ETHER;
5720 if (CSR_READ_4(sc, BGE_MAC_STS) &
5721 BGE_MACSTAT_TBI_PCS_SYNCHED)
5722 ifmr->ifm_status |= IFM_ACTIVE;
5723 else {
5724 ifmr->ifm_active |= IFM_NONE;
5725 BGE_UNLOCK(sc);
5726 return;
5727 }
5728 ifmr->ifm_active |= IFM_1000_SX;
5729 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5730 ifmr->ifm_active |= IFM_HDX;
5731 else
5732 ifmr->ifm_active |= IFM_FDX;
5733 BGE_UNLOCK(sc);
5734 return;
5735 }
5736
5737 mii = device_get_softc(sc->bge_miibus);
5738 mii_pollstat(mii);
5739 ifmr->ifm_active = mii->mii_media_active;
5740 ifmr->ifm_status = mii->mii_media_status;
5741
5742 BGE_UNLOCK(sc);
5743 }
5744
5745 static int
bge_ioctl(if_t ifp,u_long command,caddr_t data)5746 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5747 {
5748 struct bge_softc *sc = if_getsoftc(ifp);
5749 struct ifreq *ifr = (struct ifreq *) data;
5750 struct mii_data *mii;
5751 int flags, mask, error = 0;
5752
5753 switch (command) {
5754 case SIOCSIFMTU:
5755 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5756 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5757 if (ifr->ifr_mtu < ETHERMIN ||
5758 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5759 error = EINVAL;
5760 break;
5761 }
5762 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5763 error = EINVAL;
5764 break;
5765 }
5766 BGE_LOCK(sc);
5767 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5768 if_setmtu(ifp, ifr->ifr_mtu);
5769 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5770 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5771 bge_init_locked(sc);
5772 }
5773 }
5774 BGE_UNLOCK(sc);
5775 break;
5776 case SIOCSIFFLAGS:
5777 BGE_LOCK(sc);
5778 if (if_getflags(ifp) & IFF_UP) {
5779 /*
5780 * If only the state of the PROMISC flag changed,
5781 * then just use the 'set promisc mode' command
5782 * instead of reinitializing the entire NIC. Doing
5783 * a full re-init means reloading the firmware and
5784 * waiting for it to start up, which may take a
5785 * second or two. Similarly for ALLMULTI.
5786 */
5787 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5788 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5789 if (flags & IFF_PROMISC)
5790 bge_setpromisc(sc);
5791 if (flags & IFF_ALLMULTI)
5792 bge_setmulti(sc);
5793 } else
5794 bge_init_locked(sc);
5795 } else {
5796 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5797 bge_stop(sc);
5798 }
5799 }
5800 sc->bge_if_flags = if_getflags(ifp);
5801 BGE_UNLOCK(sc);
5802 error = 0;
5803 break;
5804 case SIOCADDMULTI:
5805 case SIOCDELMULTI:
5806 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5807 BGE_LOCK(sc);
5808 bge_setmulti(sc);
5809 BGE_UNLOCK(sc);
5810 error = 0;
5811 }
5812 break;
5813 case SIOCSIFMEDIA:
5814 case SIOCGIFMEDIA:
5815 if (sc->bge_flags & BGE_FLAG_TBI) {
5816 error = ifmedia_ioctl(ifp, ifr,
5817 &sc->bge_ifmedia, command);
5818 } else {
5819 mii = device_get_softc(sc->bge_miibus);
5820 error = ifmedia_ioctl(ifp, ifr,
5821 &mii->mii_media, command);
5822 }
5823 break;
5824 case SIOCSIFCAP:
5825 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5826 #ifdef DEVICE_POLLING
5827 if (mask & IFCAP_POLLING) {
5828 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5829 error = ether_poll_register(bge_poll, ifp);
5830 if (error)
5831 return (error);
5832 BGE_LOCK(sc);
5833 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5834 BGE_PCIMISCCTL_MASK_PCI_INTR);
5835 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5836 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5837 BGE_UNLOCK(sc);
5838 } else {
5839 error = ether_poll_deregister(ifp);
5840 /* Enable interrupt even in error case */
5841 BGE_LOCK(sc);
5842 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5843 BGE_PCIMISCCTL_MASK_PCI_INTR);
5844 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5845 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5846 BGE_UNLOCK(sc);
5847 }
5848 }
5849 #endif
5850 if ((mask & IFCAP_TXCSUM) != 0 &&
5851 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5852 if_togglecapenable(ifp, IFCAP_TXCSUM);
5853 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5854 if_sethwassistbits(ifp,
5855 sc->bge_csum_features, 0);
5856 else
5857 if_sethwassistbits(ifp, 0,
5858 sc->bge_csum_features);
5859 }
5860
5861 if ((mask & IFCAP_RXCSUM) != 0 &&
5862 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5863 if_togglecapenable(ifp, IFCAP_RXCSUM);
5864
5865 if ((mask & IFCAP_TSO4) != 0 &&
5866 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5867 if_togglecapenable(ifp, IFCAP_TSO4);
5868 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5869 if_sethwassistbits(ifp, CSUM_TSO, 0);
5870 else
5871 if_sethwassistbits(ifp, 0, CSUM_TSO);
5872 }
5873
5874 if (mask & IFCAP_VLAN_MTU) {
5875 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5876 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5877 bge_init(sc);
5878 }
5879
5880 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5881 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5882 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5883 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5884 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5885 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5886 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5887 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5888 BGE_LOCK(sc);
5889 bge_setvlan(sc);
5890 BGE_UNLOCK(sc);
5891 }
5892 #ifdef VLAN_CAPABILITIES
5893 if_vlancap(ifp);
5894 #endif
5895 break;
5896 default:
5897 error = ether_ioctl(ifp, command, data);
5898 break;
5899 }
5900
5901 return (error);
5902 }
5903
5904 static void
bge_watchdog(struct bge_softc * sc)5905 bge_watchdog(struct bge_softc *sc)
5906 {
5907 if_t ifp;
5908 uint32_t status;
5909
5910 BGE_LOCK_ASSERT(sc);
5911
5912 if (sc->bge_timer == 0 || --sc->bge_timer)
5913 return;
5914
5915 /* If pause frames are active then don't reset the hardware. */
5916 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5917 status = CSR_READ_4(sc, BGE_RX_STS);
5918 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5919 /*
5920 * If link partner has us in XOFF state then wait for
5921 * the condition to clear.
5922 */
5923 CSR_WRITE_4(sc, BGE_RX_STS, status);
5924 sc->bge_timer = BGE_TX_TIMEOUT;
5925 return;
5926 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5927 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5928 /*
5929 * If link partner has us in XOFF state then wait for
5930 * the condition to clear.
5931 */
5932 CSR_WRITE_4(sc, BGE_RX_STS, status);
5933 sc->bge_timer = BGE_TX_TIMEOUT;
5934 return;
5935 }
5936 /*
5937 * Any other condition is unexpected and the controller
5938 * should be reset.
5939 */
5940 }
5941
5942 ifp = sc->bge_ifp;
5943
5944 if_printf(ifp, "watchdog timeout -- resetting\n");
5945
5946 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5947 bge_init_locked(sc);
5948
5949 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5950 }
5951
5952 static void
bge_stop_block(struct bge_softc * sc,bus_size_t reg,uint32_t bit)5953 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5954 {
5955 int i;
5956
5957 BGE_CLRBIT(sc, reg, bit);
5958
5959 for (i = 0; i < BGE_TIMEOUT; i++) {
5960 if ((CSR_READ_4(sc, reg) & bit) == 0)
5961 return;
5962 DELAY(100);
5963 }
5964 }
5965
5966 /*
5967 * Stop the adapter and free any mbufs allocated to the
5968 * RX and TX lists.
5969 */
5970 static void
bge_stop(struct bge_softc * sc)5971 bge_stop(struct bge_softc *sc)
5972 {
5973 if_t ifp;
5974
5975 BGE_LOCK_ASSERT(sc);
5976
5977 ifp = sc->bge_ifp;
5978
5979 callout_stop(&sc->bge_stat_ch);
5980
5981 /* Disable host interrupts. */
5982 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5983 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5984
5985 /*
5986 * Tell firmware we're shutting down.
5987 */
5988 bge_stop_fw(sc);
5989 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5990
5991 /*
5992 * Disable all of the receiver blocks.
5993 */
5994 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5995 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5996 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5997 if (BGE_IS_5700_FAMILY(sc))
5998 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5999 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6000 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6001 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6002
6003 /*
6004 * Disable all of the transmit blocks.
6005 */
6006 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6007 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6008 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6009 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6010 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6011 if (BGE_IS_5700_FAMILY(sc))
6012 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6013 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6014
6015 /*
6016 * Shut down all of the memory managers and related
6017 * state machines.
6018 */
6019 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6020 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6021 if (BGE_IS_5700_FAMILY(sc))
6022 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6023
6024 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6025 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6026 if (!(BGE_IS_5705_PLUS(sc))) {
6027 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6028 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6029 }
6030 /* Update MAC statistics. */
6031 if (BGE_IS_5705_PLUS(sc))
6032 bge_stats_update_regs(sc);
6033
6034 bge_reset(sc);
6035 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6036 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6037
6038 /*
6039 * Keep the ASF firmware running if up.
6040 */
6041 if (sc->bge_asf_mode & ASF_STACKUP)
6042 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6043 else
6044 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6045
6046 /* Free the RX lists. */
6047 bge_free_rx_ring_std(sc);
6048
6049 /* Free jumbo RX list. */
6050 if (BGE_IS_JUMBO_CAPABLE(sc))
6051 bge_free_rx_ring_jumbo(sc);
6052
6053 /* Free TX buffers. */
6054 bge_free_tx_ring(sc);
6055
6056 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6057
6058 /* Clear MAC's link state (PHY may still have link UP). */
6059 if (bootverbose && sc->bge_link)
6060 if_printf(sc->bge_ifp, "link DOWN\n");
6061 sc->bge_link = 0;
6062
6063 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6064 }
6065
6066 /*
6067 * Stop all chip I/O so that the kernel's probe routines don't
6068 * get confused by errant DMAs when rebooting.
6069 */
6070 static int
bge_shutdown(device_t dev)6071 bge_shutdown(device_t dev)
6072 {
6073 struct bge_softc *sc;
6074
6075 sc = device_get_softc(dev);
6076 BGE_LOCK(sc);
6077 bge_stop(sc);
6078 BGE_UNLOCK(sc);
6079
6080 return (0);
6081 }
6082
6083 static int
bge_suspend(device_t dev)6084 bge_suspend(device_t dev)
6085 {
6086 struct bge_softc *sc;
6087
6088 sc = device_get_softc(dev);
6089 BGE_LOCK(sc);
6090 bge_stop(sc);
6091 BGE_UNLOCK(sc);
6092
6093 return (0);
6094 }
6095
6096 static int
bge_resume(device_t dev)6097 bge_resume(device_t dev)
6098 {
6099 struct bge_softc *sc;
6100 if_t ifp;
6101
6102 sc = device_get_softc(dev);
6103 BGE_LOCK(sc);
6104 ifp = sc->bge_ifp;
6105 if (if_getflags(ifp) & IFF_UP) {
6106 bge_init_locked(sc);
6107 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6108 bge_start_locked(ifp);
6109 }
6110 BGE_UNLOCK(sc);
6111
6112 return (0);
6113 }
6114
6115 static void
bge_link_upd(struct bge_softc * sc)6116 bge_link_upd(struct bge_softc *sc)
6117 {
6118 struct mii_data *mii;
6119 uint32_t link, status;
6120
6121 BGE_LOCK_ASSERT(sc);
6122
6123 /* Clear 'pending link event' flag. */
6124 sc->bge_link_evt = 0;
6125
6126 /*
6127 * Process link state changes.
6128 * Grrr. The link status word in the status block does
6129 * not work correctly on the BCM5700 rev AX and BX chips,
6130 * according to all available information. Hence, we have
6131 * to enable MII interrupts in order to properly obtain
6132 * async link changes. Unfortunately, this also means that
6133 * we have to read the MAC status register to detect link
6134 * changes, thereby adding an additional register access to
6135 * the interrupt handler.
6136 *
6137 * XXX: perhaps link state detection procedure used for
6138 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6139 */
6140
6141 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6142 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6143 status = CSR_READ_4(sc, BGE_MAC_STS);
6144 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6145 mii = device_get_softc(sc->bge_miibus);
6146 mii_pollstat(mii);
6147 if (!sc->bge_link &&
6148 mii->mii_media_status & IFM_ACTIVE &&
6149 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6150 sc->bge_link++;
6151 if (bootverbose)
6152 if_printf(sc->bge_ifp, "link UP\n");
6153 } else if (sc->bge_link &&
6154 (!(mii->mii_media_status & IFM_ACTIVE) ||
6155 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6156 sc->bge_link = 0;
6157 if (bootverbose)
6158 if_printf(sc->bge_ifp, "link DOWN\n");
6159 }
6160
6161 /* Clear the interrupt. */
6162 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6163 BGE_EVTENB_MI_INTERRUPT);
6164 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6165 BRGPHY_MII_ISR);
6166 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6167 BRGPHY_MII_IMR, BRGPHY_INTRS);
6168 }
6169 return;
6170 }
6171
6172 if (sc->bge_flags & BGE_FLAG_TBI) {
6173 status = CSR_READ_4(sc, BGE_MAC_STS);
6174 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6175 if (!sc->bge_link) {
6176 sc->bge_link++;
6177 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6178 BGE_CLRBIT(sc, BGE_MAC_MODE,
6179 BGE_MACMODE_TBI_SEND_CFGS);
6180 DELAY(40);
6181 }
6182 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6183 if (bootverbose)
6184 if_printf(sc->bge_ifp, "link UP\n");
6185 if_link_state_change(sc->bge_ifp,
6186 LINK_STATE_UP);
6187 }
6188 } else if (sc->bge_link) {
6189 sc->bge_link = 0;
6190 if (bootverbose)
6191 if_printf(sc->bge_ifp, "link DOWN\n");
6192 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6193 }
6194 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6195 /*
6196 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6197 * in status word always set. Workaround this bug by reading
6198 * PHY link status directly.
6199 */
6200 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6201
6202 if (link != sc->bge_link ||
6203 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6204 mii = device_get_softc(sc->bge_miibus);
6205 mii_pollstat(mii);
6206 if (!sc->bge_link &&
6207 mii->mii_media_status & IFM_ACTIVE &&
6208 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6209 sc->bge_link++;
6210 if (bootverbose)
6211 if_printf(sc->bge_ifp, "link UP\n");
6212 } else if (sc->bge_link &&
6213 (!(mii->mii_media_status & IFM_ACTIVE) ||
6214 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6215 sc->bge_link = 0;
6216 if (bootverbose)
6217 if_printf(sc->bge_ifp, "link DOWN\n");
6218 }
6219 }
6220 } else {
6221 /*
6222 * For controllers that call mii_tick, we have to poll
6223 * link status.
6224 */
6225 mii = device_get_softc(sc->bge_miibus);
6226 mii_pollstat(mii);
6227 bge_miibus_statchg(sc->bge_dev);
6228 }
6229
6230 /* Disable MAC attention when link is up. */
6231 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6232 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6233 BGE_MACSTAT_LINK_CHANGED);
6234 }
6235
6236 static void
bge_add_sysctls(struct bge_softc * sc)6237 bge_add_sysctls(struct bge_softc *sc)
6238 {
6239 struct sysctl_ctx_list *ctx;
6240 struct sysctl_oid_list *children;
6241 int unit;
6242
6243 ctx = device_get_sysctl_ctx(sc->bge_dev);
6244 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6245
6246 #ifdef BGE_REGISTER_DEBUG
6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6248 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6249 "Debug Information");
6250
6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6252 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6253 "MAC Register Read");
6254
6255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6256 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6257 "APE Register Read");
6258
6259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6260 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6261 "Memory Read");
6262
6263 #endif
6264
6265 unit = device_get_unit(sc->bge_dev);
6266 /*
6267 * A common design characteristic for many Broadcom client controllers
6268 * is that they only support a single outstanding DMA read operation
6269 * on the PCIe bus. This means that it will take twice as long to fetch
6270 * a TX frame that is split into header and payload buffers as it does
6271 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6272 * these controllers, coalescing buffers to reduce the number of memory
6273 * reads is effective way to get maximum performance(about 940Mbps).
6274 * Without collapsing TX buffers the maximum TCP bulk transfer
6275 * performance is about 850Mbps. However forcing coalescing mbufs
6276 * consumes a lot of CPU cycles, so leave it off by default.
6277 */
6278 sc->bge_forced_collapse = 0;
6279 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6280 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6281 "Number of fragmented TX buffers of a frame allowed before "
6282 "forced collapsing");
6283
6284 sc->bge_msi = 1;
6285 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6286 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6287
6288 /*
6289 * It seems all Broadcom controllers have a bug that can generate UDP
6290 * datagrams with checksum value 0 when TX UDP checksum offloading is
6291 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6292 * Even though the probability of generating such UDP datagrams is
6293 * low, I don't want to see FreeBSD boxes to inject such datagrams
6294 * into network so disable UDP checksum offloading by default. Users
6295 * still override this behavior by setting a sysctl variable,
6296 * dev.bge.0.forced_udpcsum.
6297 */
6298 sc->bge_forced_udpcsum = 0;
6299 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6300 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6301 "Enable UDP checksum offloading even if controller can "
6302 "generate UDP checksum value 0");
6303
6304 if (BGE_IS_5705_PLUS(sc))
6305 bge_add_sysctl_stats_regs(sc, ctx, children);
6306 else
6307 bge_add_sysctl_stats(sc, ctx, children);
6308 }
6309
6310 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6311 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6312 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6313 desc)
6314
6315 static void
bge_add_sysctl_stats(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6316 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6317 struct sysctl_oid_list *parent)
6318 {
6319 struct sysctl_oid *tree;
6320 struct sysctl_oid_list *children, *schildren;
6321
6322 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6323 NULL, "BGE Statistics");
6324 schildren = children = SYSCTL_CHILDREN(tree);
6325 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6326 children, COSFramesDroppedDueToFilters,
6327 "FramesDroppedDueToFilters");
6328 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6329 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6330 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6331 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6332 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6333 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6334 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6335 children, ifInDiscards, "InputDiscards");
6336 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6337 children, ifInErrors, "InputErrors");
6338 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6339 children, nicRecvThresholdHit, "RecvThresholdHit");
6340 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6341 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6342 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6343 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6344 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6345 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6346 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6347 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6348 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6349 children, nicRingStatusUpdate, "RingStatusUpdate");
6350 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6351 children, nicInterrupts, "Interrupts");
6352 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6353 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6354 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6355 children, nicSendThresholdHit, "SendThresholdHit");
6356
6357 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6358 NULL, "BGE RX Statistics");
6359 children = SYSCTL_CHILDREN(tree);
6360 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6361 children, rxstats.ifHCInOctets, "ifHCInOctets");
6362 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6363 children, rxstats.etherStatsFragments, "Fragments");
6364 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6365 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6366 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6367 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6368 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6369 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6370 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6371 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6372 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6373 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6374 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6375 children, rxstats.xoffPauseFramesReceived,
6376 "xoffPauseFramesReceived");
6377 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6378 children, rxstats.macControlFramesReceived,
6379 "ControlFramesReceived");
6380 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6381 children, rxstats.xoffStateEntered, "xoffStateEntered");
6382 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6383 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6384 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6385 children, rxstats.etherStatsJabbers, "Jabbers");
6386 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6387 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6388 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6389 children, rxstats.inRangeLengthError, "inRangeLengthError");
6390 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6391 children, rxstats.outRangeLengthError, "outRangeLengthError");
6392
6393 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6394 NULL, "BGE TX Statistics");
6395 children = SYSCTL_CHILDREN(tree);
6396 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6397 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6398 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6399 children, txstats.etherStatsCollisions, "Collisions");
6400 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6401 children, txstats.outXonSent, "XonSent");
6402 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6403 children, txstats.outXoffSent, "XoffSent");
6404 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6405 children, txstats.flowControlDone, "flowControlDone");
6406 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6407 children, txstats.dot3StatsInternalMacTransmitErrors,
6408 "InternalMacTransmitErrors");
6409 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6410 children, txstats.dot3StatsSingleCollisionFrames,
6411 "SingleCollisionFrames");
6412 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6413 children, txstats.dot3StatsMultipleCollisionFrames,
6414 "MultipleCollisionFrames");
6415 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6416 children, txstats.dot3StatsDeferredTransmissions,
6417 "DeferredTransmissions");
6418 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6419 children, txstats.dot3StatsExcessiveCollisions,
6420 "ExcessiveCollisions");
6421 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6422 children, txstats.dot3StatsLateCollisions,
6423 "LateCollisions");
6424 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6425 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6426 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6427 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6428 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6429 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6430 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6431 children, txstats.dot3StatsCarrierSenseErrors,
6432 "CarrierSenseErrors");
6433 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6434 children, txstats.ifOutDiscards, "Discards");
6435 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6436 children, txstats.ifOutErrors, "Errors");
6437 }
6438
6439 #undef BGE_SYSCTL_STAT
6440
6441 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6442 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6443
6444 static void
bge_add_sysctl_stats_regs(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6445 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6446 struct sysctl_oid_list *parent)
6447 {
6448 struct sysctl_oid *tree;
6449 struct sysctl_oid_list *child, *schild;
6450 struct bge_mac_stats *stats;
6451
6452 stats = &sc->bge_mac_stats;
6453 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6454 NULL, "BGE Statistics");
6455 schild = child = SYSCTL_CHILDREN(tree);
6456 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6457 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6458 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6459 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6460 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6461 &stats->DmaWriteHighPriQueueFull,
6462 "NIC DMA Write High Priority Queue Full");
6463 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6464 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6465 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6466 &stats->InputDiscards, "Discarded Input Frames");
6467 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6468 &stats->InputErrors, "Input Errors");
6469 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6470 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6471
6472 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6473 NULL, "BGE RX Statistics");
6474 child = SYSCTL_CHILDREN(tree);
6475 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6476 &stats->ifHCInOctets, "Inbound Octets");
6477 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6478 &stats->etherStatsFragments, "Fragments");
6479 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6480 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6481 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6482 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6484 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6486 &stats->dot3StatsFCSErrors, "FCS Errors");
6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6488 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6490 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6491 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6492 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6493 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6494 &stats->macControlFramesReceived, "MAC Control Frames Received");
6495 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6496 &stats->xoffStateEntered, "XOFF State Entered");
6497 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6498 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6500 &stats->etherStatsJabbers, "Jabbers");
6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6502 &stats->etherStatsUndersizePkts, "Undersized Packets");
6503
6504 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6505 NULL, "BGE TX Statistics");
6506 child = SYSCTL_CHILDREN(tree);
6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6508 &stats->ifHCOutOctets, "Outbound Octets");
6509 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6510 &stats->etherStatsCollisions, "TX Collisions");
6511 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6512 &stats->outXonSent, "XON Sent");
6513 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6514 &stats->outXoffSent, "XOFF Sent");
6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6516 &stats->dot3StatsInternalMacTransmitErrors,
6517 "Internal MAC TX Errors");
6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6519 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6520 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6521 &stats->dot3StatsMultipleCollisionFrames,
6522 "Multiple Collision Frames");
6523 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6524 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6525 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6526 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6527 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6528 &stats->dot3StatsLateCollisions, "Late Collisions");
6529 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6530 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6531 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6532 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6533 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6534 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6535 }
6536
6537 #undef BGE_SYSCTL_STAT_ADD64
6538
6539 static int
bge_sysctl_stats(SYSCTL_HANDLER_ARGS)6540 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6541 {
6542 struct bge_softc *sc;
6543 uint32_t result;
6544 int offset;
6545
6546 sc = (struct bge_softc *)arg1;
6547 offset = arg2;
6548 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6549 offsetof(bge_hostaddr, bge_addr_lo));
6550 return (sysctl_handle_int(oidp, &result, 0, req));
6551 }
6552
6553 #ifdef BGE_REGISTER_DEBUG
6554 static int
bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)6555 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6556 {
6557 struct bge_softc *sc;
6558 uint16_t *sbdata;
6559 int error, result, sbsz;
6560 int i, j;
6561
6562 result = -1;
6563 error = sysctl_handle_int(oidp, &result, 0, req);
6564 if (error || (req->newptr == NULL))
6565 return (error);
6566
6567 if (result == 1) {
6568 sc = (struct bge_softc *)arg1;
6569
6570 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6571 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6572 sbsz = BGE_STATUS_BLK_SZ;
6573 else
6574 sbsz = 32;
6575 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6576 printf("Status Block:\n");
6577 BGE_LOCK(sc);
6578 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6579 sc->bge_cdata.bge_status_map,
6580 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6581 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6582 printf("%06x:", i);
6583 for (j = 0; j < 8; j++)
6584 printf(" %04x", sbdata[i++]);
6585 printf("\n");
6586 }
6587
6588 printf("Registers:\n");
6589 for (i = 0x800; i < 0xA00; ) {
6590 printf("%06x:", i);
6591 for (j = 0; j < 8; j++) {
6592 printf(" %08x", CSR_READ_4(sc, i));
6593 i += 4;
6594 }
6595 printf("\n");
6596 }
6597 BGE_UNLOCK(sc);
6598
6599 printf("Hardware Flags:\n");
6600 if (BGE_IS_5717_PLUS(sc))
6601 printf(" - 5717 Plus\n");
6602 if (BGE_IS_5755_PLUS(sc))
6603 printf(" - 5755 Plus\n");
6604 if (BGE_IS_575X_PLUS(sc))
6605 printf(" - 575X Plus\n");
6606 if (BGE_IS_5705_PLUS(sc))
6607 printf(" - 5705 Plus\n");
6608 if (BGE_IS_5714_FAMILY(sc))
6609 printf(" - 5714 Family\n");
6610 if (BGE_IS_5700_FAMILY(sc))
6611 printf(" - 5700 Family\n");
6612 if (sc->bge_flags & BGE_FLAG_JUMBO)
6613 printf(" - Supports Jumbo Frames\n");
6614 if (sc->bge_flags & BGE_FLAG_PCIX)
6615 printf(" - PCI-X Bus\n");
6616 if (sc->bge_flags & BGE_FLAG_PCIE)
6617 printf(" - PCI Express Bus\n");
6618 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6619 printf(" - No 3 LEDs\n");
6620 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6621 printf(" - RX Alignment Bug\n");
6622 }
6623
6624 return (error);
6625 }
6626
6627 static int
bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)6628 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6629 {
6630 struct bge_softc *sc;
6631 int error;
6632 uint16_t result;
6633 uint32_t val;
6634
6635 result = -1;
6636 error = sysctl_handle_int(oidp, &result, 0, req);
6637 if (error || (req->newptr == NULL))
6638 return (error);
6639
6640 if (result < 0x8000) {
6641 sc = (struct bge_softc *)arg1;
6642 val = CSR_READ_4(sc, result);
6643 printf("reg 0x%06X = 0x%08X\n", result, val);
6644 }
6645
6646 return (error);
6647 }
6648
6649 static int
bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)6650 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6651 {
6652 struct bge_softc *sc;
6653 int error;
6654 uint16_t result;
6655 uint32_t val;
6656
6657 result = -1;
6658 error = sysctl_handle_int(oidp, &result, 0, req);
6659 if (error || (req->newptr == NULL))
6660 return (error);
6661
6662 if (result < 0x8000) {
6663 sc = (struct bge_softc *)arg1;
6664 val = APE_READ_4(sc, result);
6665 printf("reg 0x%06X = 0x%08X\n", result, val);
6666 }
6667
6668 return (error);
6669 }
6670
6671 static int
bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)6672 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6673 {
6674 struct bge_softc *sc;
6675 int error;
6676 uint16_t result;
6677 uint32_t val;
6678
6679 result = -1;
6680 error = sysctl_handle_int(oidp, &result, 0, req);
6681 if (error || (req->newptr == NULL))
6682 return (error);
6683
6684 if (result < 0x8000) {
6685 sc = (struct bge_softc *)arg1;
6686 val = bge_readmem_ind(sc, result);
6687 printf("mem 0x%06X = 0x%08X\n", result, val);
6688 }
6689
6690 return (error);
6691 }
6692 #endif
6693
6694 static int
bge_get_eaddr_fw(struct bge_softc * sc,uint8_t ether_addr[])6695 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6696 {
6697
6698 if (sc->bge_flags & BGE_FLAG_EADDR)
6699 return (1);
6700
6701 #ifdef __sparc64__
6702 OF_getetheraddr(sc->bge_dev, ether_addr);
6703 return (0);
6704 #endif
6705 return (1);
6706 }
6707
6708 static int
bge_get_eaddr_mem(struct bge_softc * sc,uint8_t ether_addr[])6709 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6710 {
6711 uint32_t mac_addr;
6712
6713 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6714 if ((mac_addr >> 16) == 0x484b) {
6715 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6716 ether_addr[1] = (uint8_t)mac_addr;
6717 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6718 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6719 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6720 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6721 ether_addr[5] = (uint8_t)mac_addr;
6722 return (0);
6723 }
6724 return (1);
6725 }
6726
6727 static int
bge_get_eaddr_nvram(struct bge_softc * sc,uint8_t ether_addr[])6728 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6729 {
6730 int mac_offset = BGE_EE_MAC_OFFSET;
6731
6732 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6733 mac_offset = BGE_EE_MAC_OFFSET_5906;
6734
6735 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6736 ETHER_ADDR_LEN));
6737 }
6738
6739 static int
bge_get_eaddr_eeprom(struct bge_softc * sc,uint8_t ether_addr[])6740 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6741 {
6742
6743 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6744 return (1);
6745
6746 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6747 ETHER_ADDR_LEN));
6748 }
6749
6750 static int
bge_get_eaddr(struct bge_softc * sc,uint8_t eaddr[])6751 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6752 {
6753 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6754 /* NOTE: Order is critical */
6755 bge_get_eaddr_fw,
6756 bge_get_eaddr_mem,
6757 bge_get_eaddr_nvram,
6758 bge_get_eaddr_eeprom,
6759 NULL
6760 };
6761 const bge_eaddr_fcn_t *func;
6762
6763 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6764 if ((*func)(sc, eaddr) == 0)
6765 break;
6766 }
6767 return (*func == NULL ? ENXIO : 0);
6768 }
6769
6770 static uint64_t
bge_get_counter(if_t ifp,ift_counter cnt)6771 bge_get_counter(if_t ifp, ift_counter cnt)
6772 {
6773 struct bge_softc *sc;
6774 struct bge_mac_stats *stats;
6775
6776 sc = if_getsoftc(ifp);
6777 if (!BGE_IS_5705_PLUS(sc))
6778 return (if_get_counter_default(ifp, cnt));
6779 stats = &sc->bge_mac_stats;
6780
6781 switch (cnt) {
6782 case IFCOUNTER_IERRORS:
6783 return (stats->NoMoreRxBDs + stats->InputDiscards +
6784 stats->InputErrors);
6785 case IFCOUNTER_COLLISIONS:
6786 return (stats->etherStatsCollisions);
6787 default:
6788 return (if_get_counter_default(ifp, cnt));
6789 }
6790 }
6791