1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/mbuf.h>
40 #include <sys/module.h>
41 #include <sys/rman.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
47
48 #include <net/bpf.h>
49 #include <net/if.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_llc.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/if_vlan_var.h>
58
59 #include <netinet/in.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/ip.h>
62 #include <netinet/tcp.h>
63
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
69
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72
73 #include <dev/ale/if_alereg.h>
74 #include <dev/ale/if_alevar.h>
75
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
78
79 /* For more information about Tx checksum offload issues see ale_encap(). */
80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
81
82 MODULE_DEPEND(ale, pci, 1, 1, 1);
83 MODULE_DEPEND(ale, ether, 1, 1, 1);
84 MODULE_DEPEND(ale, miibus, 1, 1, 1);
85
86 /* Tunables. */
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
91
92 /*
93 * Devices supported by this driver.
94 */
95 static const struct ale_dev {
96 uint16_t ale_vendorid;
97 uint16_t ale_deviceid;
98 const char *ale_name;
99 } ale_devs[] = {
100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
102 };
103
104 static int ale_attach(device_t);
105 static int ale_check_boundary(struct ale_softc *);
106 static int ale_detach(device_t);
107 static int ale_dma_alloc(struct ale_softc *);
108 static void ale_dma_free(struct ale_softc *);
109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_get_macaddr(struct ale_softc *);
112 static void ale_init(void *);
113 static void ale_init_locked(struct ale_softc *);
114 static void ale_init_rx_pages(struct ale_softc *);
115 static void ale_init_tx_ring(struct ale_softc *);
116 static void ale_int_task(void *, int);
117 static int ale_intr(void *);
118 static int ale_ioctl(if_t, u_long, caddr_t);
119 static void ale_mac_config(struct ale_softc *);
120 static int ale_miibus_readreg(device_t, int, int);
121 static void ale_miibus_statchg(device_t);
122 static int ale_miibus_writereg(device_t, int, int, int);
123 static int ale_mediachange(if_t);
124 static void ale_mediastatus(if_t, struct ifmediareq *);
125 static void ale_phy_reset(struct ale_softc *);
126 static int ale_probe(device_t);
127 static void ale_reset(struct ale_softc *);
128 static int ale_resume(device_t);
129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
130 uint32_t, uint32_t *);
131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
132 static int ale_rxeof(struct ale_softc *sc, int);
133 static void ale_rxfilter(struct ale_softc *);
134 static void ale_rxvlan(struct ale_softc *);
135 static void ale_setlinkspeed(struct ale_softc *);
136 static void ale_setwol(struct ale_softc *);
137 static int ale_shutdown(device_t);
138 static void ale_start(if_t);
139 static void ale_start_locked(if_t);
140 static void ale_stats_clear(struct ale_softc *);
141 static void ale_stats_update(struct ale_softc *);
142 static void ale_stop(struct ale_softc *);
143 static void ale_stop_mac(struct ale_softc *);
144 static int ale_suspend(device_t);
145 static void ale_sysctl_node(struct ale_softc *);
146 static void ale_tick(void *);
147 static void ale_txeof(struct ale_softc *);
148 static void ale_watchdog(struct ale_softc *);
149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
152
153 static device_method_t ale_methods[] = {
154 /* Device interface. */
155 DEVMETHOD(device_probe, ale_probe),
156 DEVMETHOD(device_attach, ale_attach),
157 DEVMETHOD(device_detach, ale_detach),
158 DEVMETHOD(device_shutdown, ale_shutdown),
159 DEVMETHOD(device_suspend, ale_suspend),
160 DEVMETHOD(device_resume, ale_resume),
161
162 /* MII interface. */
163 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
164 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
165 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
166
167 DEVMETHOD_END
168 };
169
170 static driver_t ale_driver = {
171 "ale",
172 ale_methods,
173 sizeof(struct ale_softc)
174 };
175
176 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL);
177 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs,
178 nitems(ale_devs));
179 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL);
180
181 static struct resource_spec ale_res_spec_mem[] = {
182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
183 { -1, 0, 0 }
184 };
185
186 static struct resource_spec ale_irq_spec_legacy[] = {
187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
188 { -1, 0, 0 }
189 };
190
191 static struct resource_spec ale_irq_spec_msi[] = {
192 { SYS_RES_IRQ, 1, RF_ACTIVE },
193 { -1, 0, 0 }
194 };
195
196 static struct resource_spec ale_irq_spec_msix[] = {
197 { SYS_RES_IRQ, 1, RF_ACTIVE },
198 { -1, 0, 0 }
199 };
200
201 static int
ale_miibus_readreg(device_t dev,int phy,int reg)202 ale_miibus_readreg(device_t dev, int phy, int reg)
203 {
204 struct ale_softc *sc;
205 uint32_t v;
206 int i;
207
208 sc = device_get_softc(dev);
209
210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
213 DELAY(5);
214 v = CSR_READ_4(sc, ALE_MDIO);
215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
216 break;
217 }
218
219 if (i == 0) {
220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
221 return (0);
222 }
223
224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
225 }
226
227 static int
ale_miibus_writereg(device_t dev,int phy,int reg,int val)228 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
229 {
230 struct ale_softc *sc;
231 uint32_t v;
232 int i;
233
234 sc = device_get_softc(dev);
235
236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
240 DELAY(5);
241 v = CSR_READ_4(sc, ALE_MDIO);
242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
243 break;
244 }
245
246 if (i == 0)
247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
248
249 return (0);
250 }
251
252 static void
ale_miibus_statchg(device_t dev)253 ale_miibus_statchg(device_t dev)
254 {
255 struct ale_softc *sc;
256 struct mii_data *mii;
257 if_t ifp;
258 uint32_t reg;
259
260 sc = device_get_softc(dev);
261 mii = device_get_softc(sc->ale_miibus);
262 ifp = sc->ale_ifp;
263 if (mii == NULL || ifp == NULL ||
264 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
265 return;
266
267 sc->ale_flags &= ~ALE_FLAG_LINK;
268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
269 (IFM_ACTIVE | IFM_AVALID)) {
270 switch (IFM_SUBTYPE(mii->mii_media_active)) {
271 case IFM_10_T:
272 case IFM_100_TX:
273 sc->ale_flags |= ALE_FLAG_LINK;
274 break;
275 case IFM_1000_T:
276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
277 sc->ale_flags |= ALE_FLAG_LINK;
278 break;
279 default:
280 break;
281 }
282 }
283
284 /* Stop Rx/Tx MACs. */
285 ale_stop_mac(sc);
286
287 /* Program MACs with resolved speed/duplex/flow-control. */
288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
289 ale_mac_config(sc);
290 /* Reenable Tx/Rx MACs. */
291 reg = CSR_READ_4(sc, ALE_MAC_CFG);
292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
294 }
295 }
296
297 static void
ale_mediastatus(if_t ifp,struct ifmediareq * ifmr)298 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr)
299 {
300 struct ale_softc *sc;
301 struct mii_data *mii;
302
303 sc = if_getsoftc(ifp);
304 ALE_LOCK(sc);
305 if ((if_getflags(ifp) & IFF_UP) == 0) {
306 ALE_UNLOCK(sc);
307 return;
308 }
309 mii = device_get_softc(sc->ale_miibus);
310
311 mii_pollstat(mii);
312 ifmr->ifm_status = mii->mii_media_status;
313 ifmr->ifm_active = mii->mii_media_active;
314 ALE_UNLOCK(sc);
315 }
316
317 static int
ale_mediachange(if_t ifp)318 ale_mediachange(if_t ifp)
319 {
320 struct ale_softc *sc;
321 struct mii_data *mii;
322 struct mii_softc *miisc;
323 int error;
324
325 sc = if_getsoftc(ifp);
326 ALE_LOCK(sc);
327 mii = device_get_softc(sc->ale_miibus);
328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
329 PHY_RESET(miisc);
330 error = mii_mediachg(mii);
331 ALE_UNLOCK(sc);
332
333 return (error);
334 }
335
336 static int
ale_probe(device_t dev)337 ale_probe(device_t dev)
338 {
339 const struct ale_dev *sp;
340 int i;
341 uint16_t vendor, devid;
342
343 vendor = pci_get_vendor(dev);
344 devid = pci_get_device(dev);
345 sp = ale_devs;
346 for (i = 0; i < nitems(ale_devs); i++) {
347 if (vendor == sp->ale_vendorid &&
348 devid == sp->ale_deviceid) {
349 device_set_desc(dev, sp->ale_name);
350 return (BUS_PROBE_DEFAULT);
351 }
352 sp++;
353 }
354
355 return (ENXIO);
356 }
357
358 static void
ale_get_macaddr(struct ale_softc * sc)359 ale_get_macaddr(struct ale_softc *sc)
360 {
361 uint32_t ea[2], reg;
362 int i, vpdc;
363
364 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
365 if ((reg & SPI_VPD_ENB) != 0) {
366 reg &= ~SPI_VPD_ENB;
367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
368 }
369
370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
371 /*
372 * PCI VPD capability found, let TWSI reload EEPROM.
373 * This will set ethernet address of controller.
374 */
375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
376 TWSI_CTRL_SW_LD_START);
377 for (i = 100; i > 0; i--) {
378 DELAY(1000);
379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
380 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
381 break;
382 }
383 if (i == 0)
384 device_printf(sc->ale_dev,
385 "reloading EEPROM timeout!\n");
386 } else {
387 if (bootverbose)
388 device_printf(sc->ale_dev,
389 "PCI VPD capability not found!\n");
390 }
391
392 ea[0] = CSR_READ_4(sc, ALE_PAR0);
393 ea[1] = CSR_READ_4(sc, ALE_PAR1);
394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
400 }
401
402 static void
ale_phy_reset(struct ale_softc * sc)403 ale_phy_reset(struct ale_softc *sc)
404 {
405
406 /* Reset magic from Linux. */
407 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
409 GPHY_CTRL_PHY_PLL_ON);
410 DELAY(1000);
411 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
414 DELAY(1000);
415
416 #define ATPHY_DBG_ADDR 0x1D
417 #define ATPHY_DBG_DATA 0x1E
418
419 /* Enable hibernation mode. */
420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
421 ATPHY_DBG_ADDR, 0x0B);
422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
423 ATPHY_DBG_DATA, 0xBC00);
424 /* Set Class A/B for all modes. */
425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
426 ATPHY_DBG_ADDR, 0x00);
427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
428 ATPHY_DBG_DATA, 0x02EF);
429 /* Enable 10BT power saving. */
430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
431 ATPHY_DBG_ADDR, 0x12);
432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
433 ATPHY_DBG_DATA, 0x4C04);
434 /* Adjust 1000T power. */
435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
436 ATPHY_DBG_ADDR, 0x04);
437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
438 ATPHY_DBG_ADDR, 0x8BBB);
439 /* 10BT center tap voltage. */
440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
441 ATPHY_DBG_ADDR, 0x05);
442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
443 ATPHY_DBG_ADDR, 0x2C46);
444
445 #undef ATPHY_DBG_ADDR
446 #undef ATPHY_DBG_DATA
447 DELAY(1000);
448 }
449
450 static int
ale_attach(device_t dev)451 ale_attach(device_t dev)
452 {
453 struct ale_softc *sc;
454 if_t ifp;
455 uint16_t burst;
456 int error, i, msic, msixc;
457 uint32_t rxf_len, txf_len;
458
459 error = 0;
460 sc = device_get_softc(dev);
461 sc->ale_dev = dev;
462
463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
464 MTX_DEF);
465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
466 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
467
468 /* Map the device. */
469 pci_enable_busmaster(dev);
470 sc->ale_res_spec = ale_res_spec_mem;
471 sc->ale_irq_spec = ale_irq_spec_legacy;
472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
473 if (error != 0) {
474 device_printf(dev, "cannot allocate memory resources.\n");
475 goto fail;
476 }
477
478 /* Set PHY address. */
479 sc->ale_phyaddr = ALE_PHY_ADDR;
480
481 /* Reset PHY. */
482 ale_phy_reset(sc);
483
484 /* Reset the ethernet controller. */
485 ale_reset(sc);
486
487 /* Get PCI and chip id/revision. */
488 sc->ale_rev = pci_get_revid(dev);
489 if (sc->ale_rev >= 0xF0) {
490 /* L2E Rev. B. AR8114 */
491 sc->ale_flags |= ALE_FLAG_FASTETHER;
492 } else {
493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
494 /* L1E AR8121 */
495 sc->ale_flags |= ALE_FLAG_JUMBO;
496 } else {
497 /* L2E Rev. A. AR8113 */
498 sc->ale_flags |= ALE_FLAG_FASTETHER;
499 }
500 }
501 /*
502 * All known controllers seems to require 4 bytes alignment
503 * of Tx buffers to make Tx checksum offload with custom
504 * checksum generation method work.
505 */
506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
507 /*
508 * All known controllers seems to have issues on Rx checksum
509 * offload for fragmented IP datagrams.
510 */
511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
512 /*
513 * Don't use Tx CMB. It is known to cause RRS update failure
514 * under certain circumstances. Typical phenomenon of the
515 * issue would be unexpected sequence number encountered in
516 * Rx handler.
517 */
518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
520 MASTER_CHIP_REV_SHIFT;
521 if (bootverbose) {
522 device_printf(dev, "PCI device revision : 0x%04x\n",
523 sc->ale_rev);
524 device_printf(dev, "Chip id/revision : 0x%04x\n",
525 sc->ale_chip_rev);
526 }
527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
529 /*
530 * Uninitialized hardware returns an invalid chip id/revision
531 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
532 */
533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
534 rxf_len == 0xFFFFFFF) {
535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
537 txf_len, rxf_len);
538 error = ENXIO;
539 goto fail;
540 }
541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
542
543 /* Allocate IRQ resources. */
544 msixc = pci_msix_count(dev);
545 msic = pci_msi_count(dev);
546 if (bootverbose) {
547 device_printf(dev, "MSIX count : %d\n", msixc);
548 device_printf(dev, "MSI count : %d\n", msic);
549 }
550
551 /* Prefer MSIX over MSI. */
552 if (msix_disable == 0 || msi_disable == 0) {
553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
554 pci_alloc_msix(dev, &msixc) == 0) {
555 if (msixc == ALE_MSIX_MESSAGES) {
556 device_printf(dev, "Using %d MSIX messages.\n",
557 msixc);
558 sc->ale_flags |= ALE_FLAG_MSIX;
559 sc->ale_irq_spec = ale_irq_spec_msix;
560 } else
561 pci_release_msi(dev);
562 }
563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
564 msic == ALE_MSI_MESSAGES &&
565 pci_alloc_msi(dev, &msic) == 0) {
566 if (msic == ALE_MSI_MESSAGES) {
567 device_printf(dev, "Using %d MSI messages.\n",
568 msic);
569 sc->ale_flags |= ALE_FLAG_MSI;
570 sc->ale_irq_spec = ale_irq_spec_msi;
571 } else
572 pci_release_msi(dev);
573 }
574 }
575
576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
577 if (error != 0) {
578 device_printf(dev, "cannot allocate IRQ resources.\n");
579 goto fail;
580 }
581
582 /* Get DMA parameters from PCIe device control register. */
583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
584 sc->ale_flags |= ALE_FLAG_PCIE;
585 burst = pci_read_config(dev, i + 0x08, 2);
586 /* Max read request size. */
587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
588 DMA_CFG_RD_BURST_SHIFT;
589 /* Max payload size. */
590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
591 DMA_CFG_WR_BURST_SHIFT;
592 if (bootverbose) {
593 device_printf(dev, "Read request size : %d bytes.\n",
594 128 << ((burst >> 12) & 0x07));
595 device_printf(dev, "TLP payload size : %d bytes.\n",
596 128 << ((burst >> 5) & 0x07));
597 }
598 } else {
599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
601 }
602
603 /* Create device sysctl node. */
604 ale_sysctl_node(sc);
605
606 if ((error = ale_dma_alloc(sc)) != 0)
607 goto fail;
608
609 /* Load station address. */
610 ale_get_macaddr(sc);
611
612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
613 if_setsoftc(ifp, sc);
614 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
615 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
616 if_setioctlfn(ifp, ale_ioctl);
617 if_setstartfn(ifp, ale_start);
618 if_setinitfn(ifp, ale_init);
619 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1);
620 if_setsendqready(ifp);
621 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4);
622 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO);
623 if (pci_has_pm(dev)) {
624 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
625 }
626 if_setcapenable(ifp, if_getcapabilities(ifp));
627
628 /* Set up MII bus. */
629 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
630 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
631 MIIF_DOPAUSE);
632 if (error != 0) {
633 device_printf(dev, "attaching PHYs failed\n");
634 goto fail;
635 }
636
637 ether_ifattach(ifp, sc->ale_eaddr);
638
639 /* VLAN capability setup. */
640 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
641 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
642 if_setcapenable(ifp, if_getcapabilities(ifp));
643 /*
644 * Even though controllers supported by ale(3) have Rx checksum
645 * offload bug the workaround for fragmented frames seemed to
646 * work so far. However it seems Rx checksum offload does not
647 * work under certain conditions. So disable Rx checksum offload
648 * until I find more clue about it but allow users to override it.
649 */
650 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
651
652 /* Tell the upper layer(s) we support long frames. */
653 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
654
655 /* Create local taskq. */
656 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
657 taskqueue_thread_enqueue, &sc->ale_tq);
658 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
659 device_get_nameunit(sc->ale_dev));
660
661 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
662 msic = ALE_MSIX_MESSAGES;
663 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
664 msic = ALE_MSI_MESSAGES;
665 else
666 msic = 1;
667 for (i = 0; i < msic; i++) {
668 error = bus_setup_intr(dev, sc->ale_irq[i],
669 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
670 &sc->ale_intrhand[i]);
671 if (error != 0)
672 break;
673 }
674 if (error != 0) {
675 device_printf(dev, "could not set up interrupt handler.\n");
676 taskqueue_free(sc->ale_tq);
677 sc->ale_tq = NULL;
678 ether_ifdetach(ifp);
679 goto fail;
680 }
681
682 fail:
683 if (error != 0)
684 ale_detach(dev);
685
686 return (error);
687 }
688
689 static int
ale_detach(device_t dev)690 ale_detach(device_t dev)
691 {
692 struct ale_softc *sc;
693 if_t ifp;
694 int i, msic;
695
696 sc = device_get_softc(dev);
697
698 ifp = sc->ale_ifp;
699 if (device_is_attached(dev)) {
700 ether_ifdetach(ifp);
701 ALE_LOCK(sc);
702 ale_stop(sc);
703 ALE_UNLOCK(sc);
704 callout_drain(&sc->ale_tick_ch);
705 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
706 }
707
708 if (sc->ale_tq != NULL) {
709 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
710 taskqueue_free(sc->ale_tq);
711 sc->ale_tq = NULL;
712 }
713
714 if (sc->ale_miibus != NULL) {
715 device_delete_child(dev, sc->ale_miibus);
716 sc->ale_miibus = NULL;
717 }
718 bus_generic_detach(dev);
719 ale_dma_free(sc);
720
721 if (ifp != NULL) {
722 if_free(ifp);
723 sc->ale_ifp = NULL;
724 }
725
726 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
727 msic = ALE_MSIX_MESSAGES;
728 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
729 msic = ALE_MSI_MESSAGES;
730 else
731 msic = 1;
732 for (i = 0; i < msic; i++) {
733 if (sc->ale_intrhand[i] != NULL) {
734 bus_teardown_intr(dev, sc->ale_irq[i],
735 sc->ale_intrhand[i]);
736 sc->ale_intrhand[i] = NULL;
737 }
738 }
739
740 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
741 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
742 pci_release_msi(dev);
743 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
744 mtx_destroy(&sc->ale_mtx);
745
746 return (0);
747 }
748
749 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
750 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
751
752 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
753 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
754
755 static void
ale_sysctl_node(struct ale_softc * sc)756 ale_sysctl_node(struct ale_softc *sc)
757 {
758 struct sysctl_ctx_list *ctx;
759 struct sysctl_oid_list *child, *parent;
760 struct sysctl_oid *tree;
761 struct ale_hw_stats *stats;
762 int error;
763
764 stats = &sc->ale_stats;
765 ctx = device_get_sysctl_ctx(sc->ale_dev);
766 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
767
768 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
769 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod,
770 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
771 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
772 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod,
773 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
774 /* Pull in device tunables. */
775 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
776 error = resource_int_value(device_get_name(sc->ale_dev),
777 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
778 if (error == 0) {
779 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
780 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
781 device_printf(sc->ale_dev, "int_rx_mod value out of "
782 "range; using default: %d\n",
783 ALE_IM_RX_TIMER_DEFAULT);
784 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
785 }
786 }
787 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
788 error = resource_int_value(device_get_name(sc->ale_dev),
789 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
790 if (error == 0) {
791 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
792 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
793 device_printf(sc->ale_dev, "int_tx_mod value out of "
794 "range; using default: %d\n",
795 ALE_IM_TX_TIMER_DEFAULT);
796 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
797 }
798 }
799 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
800 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
801 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I",
802 "max number of Rx events to process");
803 /* Pull in device tunables. */
804 sc->ale_process_limit = ALE_PROC_DEFAULT;
805 error = resource_int_value(device_get_name(sc->ale_dev),
806 device_get_unit(sc->ale_dev), "process_limit",
807 &sc->ale_process_limit);
808 if (error == 0) {
809 if (sc->ale_process_limit < ALE_PROC_MIN ||
810 sc->ale_process_limit > ALE_PROC_MAX) {
811 device_printf(sc->ale_dev,
812 "process_limit value out of range; "
813 "using default: %d\n", ALE_PROC_DEFAULT);
814 sc->ale_process_limit = ALE_PROC_DEFAULT;
815 }
816 }
817
818 /* Misc statistics. */
819 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
820 &stats->reset_brk_seq,
821 "Controller resets due to broken Rx sequnce number");
822
823 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
824 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics");
825 parent = SYSCTL_CHILDREN(tree);
826
827 /* Rx statistics. */
828 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
829 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
830 child = SYSCTL_CHILDREN(tree);
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
832 &stats->rx_frames, "Good frames");
833 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
834 &stats->rx_bcast_frames, "Good broadcast frames");
835 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
836 &stats->rx_mcast_frames, "Good multicast frames");
837 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
838 &stats->rx_pause_frames, "Pause control frames");
839 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
840 &stats->rx_control_frames, "Control frames");
841 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
842 &stats->rx_crcerrs, "CRC errors");
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
844 &stats->rx_lenerrs, "Frames with length mismatched");
845 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
846 &stats->rx_bytes, "Good octets");
847 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
848 &stats->rx_bcast_bytes, "Good broadcast octets");
849 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
850 &stats->rx_mcast_bytes, "Good multicast octets");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
852 &stats->rx_runts, "Too short frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
854 &stats->rx_fragments, "Fragmented frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
856 &stats->rx_pkts_64, "64 bytes frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
858 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
860 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
862 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
864 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
866 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
867 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
868 &stats->rx_pkts_1519_max, "1519 to max frames");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
870 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
871 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
872 &stats->rx_fifo_oflows, "FIFO overflows");
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
874 &stats->rx_rrs_errs, "Return status write-back errors");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
876 &stats->rx_alignerrs, "Alignment errors");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
878 &stats->rx_pkts_filtered,
879 "Frames dropped due to address filtering");
880
881 /* Tx statistics. */
882 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
883 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
884 child = SYSCTL_CHILDREN(tree);
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
886 &stats->tx_frames, "Good frames");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
888 &stats->tx_bcast_frames, "Good broadcast frames");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
890 &stats->tx_mcast_frames, "Good multicast frames");
891 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
892 &stats->tx_pause_frames, "Pause control frames");
893 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
894 &stats->tx_control_frames, "Control frames");
895 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
896 &stats->tx_excess_defer, "Frames with excessive derferrals");
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
898 &stats->tx_excess_defer, "Frames with derferrals");
899 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
900 &stats->tx_bytes, "Good octets");
901 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
902 &stats->tx_bcast_bytes, "Good broadcast octets");
903 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
904 &stats->tx_mcast_bytes, "Good multicast octets");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
906 &stats->tx_pkts_64, "64 bytes frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
908 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
910 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
912 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
914 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
916 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
918 &stats->tx_pkts_1519_max, "1519 to max frames");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
920 &stats->tx_single_colls, "Single collisions");
921 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
922 &stats->tx_multi_colls, "Multiple collisions");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
924 &stats->tx_late_colls, "Late collisions");
925 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
926 &stats->tx_excess_colls, "Excessive collisions");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
928 &stats->tx_underrun, "FIFO underruns");
929 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
930 &stats->tx_desc_underrun, "Descriptor write-back errors");
931 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
932 &stats->tx_lenerrs, "Frames with length mismatched");
933 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
934 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
935 }
936
937 #undef ALE_SYSCTL_STAT_ADD32
938 #undef ALE_SYSCTL_STAT_ADD64
939
940 struct ale_dmamap_arg {
941 bus_addr_t ale_busaddr;
942 };
943
944 static void
ale_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)945 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
946 {
947 struct ale_dmamap_arg *ctx;
948
949 if (error != 0)
950 return;
951
952 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
953
954 ctx = (struct ale_dmamap_arg *)arg;
955 ctx->ale_busaddr = segs[0].ds_addr;
956 }
957
958 /*
959 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
960 * which specifies high address region of DMA blocks. Therefore these
961 * blocks should have the same high address of given 4GB address
962 * space(i.e. crossing 4GB boundary is not allowed).
963 */
964 static int
ale_check_boundary(struct ale_softc * sc)965 ale_check_boundary(struct ale_softc *sc)
966 {
967 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
968 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
969
970 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
971 sc->ale_pagesize;
972 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
973 sc->ale_pagesize;
974 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
975 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
976 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
977 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
978
979 if ((ALE_ADDR_HI(tx_ring_end) !=
980 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
981 (ALE_ADDR_HI(rx_page_end[0]) !=
982 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
983 (ALE_ADDR_HI(rx_page_end[1]) !=
984 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
985 (ALE_ADDR_HI(tx_cmb_end) !=
986 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
987 (ALE_ADDR_HI(rx_cmb_end[0]) !=
988 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
989 (ALE_ADDR_HI(rx_cmb_end[1]) !=
990 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
991 return (EFBIG);
992
993 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
994 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
995 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
996 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
997 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
998 return (EFBIG);
999
1000 return (0);
1001 }
1002
1003 static int
ale_dma_alloc(struct ale_softc * sc)1004 ale_dma_alloc(struct ale_softc *sc)
1005 {
1006 struct ale_txdesc *txd;
1007 bus_addr_t lowaddr;
1008 struct ale_dmamap_arg ctx;
1009 int error, guard_size, i;
1010
1011 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1012 guard_size = ALE_JUMBO_FRAMELEN;
1013 else
1014 guard_size = ALE_MAX_FRAMELEN;
1015 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1016 ALE_RX_PAGE_ALIGN);
1017 lowaddr = BUS_SPACE_MAXADDR;
1018 again:
1019 /* Create parent DMA tag. */
1020 error = bus_dma_tag_create(
1021 bus_get_dma_tag(sc->ale_dev), /* parent */
1022 1, 0, /* alignment, boundary */
1023 lowaddr, /* lowaddr */
1024 BUS_SPACE_MAXADDR, /* highaddr */
1025 NULL, NULL, /* filter, filterarg */
1026 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1027 0, /* nsegments */
1028 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1029 0, /* flags */
1030 NULL, NULL, /* lockfunc, lockarg */
1031 &sc->ale_cdata.ale_parent_tag);
1032 if (error != 0) {
1033 device_printf(sc->ale_dev,
1034 "could not create parent DMA tag.\n");
1035 goto fail;
1036 }
1037
1038 /* Create DMA tag for Tx descriptor ring. */
1039 error = bus_dma_tag_create(
1040 sc->ale_cdata.ale_parent_tag, /* parent */
1041 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1042 BUS_SPACE_MAXADDR, /* lowaddr */
1043 BUS_SPACE_MAXADDR, /* highaddr */
1044 NULL, NULL, /* filter, filterarg */
1045 ALE_TX_RING_SZ, /* maxsize */
1046 1, /* nsegments */
1047 ALE_TX_RING_SZ, /* maxsegsize */
1048 0, /* flags */
1049 NULL, NULL, /* lockfunc, lockarg */
1050 &sc->ale_cdata.ale_tx_ring_tag);
1051 if (error != 0) {
1052 device_printf(sc->ale_dev,
1053 "could not create Tx ring DMA tag.\n");
1054 goto fail;
1055 }
1056
1057 /* Create DMA tag for Rx pages. */
1058 for (i = 0; i < ALE_RX_PAGES; i++) {
1059 error = bus_dma_tag_create(
1060 sc->ale_cdata.ale_parent_tag, /* parent */
1061 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1062 BUS_SPACE_MAXADDR, /* lowaddr */
1063 BUS_SPACE_MAXADDR, /* highaddr */
1064 NULL, NULL, /* filter, filterarg */
1065 sc->ale_pagesize, /* maxsize */
1066 1, /* nsegments */
1067 sc->ale_pagesize, /* maxsegsize */
1068 0, /* flags */
1069 NULL, NULL, /* lockfunc, lockarg */
1070 &sc->ale_cdata.ale_rx_page[i].page_tag);
1071 if (error != 0) {
1072 device_printf(sc->ale_dev,
1073 "could not create Rx page %d DMA tag.\n", i);
1074 goto fail;
1075 }
1076 }
1077
1078 /* Create DMA tag for Tx coalescing message block. */
1079 error = bus_dma_tag_create(
1080 sc->ale_cdata.ale_parent_tag, /* parent */
1081 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1082 BUS_SPACE_MAXADDR, /* lowaddr */
1083 BUS_SPACE_MAXADDR, /* highaddr */
1084 NULL, NULL, /* filter, filterarg */
1085 ALE_TX_CMB_SZ, /* maxsize */
1086 1, /* nsegments */
1087 ALE_TX_CMB_SZ, /* maxsegsize */
1088 0, /* flags */
1089 NULL, NULL, /* lockfunc, lockarg */
1090 &sc->ale_cdata.ale_tx_cmb_tag);
1091 if (error != 0) {
1092 device_printf(sc->ale_dev,
1093 "could not create Tx CMB DMA tag.\n");
1094 goto fail;
1095 }
1096
1097 /* Create DMA tag for Rx coalescing message block. */
1098 for (i = 0; i < ALE_RX_PAGES; i++) {
1099 error = bus_dma_tag_create(
1100 sc->ale_cdata.ale_parent_tag, /* parent */
1101 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1102 BUS_SPACE_MAXADDR, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, NULL, /* filter, filterarg */
1105 ALE_RX_CMB_SZ, /* maxsize */
1106 1, /* nsegments */
1107 ALE_RX_CMB_SZ, /* maxsegsize */
1108 0, /* flags */
1109 NULL, NULL, /* lockfunc, lockarg */
1110 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1111 if (error != 0) {
1112 device_printf(sc->ale_dev,
1113 "could not create Rx page %d CMB DMA tag.\n", i);
1114 goto fail;
1115 }
1116 }
1117
1118 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1119 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1120 (void **)&sc->ale_cdata.ale_tx_ring,
1121 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1122 &sc->ale_cdata.ale_tx_ring_map);
1123 if (error != 0) {
1124 device_printf(sc->ale_dev,
1125 "could not allocate DMA'able memory for Tx ring.\n");
1126 goto fail;
1127 }
1128 ctx.ale_busaddr = 0;
1129 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1130 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1131 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1132 if (error != 0 || ctx.ale_busaddr == 0) {
1133 device_printf(sc->ale_dev,
1134 "could not load DMA'able memory for Tx ring.\n");
1135 goto fail;
1136 }
1137 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1138
1139 /* Rx pages. */
1140 for (i = 0; i < ALE_RX_PAGES; i++) {
1141 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1142 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1144 &sc->ale_cdata.ale_rx_page[i].page_map);
1145 if (error != 0) {
1146 device_printf(sc->ale_dev,
1147 "could not allocate DMA'able memory for "
1148 "Rx page %d.\n", i);
1149 goto fail;
1150 }
1151 ctx.ale_busaddr = 0;
1152 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1153 sc->ale_cdata.ale_rx_page[i].page_map,
1154 sc->ale_cdata.ale_rx_page[i].page_addr,
1155 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1156 if (error != 0 || ctx.ale_busaddr == 0) {
1157 device_printf(sc->ale_dev,
1158 "could not load DMA'able memory for "
1159 "Rx page %d.\n", i);
1160 goto fail;
1161 }
1162 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1163 }
1164
1165 /* Tx CMB. */
1166 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1167 (void **)&sc->ale_cdata.ale_tx_cmb,
1168 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1169 &sc->ale_cdata.ale_tx_cmb_map);
1170 if (error != 0) {
1171 device_printf(sc->ale_dev,
1172 "could not allocate DMA'able memory for Tx CMB.\n");
1173 goto fail;
1174 }
1175 ctx.ale_busaddr = 0;
1176 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1177 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1178 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1179 if (error != 0 || ctx.ale_busaddr == 0) {
1180 device_printf(sc->ale_dev,
1181 "could not load DMA'able memory for Tx CMB.\n");
1182 goto fail;
1183 }
1184 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1185
1186 /* Rx CMB. */
1187 for (i = 0; i < ALE_RX_PAGES; i++) {
1188 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1189 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1190 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1191 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1192 if (error != 0) {
1193 device_printf(sc->ale_dev, "could not allocate "
1194 "DMA'able memory for Rx page %d CMB.\n", i);
1195 goto fail;
1196 }
1197 ctx.ale_busaddr = 0;
1198 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1199 sc->ale_cdata.ale_rx_page[i].cmb_map,
1200 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1201 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1202 if (error != 0 || ctx.ale_busaddr == 0) {
1203 device_printf(sc->ale_dev, "could not load DMA'able "
1204 "memory for Rx page %d CMB.\n", i);
1205 goto fail;
1206 }
1207 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1208 }
1209
1210 /*
1211 * Tx descriptors/RXF0/CMB DMA blocks share the same
1212 * high address region of 64bit DMA address space.
1213 */
1214 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1215 (error = ale_check_boundary(sc)) != 0) {
1216 device_printf(sc->ale_dev, "4GB boundary crossed, "
1217 "switching to 32bit DMA addressing mode.\n");
1218 ale_dma_free(sc);
1219 /*
1220 * Limit max allowable DMA address space to 32bit
1221 * and try again.
1222 */
1223 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1224 goto again;
1225 }
1226
1227 /*
1228 * Create Tx buffer parent tag.
1229 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1230 * needs separate parent DMA tag as parent DMA address space
1231 * could be restricted to be within 32bit address space by
1232 * 4GB boundary crossing.
1233 */
1234 error = bus_dma_tag_create(
1235 bus_get_dma_tag(sc->ale_dev), /* parent */
1236 1, 0, /* alignment, boundary */
1237 BUS_SPACE_MAXADDR, /* lowaddr */
1238 BUS_SPACE_MAXADDR, /* highaddr */
1239 NULL, NULL, /* filter, filterarg */
1240 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1241 0, /* nsegments */
1242 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1243 0, /* flags */
1244 NULL, NULL, /* lockfunc, lockarg */
1245 &sc->ale_cdata.ale_buffer_tag);
1246 if (error != 0) {
1247 device_printf(sc->ale_dev,
1248 "could not create parent buffer DMA tag.\n");
1249 goto fail;
1250 }
1251
1252 /* Create DMA tag for Tx buffers. */
1253 error = bus_dma_tag_create(
1254 sc->ale_cdata.ale_buffer_tag, /* parent */
1255 1, 0, /* alignment, boundary */
1256 BUS_SPACE_MAXADDR, /* lowaddr */
1257 BUS_SPACE_MAXADDR, /* highaddr */
1258 NULL, NULL, /* filter, filterarg */
1259 ALE_TSO_MAXSIZE, /* maxsize */
1260 ALE_MAXTXSEGS, /* nsegments */
1261 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1262 0, /* flags */
1263 NULL, NULL, /* lockfunc, lockarg */
1264 &sc->ale_cdata.ale_tx_tag);
1265 if (error != 0) {
1266 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1267 goto fail;
1268 }
1269
1270 /* Create DMA maps for Tx buffers. */
1271 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1272 txd = &sc->ale_cdata.ale_txdesc[i];
1273 txd->tx_m = NULL;
1274 txd->tx_dmamap = NULL;
1275 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1276 &txd->tx_dmamap);
1277 if (error != 0) {
1278 device_printf(sc->ale_dev,
1279 "could not create Tx dmamap.\n");
1280 goto fail;
1281 }
1282 }
1283
1284 fail:
1285 return (error);
1286 }
1287
1288 static void
ale_dma_free(struct ale_softc * sc)1289 ale_dma_free(struct ale_softc *sc)
1290 {
1291 struct ale_txdesc *txd;
1292 int i;
1293
1294 /* Tx buffers. */
1295 if (sc->ale_cdata.ale_tx_tag != NULL) {
1296 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1297 txd = &sc->ale_cdata.ale_txdesc[i];
1298 if (txd->tx_dmamap != NULL) {
1299 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1300 txd->tx_dmamap);
1301 txd->tx_dmamap = NULL;
1302 }
1303 }
1304 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1305 sc->ale_cdata.ale_tx_tag = NULL;
1306 }
1307 /* Tx descriptor ring. */
1308 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1309 if (sc->ale_cdata.ale_tx_ring_paddr != 0)
1310 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1311 sc->ale_cdata.ale_tx_ring_map);
1312 if (sc->ale_cdata.ale_tx_ring != NULL)
1313 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1314 sc->ale_cdata.ale_tx_ring,
1315 sc->ale_cdata.ale_tx_ring_map);
1316 sc->ale_cdata.ale_tx_ring_paddr = 0;
1317 sc->ale_cdata.ale_tx_ring = NULL;
1318 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1319 sc->ale_cdata.ale_tx_ring_tag = NULL;
1320 }
1321 /* Rx page block. */
1322 for (i = 0; i < ALE_RX_PAGES; i++) {
1323 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1324 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0)
1325 bus_dmamap_unload(
1326 sc->ale_cdata.ale_rx_page[i].page_tag,
1327 sc->ale_cdata.ale_rx_page[i].page_map);
1328 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1329 bus_dmamem_free(
1330 sc->ale_cdata.ale_rx_page[i].page_tag,
1331 sc->ale_cdata.ale_rx_page[i].page_addr,
1332 sc->ale_cdata.ale_rx_page[i].page_map);
1333 sc->ale_cdata.ale_rx_page[i].page_paddr = 0;
1334 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1335 bus_dma_tag_destroy(
1336 sc->ale_cdata.ale_rx_page[i].page_tag);
1337 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1338 }
1339 }
1340 /* Rx CMB. */
1341 for (i = 0; i < ALE_RX_PAGES; i++) {
1342 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1343 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0)
1344 bus_dmamap_unload(
1345 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1346 sc->ale_cdata.ale_rx_page[i].cmb_map);
1347 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1348 bus_dmamem_free(
1349 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1350 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1351 sc->ale_cdata.ale_rx_page[i].cmb_map);
1352 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0;
1353 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1354 bus_dma_tag_destroy(
1355 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1356 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1357 }
1358 }
1359 /* Tx CMB. */
1360 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1361 if (sc->ale_cdata.ale_tx_cmb_paddr != 0)
1362 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1363 sc->ale_cdata.ale_tx_cmb_map);
1364 if (sc->ale_cdata.ale_tx_cmb != NULL)
1365 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1366 sc->ale_cdata.ale_tx_cmb,
1367 sc->ale_cdata.ale_tx_cmb_map);
1368 sc->ale_cdata.ale_tx_cmb_paddr = 0;
1369 sc->ale_cdata.ale_tx_cmb = NULL;
1370 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1371 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1372 }
1373 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1374 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1375 sc->ale_cdata.ale_buffer_tag = NULL;
1376 }
1377 if (sc->ale_cdata.ale_parent_tag != NULL) {
1378 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1379 sc->ale_cdata.ale_parent_tag = NULL;
1380 }
1381 }
1382
1383 static int
ale_shutdown(device_t dev)1384 ale_shutdown(device_t dev)
1385 {
1386
1387 return (ale_suspend(dev));
1388 }
1389
1390 /*
1391 * Note, this driver resets the link speed to 10/100Mbps by
1392 * restarting auto-negotiation in suspend/shutdown phase but we
1393 * don't know whether that auto-negotiation would succeed or not
1394 * as driver has no control after powering off/suspend operation.
1395 * If the renegotiation fail WOL may not work. Running at 1Gbps
1396 * will draw more power than 375mA at 3.3V which is specified in
1397 * PCI specification and that would result in complete
1398 * shutdowning power to ethernet controller.
1399 *
1400 * TODO
1401 * Save current negotiated media speed/duplex/flow-control to
1402 * softc and restore the same link again after resuming. PHY
1403 * handling such as power down/resetting to 100Mbps may be better
1404 * handled in suspend method in phy driver.
1405 */
1406 static void
ale_setlinkspeed(struct ale_softc * sc)1407 ale_setlinkspeed(struct ale_softc *sc)
1408 {
1409 struct mii_data *mii;
1410 int aneg, i;
1411
1412 mii = device_get_softc(sc->ale_miibus);
1413 mii_pollstat(mii);
1414 aneg = 0;
1415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1416 (IFM_ACTIVE | IFM_AVALID)) {
1417 switch IFM_SUBTYPE(mii->mii_media_active) {
1418 case IFM_10_T:
1419 case IFM_100_TX:
1420 return;
1421 case IFM_1000_T:
1422 aneg++;
1423 break;
1424 default:
1425 break;
1426 }
1427 }
1428 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1430 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1432 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1433 DELAY(1000);
1434 if (aneg != 0) {
1435 /*
1436 * Poll link state until ale(4) get a 10/100Mbps link.
1437 */
1438 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1439 mii_pollstat(mii);
1440 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1441 == (IFM_ACTIVE | IFM_AVALID)) {
1442 switch (IFM_SUBTYPE(
1443 mii->mii_media_active)) {
1444 case IFM_10_T:
1445 case IFM_100_TX:
1446 ale_mac_config(sc);
1447 return;
1448 default:
1449 break;
1450 }
1451 }
1452 ALE_UNLOCK(sc);
1453 pause("alelnk", hz);
1454 ALE_LOCK(sc);
1455 }
1456 if (i == MII_ANEGTICKS_GIGE)
1457 device_printf(sc->ale_dev,
1458 "establishing a link failed, WOL may not work!");
1459 }
1460 /*
1461 * No link, force MAC to have 100Mbps, full-duplex link.
1462 * This is the last resort and may/may not work.
1463 */
1464 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1465 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1466 ale_mac_config(sc);
1467 }
1468
1469 static void
ale_setwol(struct ale_softc * sc)1470 ale_setwol(struct ale_softc *sc)
1471 {
1472 if_t ifp;
1473 uint32_t reg, pmcs;
1474
1475 ALE_LOCK_ASSERT(sc);
1476
1477 if (!pci_has_pm(sc->ale_dev)) {
1478 /* Disable WOL. */
1479 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1480 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1481 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1482 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1483 /* Force PHY power down. */
1484 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1485 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1486 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1487 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1488 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1489 return;
1490 }
1491
1492 ifp = sc->ale_ifp;
1493 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1494 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1495 ale_setlinkspeed(sc);
1496 }
1497
1498 pmcs = 0;
1499 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1500 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1501 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1502 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1503 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1504 MAC_CFG_BCAST);
1505 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1506 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1507 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1508 reg |= MAC_CFG_RX_ENB;
1509 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1510
1511 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1512 /* WOL disabled, PHY power down. */
1513 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1514 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1515 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1516 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1517 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1518 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1519 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1520 GPHY_CTRL_PWDOWN_HW);
1521 }
1522 /* Request PME. */
1523 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1524 pci_enable_pme(sc->ale_dev);
1525 }
1526
1527 static int
ale_suspend(device_t dev)1528 ale_suspend(device_t dev)
1529 {
1530 struct ale_softc *sc;
1531
1532 sc = device_get_softc(dev);
1533
1534 ALE_LOCK(sc);
1535 ale_stop(sc);
1536 ale_setwol(sc);
1537 ALE_UNLOCK(sc);
1538
1539 return (0);
1540 }
1541
1542 static int
ale_resume(device_t dev)1543 ale_resume(device_t dev)
1544 {
1545 struct ale_softc *sc;
1546 if_t ifp;
1547
1548 sc = device_get_softc(dev);
1549
1550 /* Reset PHY. */
1551 ALE_LOCK(sc);
1552 ale_phy_reset(sc);
1553 ifp = sc->ale_ifp;
1554 if ((if_getflags(ifp) & IFF_UP) != 0) {
1555 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1556 ale_init_locked(sc);
1557 }
1558 ALE_UNLOCK(sc);
1559
1560 return (0);
1561 }
1562
1563 static int
ale_encap(struct ale_softc * sc,struct mbuf ** m_head)1564 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1565 {
1566 struct ale_txdesc *txd, *txd_last;
1567 struct tx_desc *desc;
1568 struct mbuf *m;
1569 struct ip *ip;
1570 struct tcphdr *tcp;
1571 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1572 bus_dmamap_t map;
1573 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1574 int error, i, nsegs, prod, si;
1575
1576 ALE_LOCK_ASSERT(sc);
1577
1578 M_ASSERTPKTHDR((*m_head));
1579
1580 m = *m_head;
1581 ip = NULL;
1582 tcp = NULL;
1583 cflags = vtag = 0;
1584 ip_off = poff = 0;
1585 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1586 /*
1587 * AR81xx requires offset of TCP/UDP payload in its Tx
1588 * descriptor to perform hardware Tx checksum offload.
1589 * Additionally, TSO requires IP/TCP header size and
1590 * modification of IP/TCP header in order to make TSO
1591 * engine work. This kind of operation takes many CPU
1592 * cycles on FreeBSD so fast host CPU is required to
1593 * get smooth TSO performance.
1594 */
1595 struct ether_header *eh;
1596
1597 if (M_WRITABLE(m) == 0) {
1598 /* Get a writable copy. */
1599 m = m_dup(*m_head, M_NOWAIT);
1600 /* Release original mbufs. */
1601 m_freem(*m_head);
1602 if (m == NULL) {
1603 *m_head = NULL;
1604 return (ENOBUFS);
1605 }
1606 *m_head = m;
1607 }
1608
1609 /*
1610 * Buggy-controller requires 4 byte aligned Tx buffer
1611 * to make custom checksum offload work.
1612 */
1613 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1614 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1615 (mtod(m, intptr_t) & 3) != 0) {
1616 m = m_defrag(*m_head, M_NOWAIT);
1617 if (m == NULL) {
1618 m_freem(*m_head);
1619 *m_head = NULL;
1620 return (ENOBUFS);
1621 }
1622 *m_head = m;
1623 }
1624
1625 ip_off = sizeof(struct ether_header);
1626 m = m_pullup(m, ip_off);
1627 if (m == NULL) {
1628 *m_head = NULL;
1629 return (ENOBUFS);
1630 }
1631 eh = mtod(m, struct ether_header *);
1632 /*
1633 * Check if hardware VLAN insertion is off.
1634 * Additional check for LLC/SNAP frame?
1635 */
1636 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1637 ip_off = sizeof(struct ether_vlan_header);
1638 m = m_pullup(m, ip_off);
1639 if (m == NULL) {
1640 *m_head = NULL;
1641 return (ENOBUFS);
1642 }
1643 }
1644 m = m_pullup(m, ip_off + sizeof(struct ip));
1645 if (m == NULL) {
1646 *m_head = NULL;
1647 return (ENOBUFS);
1648 }
1649 ip = (struct ip *)(mtod(m, char *) + ip_off);
1650 poff = ip_off + (ip->ip_hl << 2);
1651 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1652 /*
1653 * XXX
1654 * AR81xx requires the first descriptor should
1655 * not include any TCP playload for TSO case.
1656 * (i.e. ethernet header + IP + TCP header only)
1657 * m_pullup(9) above will ensure this too.
1658 * However it's not correct if the first mbuf
1659 * of the chain does not use cluster.
1660 */
1661 m = m_pullup(m, poff + sizeof(struct tcphdr));
1662 if (m == NULL) {
1663 *m_head = NULL;
1664 return (ENOBUFS);
1665 }
1666 ip = (struct ip *)(mtod(m, char *) + ip_off);
1667 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1668 m = m_pullup(m, poff + (tcp->th_off << 2));
1669 if (m == NULL) {
1670 *m_head = NULL;
1671 return (ENOBUFS);
1672 }
1673 /*
1674 * AR81xx requires IP/TCP header size and offset as
1675 * well as TCP pseudo checksum which complicates
1676 * TSO configuration. I guess this comes from the
1677 * adherence to Microsoft NDIS Large Send
1678 * specification which requires insertion of
1679 * pseudo checksum by upper stack. The pseudo
1680 * checksum that NDIS refers to doesn't include
1681 * TCP payload length so ale(4) should recompute
1682 * the pseudo checksum here. Hopefully this wouldn't
1683 * be much burden on modern CPUs.
1684 * Reset IP checksum and recompute TCP pseudo
1685 * checksum as NDIS specification said.
1686 */
1687 ip->ip_sum = 0;
1688 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1689 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1690 }
1691 *m_head = m;
1692 }
1693
1694 si = prod = sc->ale_cdata.ale_tx_prod;
1695 txd = &sc->ale_cdata.ale_txdesc[prod];
1696 txd_last = txd;
1697 map = txd->tx_dmamap;
1698
1699 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1700 *m_head, txsegs, &nsegs, 0);
1701 if (error == EFBIG) {
1702 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1703 if (m == NULL) {
1704 m_freem(*m_head);
1705 *m_head = NULL;
1706 return (ENOMEM);
1707 }
1708 *m_head = m;
1709 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1710 *m_head, txsegs, &nsegs, 0);
1711 if (error != 0) {
1712 m_freem(*m_head);
1713 *m_head = NULL;
1714 return (error);
1715 }
1716 } else if (error != 0)
1717 return (error);
1718 if (nsegs == 0) {
1719 m_freem(*m_head);
1720 *m_head = NULL;
1721 return (EIO);
1722 }
1723
1724 /* Check descriptor overrun. */
1725 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1726 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1727 return (ENOBUFS);
1728 }
1729 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1730
1731 m = *m_head;
1732 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1733 /* Request TSO and set MSS. */
1734 cflags |= ALE_TD_TSO;
1735 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1736 /* Set IP/TCP header size. */
1737 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1738 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1739 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1740 /*
1741 * AR81xx supports Tx custom checksum offload feature
1742 * that offloads single 16bit checksum computation.
1743 * So you can choose one among IP, TCP and UDP.
1744 * Normally driver sets checksum start/insertion
1745 * position from the information of TCP/UDP frame as
1746 * TCP/UDP checksum takes more time than that of IP.
1747 * However it seems that custom checksum offload
1748 * requires 4 bytes aligned Tx buffers due to hardware
1749 * bug.
1750 * AR81xx also supports explicit Tx checksum computation
1751 * if it is told that the size of IP header and TCP
1752 * header(for UDP, the header size does not matter
1753 * because it's fixed length). However with this scheme
1754 * TSO does not work so you have to choose one either
1755 * TSO or explicit Tx checksum offload. I chosen TSO
1756 * plus custom checksum offload with work-around which
1757 * will cover most common usage for this consumer
1758 * ethernet controller. The work-around takes a lot of
1759 * CPU cycles if Tx buffer is not aligned on 4 bytes
1760 * boundary, though.
1761 */
1762 cflags |= ALE_TD_CXSUM;
1763 /* Set checksum start offset. */
1764 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1765 /* Set checksum insertion position of TCP/UDP. */
1766 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1767 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1768 }
1769
1770 /* Configure VLAN hardware tag insertion. */
1771 if ((m->m_flags & M_VLANTAG) != 0) {
1772 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1773 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1774 cflags |= ALE_TD_INSERT_VLAN_TAG;
1775 }
1776
1777 i = 0;
1778 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1779 /*
1780 * Make sure the first fragment contains
1781 * only ethernet and IP/TCP header with options.
1782 */
1783 hdrlen = poff + (tcp->th_off << 2);
1784 desc = &sc->ale_cdata.ale_tx_ring[prod];
1785 desc->addr = htole64(txsegs[i].ds_addr);
1786 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1787 desc->flags = htole32(cflags);
1788 sc->ale_cdata.ale_tx_cnt++;
1789 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1790 if (m->m_len - hdrlen > 0) {
1791 /* Handle remaining payload of the first fragment. */
1792 desc = &sc->ale_cdata.ale_tx_ring[prod];
1793 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1794 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1795 vtag);
1796 desc->flags = htole32(cflags);
1797 sc->ale_cdata.ale_tx_cnt++;
1798 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1799 }
1800 i = 1;
1801 }
1802 for (; i < nsegs; i++) {
1803 desc = &sc->ale_cdata.ale_tx_ring[prod];
1804 desc->addr = htole64(txsegs[i].ds_addr);
1805 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1806 desc->flags = htole32(cflags);
1807 sc->ale_cdata.ale_tx_cnt++;
1808 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1809 }
1810 /* Update producer index. */
1811 sc->ale_cdata.ale_tx_prod = prod;
1812 /* Set TSO header on the first descriptor. */
1813 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1814 desc = &sc->ale_cdata.ale_tx_ring[si];
1815 desc->flags |= htole32(ALE_TD_TSO_HDR);
1816 }
1817
1818 /* Finally set EOP on the last descriptor. */
1819 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1820 desc = &sc->ale_cdata.ale_tx_ring[prod];
1821 desc->flags |= htole32(ALE_TD_EOP);
1822
1823 /* Swap dmamap of the first and the last. */
1824 txd = &sc->ale_cdata.ale_txdesc[prod];
1825 map = txd_last->tx_dmamap;
1826 txd_last->tx_dmamap = txd->tx_dmamap;
1827 txd->tx_dmamap = map;
1828 txd->tx_m = m;
1829
1830 /* Sync descriptors. */
1831 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1832 sc->ale_cdata.ale_tx_ring_map,
1833 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1834
1835 return (0);
1836 }
1837
1838 static void
ale_start(if_t ifp)1839 ale_start(if_t ifp)
1840 {
1841 struct ale_softc *sc;
1842
1843 sc = if_getsoftc(ifp);
1844 ALE_LOCK(sc);
1845 ale_start_locked(ifp);
1846 ALE_UNLOCK(sc);
1847 }
1848
1849 static void
ale_start_locked(if_t ifp)1850 ale_start_locked(if_t ifp)
1851 {
1852 struct ale_softc *sc;
1853 struct mbuf *m_head;
1854 int enq;
1855
1856 sc = if_getsoftc(ifp);
1857
1858 ALE_LOCK_ASSERT(sc);
1859
1860 /* Reclaim transmitted frames. */
1861 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1862 ale_txeof(sc);
1863
1864 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1865 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1866 return;
1867
1868 for (enq = 0; !if_sendq_empty(ifp); ) {
1869 m_head = if_dequeue(ifp);
1870 if (m_head == NULL)
1871 break;
1872 /*
1873 * Pack the data into the transmit ring. If we
1874 * don't have room, set the OACTIVE flag and wait
1875 * for the NIC to drain the ring.
1876 */
1877 if (ale_encap(sc, &m_head)) {
1878 if (m_head == NULL)
1879 break;
1880 if_sendq_prepend(ifp, m_head);
1881 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1882 break;
1883 }
1884
1885 enq++;
1886 /*
1887 * If there's a BPF listener, bounce a copy of this frame
1888 * to him.
1889 */
1890 ETHER_BPF_MTAP(ifp, m_head);
1891 }
1892
1893 if (enq > 0) {
1894 /* Kick. */
1895 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1896 sc->ale_cdata.ale_tx_prod);
1897 /* Set a timeout in case the chip goes out to lunch. */
1898 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1899 }
1900 }
1901
1902 static void
ale_watchdog(struct ale_softc * sc)1903 ale_watchdog(struct ale_softc *sc)
1904 {
1905 if_t ifp;
1906
1907 ALE_LOCK_ASSERT(sc);
1908
1909 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1910 return;
1911
1912 ifp = sc->ale_ifp;
1913 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1914 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1915 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1916 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1917 ale_init_locked(sc);
1918 return;
1919 }
1920 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1921 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1922 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1923 ale_init_locked(sc);
1924 if (!if_sendq_empty(ifp))
1925 ale_start_locked(ifp);
1926 }
1927
1928 static int
ale_ioctl(if_t ifp,u_long cmd,caddr_t data)1929 ale_ioctl(if_t ifp, u_long cmd, caddr_t data)
1930 {
1931 struct ale_softc *sc;
1932 struct ifreq *ifr;
1933 struct mii_data *mii;
1934 int error, mask;
1935
1936 sc = if_getsoftc(ifp);
1937 ifr = (struct ifreq *)data;
1938 error = 0;
1939 switch (cmd) {
1940 case SIOCSIFMTU:
1941 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1942 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1943 ifr->ifr_mtu > ETHERMTU))
1944 error = EINVAL;
1945 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1946 ALE_LOCK(sc);
1947 if_setmtu(ifp, ifr->ifr_mtu);
1948 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1949 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1950 ale_init_locked(sc);
1951 }
1952 ALE_UNLOCK(sc);
1953 }
1954 break;
1955 case SIOCSIFFLAGS:
1956 ALE_LOCK(sc);
1957 if ((if_getflags(ifp) & IFF_UP) != 0) {
1958 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1959 if (((if_getflags(ifp) ^ sc->ale_if_flags)
1960 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1961 ale_rxfilter(sc);
1962 } else {
1963 ale_init_locked(sc);
1964 }
1965 } else {
1966 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1967 ale_stop(sc);
1968 }
1969 sc->ale_if_flags = if_getflags(ifp);
1970 ALE_UNLOCK(sc);
1971 break;
1972 case SIOCADDMULTI:
1973 case SIOCDELMULTI:
1974 ALE_LOCK(sc);
1975 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1976 ale_rxfilter(sc);
1977 ALE_UNLOCK(sc);
1978 break;
1979 case SIOCSIFMEDIA:
1980 case SIOCGIFMEDIA:
1981 mii = device_get_softc(sc->ale_miibus);
1982 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1983 break;
1984 case SIOCSIFCAP:
1985 ALE_LOCK(sc);
1986 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1987 if ((mask & IFCAP_TXCSUM) != 0 &&
1988 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1989 if_togglecapenable(ifp, IFCAP_TXCSUM);
1990 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1991 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0);
1992 else
1993 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES);
1994 }
1995 if ((mask & IFCAP_RXCSUM) != 0 &&
1996 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
1997 if_togglecapenable(ifp, IFCAP_RXCSUM);
1998 if ((mask & IFCAP_TSO4) != 0 &&
1999 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2000 if_togglecapenable(ifp, IFCAP_TSO4);
2001 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2002 if_sethwassistbits(ifp, CSUM_TSO, 0);
2003 else
2004 if_sethwassistbits(ifp, 0, CSUM_TSO);
2005 }
2006
2007 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2008 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
2009 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2010 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2011 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2012 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2013 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2014 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2015 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2016 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2017 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2018 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2019 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2020 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2021 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2022 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2023 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
2024 ale_rxvlan(sc);
2025 }
2026 ALE_UNLOCK(sc);
2027 VLAN_CAPABILITIES(ifp);
2028 break;
2029 default:
2030 error = ether_ioctl(ifp, cmd, data);
2031 break;
2032 }
2033
2034 return (error);
2035 }
2036
2037 static void
ale_mac_config(struct ale_softc * sc)2038 ale_mac_config(struct ale_softc *sc)
2039 {
2040 struct mii_data *mii;
2041 uint32_t reg;
2042
2043 ALE_LOCK_ASSERT(sc);
2044
2045 mii = device_get_softc(sc->ale_miibus);
2046 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2047 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2048 MAC_CFG_SPEED_MASK);
2049 /* Reprogram MAC with resolved speed/duplex. */
2050 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2051 case IFM_10_T:
2052 case IFM_100_TX:
2053 reg |= MAC_CFG_SPEED_10_100;
2054 break;
2055 case IFM_1000_T:
2056 reg |= MAC_CFG_SPEED_1000;
2057 break;
2058 }
2059 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2060 reg |= MAC_CFG_FULL_DUPLEX;
2061 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2062 reg |= MAC_CFG_TX_FC;
2063 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2064 reg |= MAC_CFG_RX_FC;
2065 }
2066 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2067 }
2068
2069 static void
ale_stats_clear(struct ale_softc * sc)2070 ale_stats_clear(struct ale_softc *sc)
2071 {
2072 struct smb sb;
2073 uint32_t *reg;
2074 int i;
2075
2076 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2077 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2078 i += sizeof(uint32_t);
2079 }
2080 /* Read Tx statistics. */
2081 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2082 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2083 i += sizeof(uint32_t);
2084 }
2085 }
2086
2087 static void
ale_stats_update(struct ale_softc * sc)2088 ale_stats_update(struct ale_softc *sc)
2089 {
2090 struct ale_hw_stats *stat;
2091 struct smb sb, *smb;
2092 if_t ifp;
2093 uint32_t *reg;
2094 int i;
2095
2096 ALE_LOCK_ASSERT(sc);
2097
2098 ifp = sc->ale_ifp;
2099 stat = &sc->ale_stats;
2100 smb = &sb;
2101
2102 /* Read Rx statistics. */
2103 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2104 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2105 i += sizeof(uint32_t);
2106 }
2107 /* Read Tx statistics. */
2108 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2109 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2110 i += sizeof(uint32_t);
2111 }
2112
2113 /* Rx stats. */
2114 stat->rx_frames += smb->rx_frames;
2115 stat->rx_bcast_frames += smb->rx_bcast_frames;
2116 stat->rx_mcast_frames += smb->rx_mcast_frames;
2117 stat->rx_pause_frames += smb->rx_pause_frames;
2118 stat->rx_control_frames += smb->rx_control_frames;
2119 stat->rx_crcerrs += smb->rx_crcerrs;
2120 stat->rx_lenerrs += smb->rx_lenerrs;
2121 stat->rx_bytes += smb->rx_bytes;
2122 stat->rx_runts += smb->rx_runts;
2123 stat->rx_fragments += smb->rx_fragments;
2124 stat->rx_pkts_64 += smb->rx_pkts_64;
2125 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2126 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2127 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2128 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2129 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2130 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2131 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2132 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2133 stat->rx_rrs_errs += smb->rx_rrs_errs;
2134 stat->rx_alignerrs += smb->rx_alignerrs;
2135 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2136 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2137 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2138
2139 /* Tx stats. */
2140 stat->tx_frames += smb->tx_frames;
2141 stat->tx_bcast_frames += smb->tx_bcast_frames;
2142 stat->tx_mcast_frames += smb->tx_mcast_frames;
2143 stat->tx_pause_frames += smb->tx_pause_frames;
2144 stat->tx_excess_defer += smb->tx_excess_defer;
2145 stat->tx_control_frames += smb->tx_control_frames;
2146 stat->tx_deferred += smb->tx_deferred;
2147 stat->tx_bytes += smb->tx_bytes;
2148 stat->tx_pkts_64 += smb->tx_pkts_64;
2149 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2150 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2151 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2152 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2153 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2154 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2155 stat->tx_single_colls += smb->tx_single_colls;
2156 stat->tx_multi_colls += smb->tx_multi_colls;
2157 stat->tx_late_colls += smb->tx_late_colls;
2158 stat->tx_excess_colls += smb->tx_excess_colls;
2159 stat->tx_underrun += smb->tx_underrun;
2160 stat->tx_desc_underrun += smb->tx_desc_underrun;
2161 stat->tx_lenerrs += smb->tx_lenerrs;
2162 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2163 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2164 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2165
2166 /* Update counters in ifnet. */
2167 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2168
2169 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2170 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2171 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2172
2173 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
2174 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
2175
2176 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2177
2178 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2179 smb->rx_crcerrs + smb->rx_lenerrs +
2180 smb->rx_runts + smb->rx_pkts_truncated +
2181 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2182 smb->rx_alignerrs);
2183 }
2184
2185 static int
ale_intr(void * arg)2186 ale_intr(void *arg)
2187 {
2188 struct ale_softc *sc;
2189 uint32_t status;
2190
2191 sc = (struct ale_softc *)arg;
2192
2193 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2194 if ((status & ALE_INTRS) == 0)
2195 return (FILTER_STRAY);
2196 /* Disable interrupts. */
2197 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2198 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2199
2200 return (FILTER_HANDLED);
2201 }
2202
2203 static void
ale_int_task(void * arg,int pending)2204 ale_int_task(void *arg, int pending)
2205 {
2206 struct ale_softc *sc;
2207 if_t ifp;
2208 uint32_t status;
2209 int more;
2210
2211 sc = (struct ale_softc *)arg;
2212
2213 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2214 ALE_LOCK(sc);
2215 if (sc->ale_morework != 0)
2216 status |= INTR_RX_PKT;
2217 if ((status & ALE_INTRS) == 0)
2218 goto done;
2219
2220 /* Acknowledge interrupts but still disable interrupts. */
2221 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2222
2223 ifp = sc->ale_ifp;
2224 more = 0;
2225 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2226 more = ale_rxeof(sc, sc->ale_process_limit);
2227 if (more == EAGAIN)
2228 sc->ale_morework = 1;
2229 else if (more == EIO) {
2230 sc->ale_stats.reset_brk_seq++;
2231 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2232 ale_init_locked(sc);
2233 ALE_UNLOCK(sc);
2234 return;
2235 }
2236
2237 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2238 if ((status & INTR_DMA_RD_TO_RST) != 0)
2239 device_printf(sc->ale_dev,
2240 "DMA read error! -- resetting\n");
2241 if ((status & INTR_DMA_WR_TO_RST) != 0)
2242 device_printf(sc->ale_dev,
2243 "DMA write error! -- resetting\n");
2244 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2245 ale_init_locked(sc);
2246 ALE_UNLOCK(sc);
2247 return;
2248 }
2249 if (!if_sendq_empty(ifp))
2250 ale_start_locked(ifp);
2251 }
2252
2253 if (more == EAGAIN ||
2254 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2255 ALE_UNLOCK(sc);
2256 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2257 return;
2258 }
2259
2260 done:
2261 ALE_UNLOCK(sc);
2262
2263 /* Re-enable interrupts. */
2264 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2265 }
2266
2267 static void
ale_txeof(struct ale_softc * sc)2268 ale_txeof(struct ale_softc *sc)
2269 {
2270 if_t ifp;
2271 struct ale_txdesc *txd;
2272 uint32_t cons, prod;
2273 int prog;
2274
2275 ALE_LOCK_ASSERT(sc);
2276
2277 ifp = sc->ale_ifp;
2278
2279 if (sc->ale_cdata.ale_tx_cnt == 0)
2280 return;
2281
2282 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2283 sc->ale_cdata.ale_tx_ring_map,
2284 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2285 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2286 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2287 sc->ale_cdata.ale_tx_cmb_map,
2288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2289 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2290 } else
2291 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2292 cons = sc->ale_cdata.ale_tx_cons;
2293 /*
2294 * Go through our Tx list and free mbufs for those
2295 * frames which have been transmitted.
2296 */
2297 for (prog = 0; cons != prod; prog++,
2298 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2299 if (sc->ale_cdata.ale_tx_cnt <= 0)
2300 break;
2301 prog++;
2302 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2303 sc->ale_cdata.ale_tx_cnt--;
2304 txd = &sc->ale_cdata.ale_txdesc[cons];
2305 if (txd->tx_m != NULL) {
2306 /* Reclaim transmitted mbufs. */
2307 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2308 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2309 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2310 txd->tx_dmamap);
2311 m_freem(txd->tx_m);
2312 txd->tx_m = NULL;
2313 }
2314 }
2315
2316 if (prog > 0) {
2317 sc->ale_cdata.ale_tx_cons = cons;
2318 /*
2319 * Unarm watchdog timer only when there is no pending
2320 * Tx descriptors in queue.
2321 */
2322 if (sc->ale_cdata.ale_tx_cnt == 0)
2323 sc->ale_watchdog_timer = 0;
2324 }
2325 }
2326
2327 static void
ale_rx_update_page(struct ale_softc * sc,struct ale_rx_page ** page,uint32_t length,uint32_t * prod)2328 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2329 uint32_t length, uint32_t *prod)
2330 {
2331 struct ale_rx_page *rx_page;
2332
2333 rx_page = *page;
2334 /* Update consumer position. */
2335 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2336 ALE_RX_PAGE_ALIGN);
2337 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2338 /*
2339 * End of Rx page reached, let hardware reuse
2340 * this page.
2341 */
2342 rx_page->cons = 0;
2343 *rx_page->cmb_addr = 0;
2344 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2345 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2346 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2347 RXF_VALID);
2348 /* Switch to alternate Rx page. */
2349 sc->ale_cdata.ale_rx_curp ^= 1;
2350 rx_page = *page =
2351 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2352 /* Page flipped, sync CMB and Rx page. */
2353 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2354 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2355 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2356 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2357 /* Sync completed, cache updated producer index. */
2358 *prod = *rx_page->cmb_addr;
2359 }
2360 }
2361
2362 /*
2363 * It seems that AR81xx controller can compute partial checksum.
2364 * The partial checksum value can be used to accelerate checksum
2365 * computation for fragmented TCP/UDP packets. Upper network stack
2366 * already takes advantage of the partial checksum value in IP
2367 * reassembly stage. But I'm not sure the correctness of the
2368 * partial hardware checksum assistance due to lack of data sheet.
2369 * In addition, the Rx feature of controller that requires copying
2370 * for every frames effectively nullifies one of most nice offload
2371 * capability of controller.
2372 */
2373 static void
ale_rxcsum(struct ale_softc * sc,struct mbuf * m,uint32_t status)2374 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2375 {
2376 if_t ifp;
2377 struct ip *ip;
2378 char *p;
2379
2380 ifp = sc->ale_ifp;
2381 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2382 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2383 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2384
2385 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2386 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2387 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2388 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2389 m->m_pkthdr.csum_flags |=
2390 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2391 m->m_pkthdr.csum_data = 0xffff;
2392 }
2393 } else {
2394 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2395 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2396 p = mtod(m, char *);
2397 p += ETHER_HDR_LEN;
2398 if ((status & ALE_RD_802_3) != 0)
2399 p += LLC_SNAPFRAMELEN;
2400 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 &&
2401 (status & ALE_RD_VLAN) != 0)
2402 p += ETHER_VLAN_ENCAP_LEN;
2403 ip = (struct ip *)p;
2404 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2405 return;
2406 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2407 CSUM_PSEUDO_HDR;
2408 m->m_pkthdr.csum_data = 0xffff;
2409 }
2410 }
2411 /*
2412 * Don't mark bad checksum for TCP/UDP frames
2413 * as fragmented frames may always have set
2414 * bad checksummed bit of frame status.
2415 */
2416 }
2417
2418 /* Process received frames. */
2419 static int
ale_rxeof(struct ale_softc * sc,int count)2420 ale_rxeof(struct ale_softc *sc, int count)
2421 {
2422 struct ale_rx_page *rx_page;
2423 struct rx_rs *rs;
2424 if_t ifp;
2425 struct mbuf *m;
2426 uint32_t length, prod, seqno, status, vtags;
2427 int prog;
2428
2429 ifp = sc->ale_ifp;
2430 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2431 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2433 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2435 /*
2436 * Don't directly access producer index as hardware may
2437 * update it while Rx handler is in progress. It would
2438 * be even better if there is a way to let hardware
2439 * know how far driver processed its received frames.
2440 * Alternatively, hardware could provide a way to disable
2441 * CMB updates until driver acknowledges the end of CMB
2442 * access.
2443 */
2444 prod = *rx_page->cmb_addr;
2445 for (prog = 0; prog < count; prog++) {
2446 if (rx_page->cons >= prod)
2447 break;
2448 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2449 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2450 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2451 /*
2452 * Normally I believe this should not happen unless
2453 * severe driver bug or corrupted memory. However
2454 * it seems to happen under certain conditions which
2455 * is triggered by abrupt Rx events such as initiation
2456 * of bulk transfer of remote host. It's not easy to
2457 * reproduce this and I doubt it could be related
2458 * with FIFO overflow of hardware or activity of Tx
2459 * CMB updates. I also remember similar behaviour
2460 * seen on RealTek 8139 which uses resembling Rx
2461 * scheme.
2462 */
2463 if (bootverbose)
2464 device_printf(sc->ale_dev,
2465 "garbled seq: %u, expected: %u -- "
2466 "resetting!\n", seqno,
2467 sc->ale_cdata.ale_rx_seqno);
2468 return (EIO);
2469 }
2470 /* Frame received. */
2471 sc->ale_cdata.ale_rx_seqno++;
2472 length = ALE_RX_BYTES(le32toh(rs->length));
2473 status = le32toh(rs->flags);
2474 if ((status & ALE_RD_ERROR) != 0) {
2475 /*
2476 * We want to pass the following frames to upper
2477 * layer regardless of error status of Rx return
2478 * status.
2479 *
2480 * o IP/TCP/UDP checksum is bad.
2481 * o frame length and protocol specific length
2482 * does not match.
2483 */
2484 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2485 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2486 ALE_RD_TRUNC)) != 0) {
2487 ale_rx_update_page(sc, &rx_page, length, &prod);
2488 continue;
2489 }
2490 }
2491 /*
2492 * m_devget(9) is major bottle-neck of ale(4)(It comes
2493 * from hardware limitation). For jumbo frames we could
2494 * get a slightly better performance if driver use
2495 * m_getjcl(9) with proper buffer size argument. However
2496 * that would make code more complicated and I don't
2497 * think users would expect good Rx performance numbers
2498 * on these low-end consumer ethernet controller.
2499 */
2500 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2501 ETHER_ALIGN, ifp, NULL);
2502 if (m == NULL) {
2503 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2504 ale_rx_update_page(sc, &rx_page, length, &prod);
2505 continue;
2506 }
2507 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2508 (status & ALE_RD_IPV4) != 0)
2509 ale_rxcsum(sc, m, status);
2510 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2511 (status & ALE_RD_VLAN) != 0) {
2512 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2513 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2514 m->m_flags |= M_VLANTAG;
2515 }
2516
2517 /* Pass it to upper layer. */
2518 ALE_UNLOCK(sc);
2519 if_input(ifp, m);
2520 ALE_LOCK(sc);
2521
2522 ale_rx_update_page(sc, &rx_page, length, &prod);
2523 }
2524
2525 return (count > 0 ? 0 : EAGAIN);
2526 }
2527
2528 static void
ale_tick(void * arg)2529 ale_tick(void *arg)
2530 {
2531 struct ale_softc *sc;
2532 struct mii_data *mii;
2533
2534 sc = (struct ale_softc *)arg;
2535
2536 ALE_LOCK_ASSERT(sc);
2537
2538 mii = device_get_softc(sc->ale_miibus);
2539 mii_tick(mii);
2540 ale_stats_update(sc);
2541 /*
2542 * Reclaim Tx buffers that have been transferred. It's not
2543 * needed here but it would release allocated mbuf chains
2544 * faster and limit the maximum delay to a hz.
2545 */
2546 ale_txeof(sc);
2547 ale_watchdog(sc);
2548 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2549 }
2550
2551 static void
ale_reset(struct ale_softc * sc)2552 ale_reset(struct ale_softc *sc)
2553 {
2554 uint32_t reg;
2555 int i;
2556
2557 /* Initialize PCIe module. From Linux. */
2558 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2559
2560 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2561 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2562 DELAY(10);
2563 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2564 break;
2565 }
2566 if (i == 0)
2567 device_printf(sc->ale_dev, "master reset timeout!\n");
2568
2569 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2570 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2571 break;
2572 DELAY(10);
2573 }
2574
2575 if (i == 0)
2576 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2577 }
2578
2579 static void
ale_init(void * xsc)2580 ale_init(void *xsc)
2581 {
2582 struct ale_softc *sc;
2583
2584 sc = (struct ale_softc *)xsc;
2585 ALE_LOCK(sc);
2586 ale_init_locked(sc);
2587 ALE_UNLOCK(sc);
2588 }
2589
2590 static void
ale_init_locked(struct ale_softc * sc)2591 ale_init_locked(struct ale_softc *sc)
2592 {
2593 if_t ifp;
2594 struct mii_data *mii;
2595 uint8_t eaddr[ETHER_ADDR_LEN];
2596 bus_addr_t paddr;
2597 uint32_t reg, rxf_hi, rxf_lo;
2598
2599 ALE_LOCK_ASSERT(sc);
2600
2601 ifp = sc->ale_ifp;
2602 mii = device_get_softc(sc->ale_miibus);
2603
2604 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2605 return;
2606 /*
2607 * Cancel any pending I/O.
2608 */
2609 ale_stop(sc);
2610 /*
2611 * Reset the chip to a known state.
2612 */
2613 ale_reset(sc);
2614 /* Initialize Tx descriptors, DMA memory blocks. */
2615 ale_init_rx_pages(sc);
2616 ale_init_tx_ring(sc);
2617
2618 /* Reprogram the station address. */
2619 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2620 CSR_WRITE_4(sc, ALE_PAR0,
2621 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2622 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2623 /*
2624 * Clear WOL status and disable all WOL feature as WOL
2625 * would interfere Rx operation under normal environments.
2626 */
2627 CSR_READ_4(sc, ALE_WOL_CFG);
2628 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2629 /*
2630 * Set Tx descriptor/RXF0/CMB base addresses. They share
2631 * the same high address part of DMAable region.
2632 */
2633 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2634 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2635 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2636 CSR_WRITE_4(sc, ALE_TPD_CNT,
2637 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2638 /* Set Rx page base address, note we use single queue. */
2639 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2640 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2641 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2642 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2643 /* Set Tx/Rx CMB addresses. */
2644 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2645 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2646 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2647 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2648 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2649 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2650 /* Mark RXF0 is valid. */
2651 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2652 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2653 /*
2654 * No need to initialize RFX1/RXF2/RXF3. We don't use
2655 * multi-queue yet.
2656 */
2657
2658 /* Set Rx page size, excluding guard frame size. */
2659 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2660 /* Tell hardware that we're ready to load DMA blocks. */
2661 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2662
2663 /* Set Rx/Tx interrupt trigger threshold. */
2664 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2665 (4 << INT_TRIG_TX_THRESH_SHIFT));
2666 /*
2667 * XXX
2668 * Set interrupt trigger timer, its purpose and relation
2669 * with interrupt moderation mechanism is not clear yet.
2670 */
2671 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2672 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2673 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2674
2675 /* Configure interrupt moderation timer. */
2676 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2677 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2678 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2679 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2680 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2681 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2682 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2683 reg |= MASTER_IM_RX_TIMER_ENB;
2684 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2685 reg |= MASTER_IM_TX_TIMER_ENB;
2686 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2687 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2688
2689 /* Set Maximum frame size of controller. */
2690 if (if_getmtu(ifp) < ETHERMTU)
2691 sc->ale_max_frame_size = ETHERMTU;
2692 else
2693 sc->ale_max_frame_size = if_getmtu(ifp);
2694 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2695 ETHER_CRC_LEN;
2696 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2697 /* Configure IPG/IFG parameters. */
2698 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2699 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2700 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2701 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2702 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2703 /* Set parameters for half-duplex media. */
2704 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2705 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2706 HDPX_CFG_LCOL_MASK) |
2707 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2708 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2709 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2710 HDPX_CFG_ABEBT_MASK) |
2711 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2712 HDPX_CFG_JAMIPG_MASK));
2713
2714 /* Configure Tx jumbo frame parameters. */
2715 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2716 if (if_getmtu(ifp) < ETHERMTU)
2717 reg = sc->ale_max_frame_size;
2718 else if (if_getmtu(ifp) < 6 * 1024)
2719 reg = (sc->ale_max_frame_size * 2) / 3;
2720 else
2721 reg = sc->ale_max_frame_size / 2;
2722 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2723 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2724 TX_JUMBO_THRESH_UNIT_SHIFT);
2725 }
2726 /* Configure TxQ. */
2727 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2728 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2729 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2730 TXQ_CFG_TPD_BURST_MASK;
2731 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2732
2733 /* Configure Rx jumbo frame & flow control parameters. */
2734 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2735 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2736 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2737 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2738 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2739 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2740 RX_JUMBO_LKAH_MASK));
2741 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2742 rxf_hi = (reg * 7) / 10;
2743 rxf_lo = (reg * 3)/ 10;
2744 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2745 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2746 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2747 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2748 RX_FIFO_PAUSE_THRESH_HI_MASK));
2749 }
2750
2751 /* Disable RSS. */
2752 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2753 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2754
2755 /* Configure RxQ. */
2756 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2757 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2758
2759 /* Configure DMA parameters. */
2760 reg = 0;
2761 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2762 reg |= DMA_CFG_TXCMB_ENB;
2763 CSR_WRITE_4(sc, ALE_DMA_CFG,
2764 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2765 sc->ale_dma_rd_burst | reg |
2766 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2767 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2768 DMA_CFG_RD_DELAY_CNT_MASK) |
2769 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2770 DMA_CFG_WR_DELAY_CNT_MASK));
2771
2772 /*
2773 * Hardware can be configured to issue SMB interrupt based
2774 * on programmed interval. Since there is a callout that is
2775 * invoked for every hz in driver we use that instead of
2776 * relying on periodic SMB interrupt.
2777 */
2778 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2779 /* Clear MAC statistics. */
2780 ale_stats_clear(sc);
2781
2782 /*
2783 * Configure Tx/Rx MACs.
2784 * - Auto-padding for short frames.
2785 * - Enable CRC generation.
2786 * Actual reconfiguration of MAC for resolved speed/duplex
2787 * is followed after detection of link establishment.
2788 * AR81xx always does checksum computation regardless of
2789 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2790 * cause Rx handling issue for fragmented IP datagrams due
2791 * to silicon bug.
2792 */
2793 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2794 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2795 MAC_CFG_PREAMBLE_MASK);
2796 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2797 reg |= MAC_CFG_SPEED_10_100;
2798 else
2799 reg |= MAC_CFG_SPEED_1000;
2800 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2801
2802 /* Set up the receive filter. */
2803 ale_rxfilter(sc);
2804 ale_rxvlan(sc);
2805
2806 /* Acknowledge all pending interrupts and clear it. */
2807 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2808 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2809 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2810
2811 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2812 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2813
2814 sc->ale_flags &= ~ALE_FLAG_LINK;
2815 /* Switch to the current media. */
2816 mii_mediachg(mii);
2817
2818 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2819 }
2820
2821 static void
ale_stop(struct ale_softc * sc)2822 ale_stop(struct ale_softc *sc)
2823 {
2824 if_t ifp;
2825 struct ale_txdesc *txd;
2826 uint32_t reg;
2827 int i;
2828
2829 ALE_LOCK_ASSERT(sc);
2830 /*
2831 * Mark the interface down and cancel the watchdog timer.
2832 */
2833 ifp = sc->ale_ifp;
2834 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2835 sc->ale_flags &= ~ALE_FLAG_LINK;
2836 callout_stop(&sc->ale_tick_ch);
2837 sc->ale_watchdog_timer = 0;
2838 ale_stats_update(sc);
2839 /* Disable interrupts. */
2840 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2841 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2842 /* Disable queue processing and DMA. */
2843 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2844 reg &= ~TXQ_CFG_ENB;
2845 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2846 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2847 reg &= ~RXQ_CFG_ENB;
2848 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2849 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2850 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2851 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2852 DELAY(1000);
2853 /* Stop Rx/Tx MACs. */
2854 ale_stop_mac(sc);
2855 /* Disable interrupts which might be touched in taskq handler. */
2856 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2857
2858 /*
2859 * Free TX mbufs still in the queues.
2860 */
2861 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2862 txd = &sc->ale_cdata.ale_txdesc[i];
2863 if (txd->tx_m != NULL) {
2864 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2865 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2866 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2867 txd->tx_dmamap);
2868 m_freem(txd->tx_m);
2869 txd->tx_m = NULL;
2870 }
2871 }
2872 }
2873
2874 static void
ale_stop_mac(struct ale_softc * sc)2875 ale_stop_mac(struct ale_softc *sc)
2876 {
2877 uint32_t reg;
2878 int i;
2879
2880 ALE_LOCK_ASSERT(sc);
2881
2882 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2883 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2884 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2885 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2886 }
2887
2888 for (i = ALE_TIMEOUT; i > 0; i--) {
2889 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2890 if (reg == 0)
2891 break;
2892 DELAY(10);
2893 }
2894 if (i == 0)
2895 device_printf(sc->ale_dev,
2896 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2897 }
2898
2899 static void
ale_init_tx_ring(struct ale_softc * sc)2900 ale_init_tx_ring(struct ale_softc *sc)
2901 {
2902 struct ale_txdesc *txd;
2903 int i;
2904
2905 ALE_LOCK_ASSERT(sc);
2906
2907 sc->ale_cdata.ale_tx_prod = 0;
2908 sc->ale_cdata.ale_tx_cons = 0;
2909 sc->ale_cdata.ale_tx_cnt = 0;
2910
2911 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2912 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2913 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2914 txd = &sc->ale_cdata.ale_txdesc[i];
2915 txd->tx_m = NULL;
2916 }
2917 *sc->ale_cdata.ale_tx_cmb = 0;
2918 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2919 sc->ale_cdata.ale_tx_cmb_map,
2920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2921 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2922 sc->ale_cdata.ale_tx_ring_map,
2923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2924 }
2925
2926 static void
ale_init_rx_pages(struct ale_softc * sc)2927 ale_init_rx_pages(struct ale_softc *sc)
2928 {
2929 struct ale_rx_page *rx_page;
2930 int i;
2931
2932 ALE_LOCK_ASSERT(sc);
2933
2934 sc->ale_morework = 0;
2935 sc->ale_cdata.ale_rx_seqno = 0;
2936 sc->ale_cdata.ale_rx_curp = 0;
2937
2938 for (i = 0; i < ALE_RX_PAGES; i++) {
2939 rx_page = &sc->ale_cdata.ale_rx_page[i];
2940 bzero(rx_page->page_addr, sc->ale_pagesize);
2941 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2942 rx_page->cons = 0;
2943 *rx_page->cmb_addr = 0;
2944 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2946 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2947 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2948 }
2949 }
2950
2951 static void
ale_rxvlan(struct ale_softc * sc)2952 ale_rxvlan(struct ale_softc *sc)
2953 {
2954 if_t ifp;
2955 uint32_t reg;
2956
2957 ALE_LOCK_ASSERT(sc);
2958
2959 ifp = sc->ale_ifp;
2960 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2961 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2962 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2963 reg |= MAC_CFG_VLAN_TAG_STRIP;
2964 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2965 }
2966
2967 static u_int
ale_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2968 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2969 {
2970 uint32_t crc, *mchash = arg;
2971
2972 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
2973 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2974
2975 return (1);
2976 }
2977
2978 static void
ale_rxfilter(struct ale_softc * sc)2979 ale_rxfilter(struct ale_softc *sc)
2980 {
2981 if_t ifp;
2982 uint32_t mchash[2];
2983 uint32_t rxcfg;
2984
2985 ALE_LOCK_ASSERT(sc);
2986
2987 ifp = sc->ale_ifp;
2988
2989 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
2990 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2991 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
2992 rxcfg |= MAC_CFG_BCAST;
2993 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2994 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
2995 rxcfg |= MAC_CFG_PROMISC;
2996 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
2997 rxcfg |= MAC_CFG_ALLMULTI;
2998 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
2999 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3000 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3001 return;
3002 }
3003
3004 /* Program new filter. */
3005 bzero(mchash, sizeof(mchash));
3006 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash);
3007
3008 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3009 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3010 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3011 }
3012
3013 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3014 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3015 {
3016 int error, value;
3017
3018 if (arg1 == NULL)
3019 return (EINVAL);
3020 value = *(int *)arg1;
3021 error = sysctl_handle_int(oidp, &value, 0, req);
3022 if (error || req->newptr == NULL)
3023 return (error);
3024 if (value < low || value > high)
3025 return (EINVAL);
3026 *(int *)arg1 = value;
3027
3028 return (0);
3029 }
3030
3031 static int
sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)3032 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3033 {
3034 return (sysctl_int_range(oidp, arg1, arg2, req,
3035 ALE_PROC_MIN, ALE_PROC_MAX));
3036 }
3037
3038 static int
sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)3039 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3040 {
3041
3042 return (sysctl_int_range(oidp, arg1, arg2, req,
3043 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
3044 }
3045