1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "include/gpio_types.h"
28 #include "../hw_factory.h"
29
30 #include "hw_factory_dce80.h"
31
32 #include "../hw_gpio.h"
33 #include "../hw_ddc.h"
34 #include "../hw_hpd.h"
35
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
38
39 #define REG(reg_name)\
40 mm ## reg_name
41
42 #include "reg_helper.h"
43 #include "../hpd_regs.h"
44
45 #define HPD_REG_LIST_DCE8(id) \
46 HPD_GPIO_REG_LIST(id), \
47 .int_status = mmDC_HPD ## id ## _INT_STATUS,\
48 .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
49
50 #define HPD_MASK_SH_LIST_DCE8(mask_sh) \
51 .DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
52 .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
53 .DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
54 .DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
55
56 #define hpd_regs(id) \
57 {\
58 HPD_REG_LIST_DCE8(id)\
59 }
60
61 static const struct hpd_registers hpd_regs[] = {
62 hpd_regs(1),
63 hpd_regs(2),
64 hpd_regs(3),
65 hpd_regs(4),
66 hpd_regs(5),
67 hpd_regs(6)
68 };
69
70 static const struct hpd_sh_mask hpd_shift = {
71 HPD_MASK_SH_LIST_DCE8(__SHIFT)
72 };
73
74 static const struct hpd_sh_mask hpd_mask = {
75 HPD_MASK_SH_LIST_DCE8(_MASK)
76 };
77
78 #include "../ddc_regs.h"
79
80 /* set field name */
81 #define SF_DDC(reg_name, field_name, post_fix)\
82 .field_name = reg_name ## __ ## field_name ## post_fix
83
84 static const struct ddc_registers ddc_data_regs[] = {
85 ddc_data_regs(1),
86 ddc_data_regs(2),
87 ddc_data_regs(3),
88 ddc_data_regs(4),
89 ddc_data_regs(5),
90 ddc_data_regs(6),
91 ddc_vga_data_regs,
92 ddc_i2c_data_regs
93 };
94
95 static const struct ddc_registers ddc_clk_regs[] = {
96 ddc_clk_regs(1),
97 ddc_clk_regs(2),
98 ddc_clk_regs(3),
99 ddc_clk_regs(4),
100 ddc_clk_regs(5),
101 ddc_clk_regs(6),
102 ddc_vga_clk_regs,
103 ddc_i2c_clk_regs
104 };
105
106 static const struct ddc_sh_mask ddc_shift = {
107 DDC_MASK_SH_LIST(__SHIFT)
108 };
109
110 static const struct ddc_sh_mask ddc_mask = {
111 DDC_MASK_SH_LIST(_MASK)
112 };
113
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)114 static void define_ddc_registers(
115 struct hw_gpio_pin *pin,
116 uint32_t en)
117 {
118 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
119
120 switch (pin->id) {
121 case GPIO_ID_DDC_DATA:
122 ddc->regs = &ddc_data_regs[en];
123 ddc->base.regs = &ddc_data_regs[en].gpio;
124 break;
125 case GPIO_ID_DDC_CLOCK:
126 ddc->regs = &ddc_clk_regs[en];
127 ddc->base.regs = &ddc_clk_regs[en].gpio;
128 break;
129 default:
130 ASSERT_CRITICAL(false);
131 return;
132 }
133
134 ddc->shifts = &ddc_shift;
135 ddc->masks = &ddc_mask;
136
137 }
138
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)139 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
140 {
141 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
142
143 hpd->regs = &hpd_regs[en];
144 hpd->shifts = &hpd_shift;
145 hpd->masks = &hpd_mask;
146 hpd->base.regs = &hpd_regs[en].gpio;
147 }
148
149 static const struct hw_factory_funcs funcs = {
150 .create_ddc_data = dal_hw_ddc_create,
151 .create_ddc_clock = dal_hw_ddc_create,
152 .create_generic = NULL,
153 .create_hpd = dal_hw_hpd_create,
154 .create_sync = NULL,
155 .create_gsl = NULL,
156 .define_hpd_registers = define_hpd_registers,
157 .define_ddc_registers = define_ddc_registers
158 };
159
dal_hw_factory_dce80_init(struct hw_factory * factory)160 void dal_hw_factory_dce80_init(
161 struct hw_factory *factory)
162 {
163 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
164 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
165 factory->number_of_pins[GPIO_ID_GENERIC] = 7;
166 factory->number_of_pins[GPIO_ID_HPD] = 6;
167 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
168 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
169 factory->number_of_pins[GPIO_ID_SYNC] = 2;
170 factory->number_of_pins[GPIO_ID_GSL] = 4;
171
172 factory->funcs = &funcs;
173 }
174