1 /*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Samsung Exynos 5 Interrupt Combiner
29 * Chapter 7, Exynos 5 Dual User's Manual Public Rev 1.00
30 */
31 #ifdef USB_GLOBAL_INCLUDE_FILE
32 #include USB_GLOBAL_INCLUDE_FILE
33 #else
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/rman.h>
44 #include <sys/timeet.h>
45 #include <sys/timetc.h>
46 #include <sys/watchdog.h>
47
48 #include <dev/ofw/openfirm.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51
52 #include <machine/bus.h>
53 #include <machine/cpu.h>
54 #include <machine/intr.h>
55 #endif
56
57 #include <arm/samsung/exynos/exynos5_common.h>
58 #include <arm/samsung/exynos/exynos5_combiner.h>
59
60 #define NGRP 32
61
62 #define IESR(n) (0x10 * n + 0x0) /* Interrupt enable set */
63 #define IECR(n) (0x10 * n + 0x4) /* Interrupt enable clear */
64 #define ISTR(n) (0x10 * n + 0x8) /* Interrupt status */
65 #define IMSR(n) (0x10 * n + 0xC) /* Interrupt masked status */
66 #define CIPSR 0x100 /* Combined interrupt pending */
67
68 struct combiner_softc {
69 struct resource *res[1 + NGRP];
70 bus_space_tag_t bst;
71 bus_space_handle_t bsh;
72 void *ih[NGRP];
73 device_t dev;
74 };
75
76 struct combiner_softc *combiner_sc;
77
78 static struct resource_spec combiner_spec[] = {
79 { SYS_RES_MEMORY, 0, RF_ACTIVE },
80 { SYS_RES_IRQ, 0, RF_ACTIVE },
81 { SYS_RES_IRQ, 1, RF_ACTIVE },
82 { SYS_RES_IRQ, 2, RF_ACTIVE },
83 { SYS_RES_IRQ, 3, RF_ACTIVE },
84 { SYS_RES_IRQ, 4, RF_ACTIVE },
85 { SYS_RES_IRQ, 5, RF_ACTIVE },
86 { SYS_RES_IRQ, 6, RF_ACTIVE },
87 { SYS_RES_IRQ, 7, RF_ACTIVE },
88 { SYS_RES_IRQ, 8, RF_ACTIVE },
89 { SYS_RES_IRQ, 9, RF_ACTIVE },
90 { SYS_RES_IRQ, 10, RF_ACTIVE },
91 { SYS_RES_IRQ, 11, RF_ACTIVE },
92 { SYS_RES_IRQ, 12, RF_ACTIVE },
93 { SYS_RES_IRQ, 13, RF_ACTIVE },
94 { SYS_RES_IRQ, 14, RF_ACTIVE },
95 { SYS_RES_IRQ, 15, RF_ACTIVE },
96 { SYS_RES_IRQ, 16, RF_ACTIVE },
97 { SYS_RES_IRQ, 17, RF_ACTIVE },
98 { SYS_RES_IRQ, 18, RF_ACTIVE },
99 { SYS_RES_IRQ, 19, RF_ACTIVE },
100 { SYS_RES_IRQ, 20, RF_ACTIVE },
101 { SYS_RES_IRQ, 21, RF_ACTIVE },
102 { SYS_RES_IRQ, 22, RF_ACTIVE },
103 { SYS_RES_IRQ, 23, RF_ACTIVE },
104 { SYS_RES_IRQ, 24, RF_ACTIVE },
105 { SYS_RES_IRQ, 25, RF_ACTIVE },
106 { SYS_RES_IRQ, 26, RF_ACTIVE },
107 { SYS_RES_IRQ, 27, RF_ACTIVE },
108 { SYS_RES_IRQ, 28, RF_ACTIVE },
109 { SYS_RES_IRQ, 29, RF_ACTIVE },
110 { SYS_RES_IRQ, 30, RF_ACTIVE },
111 { SYS_RES_IRQ, 31, RF_ACTIVE },
112 { -1, 0 }
113 };
114
115 struct combiner_entry {
116 int combiner_id;
117 int bit;
118 char *source_name;
119 };
120
121 static struct combiner_entry interrupt_table[] = {
122 { 63, 1, "EINT[15]" },
123 { 63, 0, "EINT[14]" },
124 { 62, 1, "EINT[13]" },
125 { 62, 0, "EINT[12]" },
126 { 61, 1, "EINT[11]" },
127 { 61, 0, "EINT[10]" },
128 { 60, 1, "EINT[9]" },
129 { 60, 0, "EINT[8]" },
130 { 59, 1, "EINT[7]" },
131 { 59, 0, "EINT[6]" },
132 { 58, 1, "EINT[5]" },
133 { 58, 0, "EINT[4]" },
134 { 57, 3, "MCT_G3" },
135 { 57, 2, "MCT_G2" },
136 { 57, 1, "EINT[3]" },
137 { 57, 0, "EINT[2]" },
138 { 56, 6, "SYSMMU_G2D[1]" },
139 { 56, 5, "SYSMMU_G2D[0]" },
140 { 56, 2, "SYSMMU_FIMC_LITE1[1]" },
141 { 56, 1, "SYSMMU_FIMC_LITE1[0]" },
142 { 56, 0, "EINT[1]" },
143 { 55, 4, "MCT_G1" },
144 { 55, 3, "MCT_G0" },
145 { 55, 0, "EINT[0]" },
146 { 54, 7, "CPU_nCNTVIRQ[1]" },
147 { 54, 6, "CPU_nCTIIRQ[1]" },
148 { 54, 5, "CPU_nCNTPSIRQ[1]" },
149 { 54, 4, "CPU_nPMUIRQ[1]" },
150 { 54, 3, "CPU_nCNTPNSIRQ[1]" },
151 { 54, 2, "CPU_PARITYFAILSCU[1]" },
152 { 54, 1, "CPU_nCNTHPIRQ[1]" },
153 { 54, 0, "PARITYFAIL[1]" },
154 { 53, 1, "CPU_nIRQ[1]" },
155 { 52, 0, "CPU_nIRQ[0]" },
156 { 51, 7, "CPU_nRAMERRIRQ" },
157 { 51, 6, "CPU_nAXIERRIRQ" },
158 { 51, 4, "INT_COMB_ISP_GIC" },
159 { 51, 3, "INT_COMB_IOP_GIC" },
160 { 51, 2, "CCI_nERRORIRQ" },
161 { 51, 1, "INT_COMB_ARMISP_GIC" },
162 { 51, 0, "INT_COMB_ARMIOP_GIC" },
163 { 50, 7, "DISP1[3]" },
164 { 50, 6, "DISP1[2]" },
165 { 50, 5, "DISP1[1]" },
166 { 50, 4, "DISP1[0]" },
167 { 49, 3, "SSCM_PULSE_IRQ_C2CIF[1]" },
168 { 49, 2, "SSCM_PULSE_IRQ_C2CIF[0]" },
169 { 49, 1, "SSCM_IRQ_C2CIF[1]" },
170 { 49, 0, "SSCM_IRQ_C2CIF[0]" },
171 { 48, 3, "PEREV_M1_CDREX" },
172 { 48, 2, "PEREV_M0_CDREX" },
173 { 48, 1, "PEREV_A1_CDREX" },
174 { 48, 0, "PEREV_A0_CDREX" },
175 { 47, 3, "MDMA0_ABORT" },
176 /* 46 is fully reserved */
177 { 45, 1, "MDMA1_ABORT" },
178 /* 44 is fully reserved */
179 { 43, 7, "SYSMMU_DRCISP[1]" },
180 { 43, 6, "SYSMMU_DRCISP[0]" },
181 { 43, 1, "SYSMMU_ODC[1]" },
182 { 43, 0, "SYSMMU_ODC[0]" },
183 { 42, 7, "SYSMMU_ISP[1]" },
184 { 42, 6, "SYSMMU_ISP[0]" },
185 { 42, 5, "SYSMMU_DIS0[1]" },
186 { 42, 4, "SYSMMU_DIS0[0]" },
187 { 42, 3, "DP1" },
188 { 41, 5, "SYSMMU_DIS1[1]" },
189 { 41, 4, "SYSMMU_DIS1[0]" },
190 { 40, 6, "SYSMMU_MFCL[1]" },
191 { 40, 5, "SYSMMU_MFCL[0]" },
192 { 39, 5, "SYSMMU_TV_M0[1]" },
193 { 39, 4, "SYSMMU_TV_M0[0]" },
194 { 39, 3, "SYSMMU_MDMA1[1]" },
195 { 39, 2, "SYSMMU_MDMA1[0]" },
196 { 39, 1, "SYSMMU_MDMA0[1]" },
197 { 39, 0, "SYSMMU_MDMA0[0]" },
198 { 38, 7, "SYSMMU_SSS[1]" },
199 { 38, 6, "SYSMMU_SSS[0]" },
200 { 38, 5, "SYSMMU_RTIC[1]" },
201 { 38, 4, "SYSMMU_RTIC[0]" },
202 { 38, 3, "SYSMMU_MFCR[1]" },
203 { 38, 2, "SYSMMU_MFCR[0]" },
204 { 38, 1, "SYSMMU_ARM[1]" },
205 { 38, 0, "SYSMMU_ARM[0]" },
206 { 37, 7, "SYSMMU_3DNR[1]" },
207 { 37, 6, "SYSMMU_3DNR[0]" },
208 { 37, 5, "SYSMMU_MCUISP[1]" },
209 { 37, 4, "SYSMMU_MCUISP[0]" },
210 { 37, 3, "SYSMMU_SCALERCISP[1]" },
211 { 37, 2, "SYSMMU_SCALERCISP[0]" },
212 { 37, 1, "SYSMMU_FDISP[1]" },
213 { 37, 0, "SYSMMU_FDISP[0]" },
214 { 36, 7, "MCUIOP_CTIIRQ" },
215 { 36, 6, "MCUIOP_PMUIRQ" },
216 { 36, 5, "MCUISP_CTIIRQ" },
217 { 36, 4, "MCUISP_PMUIRQ" },
218 { 36, 3, "SYSMMU_JPEGX[1]" },
219 { 36, 2, "SYSMMU_JPEGX[0]" },
220 { 36, 1, "SYSMMU_ROTATOR[1]" },
221 { 36, 0, "SYSMMU_ROTATOR[0]" },
222 { 35, 7, "SYSMMU_SCALERPISP[1]" },
223 { 35, 6, "SYSMMU_SCALERPISP[0]" },
224 { 35, 5, "SYSMMU_FIMC_LITE0[1]" },
225 { 35, 4, "SYSMMU_FIMC_LITE0[0]" },
226 { 35, 3, "SYSMMU_DISP1_M0[1]" },
227 { 35, 2, "SYSMMU_DISP1_M0[0]" },
228 { 35, 1, "SYSMMU_FIMC_LITE2[1]" },
229 { 35, 0, "SYSMMU_FIMC_LITE2[0]" },
230 { 34, 7, "SYSMMU_GSCL3[1]" },
231 { 34, 6, "SYSMMU_GSCL3[0]" },
232 { 34, 5, "SYSMMU_GSCL2[1]" },
233 { 34, 4, "SYSMMU_GSCL2[0]" },
234 { 34, 3, "SYSMMU_GSCL1[1]" },
235 { 34, 2, "SYSMMU_GSCL1[0]" },
236 { 34, 1, "SYSMMU_GSCL0[1]" },
237 { 34, 0, "SYSMMU_GSCL0[0]" },
238 { 33, 7, "CPU_nCNTVIRQ[0]" },
239 { 33, 6, "CPU_nCNTPSIRQ[0]" },
240 { 33, 5, "CPU_nCNTPSNIRQ[0]" },
241 { 33, 4, "CPU_nCNTHPIRQ[0]" },
242 { 33, 3, "CPU_nCTIIRQ[0]" },
243 { 33, 2, "CPU_nPMUIRQ[0]" },
244 { 33, 1, "CPU_PARITYFAILSCU[0]" },
245 { 33, 0, "CPU_PARITYFAIL0" },
246 { 32, 7, "TZASC_XR1BXW" },
247 { 32, 6, "TZASC_XR1BXR" },
248 { 32, 5, "TZASC_XLBXW" },
249 { 32, 4, "TZASC_XLBXR" },
250 { 32, 3, "TZASC_DRBXW" },
251 { 32, 2, "TZASC_DRBXR" },
252 { 32, 1, "TZASC_CBXW" },
253 { 32, 0, "TZASC_CBXR" },
254
255 { -1, -1, NULL },
256 };
257
258 struct combined_intr {
259 uint32_t enabled;
260 void (*ih) (void *);
261 void *ih_user;
262 };
263
264 static struct combined_intr intr_map[32][8];
265
266 static void
combiner_intr(void * arg)267 combiner_intr(void *arg)
268 {
269 struct combiner_softc *sc;
270 void (*ih) (void *);
271 void *ih_user;
272 int enabled;
273 int intrs;
274 int shift;
275 int cirq;
276 int grp;
277 int i,n;
278
279 sc = arg;
280
281 intrs = READ4(sc, CIPSR);
282 for (grp = 0; grp < 32; grp++) {
283 if (intrs & (1 << grp)) {
284 n = (grp / 4);
285 shift = (grp % 4) * 8;
286
287 cirq = READ4(sc, ISTR(n));
288 for (i = 0; i < 8; i++) {
289 if (cirq & (1 << (i + shift))) {
290 ih = intr_map[grp][i].ih;
291 ih_user = intr_map[grp][i].ih_user;
292 enabled = intr_map[grp][i].enabled;
293 if (enabled && (ih != NULL)) {
294 ih(ih_user);
295 }
296 }
297 }
298 }
299 }
300 }
301
302 void
combiner_setup_intr(char * source_name,void (* ih)(void *),void * ih_user)303 combiner_setup_intr(char *source_name, void (*ih)(void *), void *ih_user)
304 {
305 struct combiner_entry *entry;
306 struct combined_intr *cirq;
307 struct combiner_softc *sc;
308 int shift;
309 int reg;
310 int grp;
311 int n;
312 int i;
313
314 sc = combiner_sc;
315
316 if (sc == NULL) {
317 printf("%s: error: combiner is not attached\n", __func__);
318 return;
319 }
320
321 entry = NULL;
322
323 for (i = 0; i < NGRP && interrupt_table[i].bit != -1; i++) {
324 if (strcmp(interrupt_table[i].source_name, source_name) == 0) {
325 entry = &interrupt_table[i];
326 }
327 }
328
329 if (entry == NULL) {
330 device_printf(sc->dev, "Can't find interrupt name %s\n",
331 source_name);
332 return;
333 }
334
335 #if 0
336 device_printf(sc->dev, "Setting up interrupt %s\n", source_name);
337 #endif
338
339 grp = entry->combiner_id - 32;
340
341 cirq = &intr_map[grp][entry->bit];
342 cirq->enabled = 1;
343 cirq->ih = ih;
344 cirq->ih_user = ih_user;
345
346 n = grp / 4;
347 shift = (grp % 4) * 8 + entry->bit;
348
349 reg = (1 << shift);
350 WRITE4(sc, IESR(n), reg);
351 }
352
353 static int
combiner_probe(device_t dev)354 combiner_probe(device_t dev)
355 {
356
357 if (!ofw_bus_status_okay(dev))
358 return (ENXIO);
359
360 if (!ofw_bus_is_compatible(dev, "exynos,combiner"))
361 return (ENXIO);
362
363 device_set_desc(dev, "Samsung Exynos 5 Interrupt Combiner");
364 return (BUS_PROBE_DEFAULT);
365 }
366
367 static int
combiner_attach(device_t dev)368 combiner_attach(device_t dev)
369 {
370 struct combiner_softc *sc;
371 int err;
372 int i;
373
374 sc = device_get_softc(dev);
375 sc->dev = dev;
376
377 if (bus_alloc_resources(dev, combiner_spec, sc->res)) {
378 device_printf(dev, "could not allocate resources\n");
379 return (ENXIO);
380 }
381
382 /* Memory interface */
383 sc->bst = rman_get_bustag(sc->res[0]);
384 sc->bsh = rman_get_bushandle(sc->res[0]);
385
386 combiner_sc = sc;
387
388 /* Setup interrupt handler */
389 for (i = 0; i < NGRP; i++) {
390 err = bus_setup_intr(dev, sc->res[1+i], INTR_TYPE_BIO | \
391 INTR_MPSAFE, NULL, combiner_intr, sc, &sc->ih[i]);
392 if (err) {
393 device_printf(dev, "Unable to alloc int resource.\n");
394 return (ENXIO);
395 }
396 }
397
398 return (0);
399 }
400
401 static device_method_t combiner_methods[] = {
402 DEVMETHOD(device_probe, combiner_probe),
403 DEVMETHOD(device_attach, combiner_attach),
404 { 0, 0 }
405 };
406
407 static driver_t combiner_driver = {
408 "combiner",
409 combiner_methods,
410 sizeof(struct combiner_softc),
411 };
412
413 static devclass_t combiner_devclass;
414
415 DRIVER_MODULE(combiner, simplebus, combiner_driver, combiner_devclass, 0, 0);
416