1;;- Machine description for the AT&T DSP1600 for GNU C compiler 2;; Copyright (C) 1994, 1995, 1997, 1998, 2001, 2002 3;; Free Software Foundation, Inc. 4;; Contributed by Michael Collison (collison@isisinc.net). 5 6;; This file is part of GNU CC. 7 8;; GNU CC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12 13;; GNU CC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GNU CC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 59 Temple Place - Suite 330, 21;; Boston, MA 02111-1307, USA. 22 23 24;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 25 26;; Attribute specifications 27 28; Type of each instruction. Default is arithmetic. 29; I'd like to write the list as this, but genattrtab won't accept it. 30; 31; "jump,cond_jump,call, ; flow-control instructions 32; load_i,load, store, move ; Y space address arithmetic instructions 33; malu,special,f3_alu,f3_alu_i ; data arithmetic unit instructions 34; shift_i,shift, bfield_i, bfield ; bit manipulation unit instructions 35; arith, ; integer unit instructions 36; nop 37 38; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. 39(define_attr "type" 40 "jump,cond_jump,call,load_i,load,move,store,malu,malu_mul,tstqi,special,special_2,f3_alu,f3_alu_i,f3_alu_i_mult,shift_i,shift,shift_multiple,shift_i_multiple,bfield_i,bfield,nop,ld_short_i,data_move,data_move_i,data_move_memory,data_move_memory_2,data_move_short_i,data_move_multiple,data_move_2,nothing" 41 (const_string "malu")) 42 43;; Data arithmetic unit 44(define_function_unit "dau" 1 1 (eq_attr "type" "data_move,data_move_i,f3_alu_i") 2 0) 45 46(define_function_unit "dau" 1 1 (eq_attr "type" "special_2") 3 0) 47 48(define_function_unit "dau" 1 1 (eq_attr "type" "data_move_2") 4 0) 49 50;; Bit manipulation 51(define_function_unit "bmu" 1 1 (eq_attr "type" "shift_i,shift_i_multiple") 2 0) 52 53(define_function_unit "bmu" 1 1 (eq_attr "type" "shift_multiple") 4 0) 54 55;; Y-memory addressing arithmetic unit 56(define_function_unit "yaau" 1 1 (eq_attr "type" "data_move_memory") 2 0) 57 58(define_function_unit "yaau" 1 1 (eq_attr "type" "data_move_memory_2") 4 0) 59 60 61;; .................... 62;; 63;; Test against 0 instructions 64;; 65;; .................... 66 67(define_expand "tsthi" 68 [(set (cc0) 69 (match_operand:HI 0 "register_operand" ""))] 70 "" 71 " 72{ 73 dsp16xx_compare_gen = gen_tst_reg; 74 dsp16xx_compare_op0 = operands[0]; 75 dsp16xx_compare_op1 = const0_rtx; 76 DONE; 77}") 78 79(define_insn "tsthi_1" 80 [(set (cc0) 81 (match_operand:HI 0 "register_operand" "A"))] 82 "" 83 "%0=%0" 84 [(set_attr "type" "malu")]) 85 86(define_expand "tstqi" 87 [(set (cc0) 88 (match_operand:QI 0 "register_operand" ""))] 89 "" 90 " 91{ 92 dsp16xx_compare_gen = gen_tst_reg; 93 dsp16xx_compare_op0 = operands[0]; 94 dsp16xx_compare_op1 = const0_rtx; 95 DONE; 96}") 97 98(define_split 99 [(set (cc0) 100 (match_operand:QI 0 "register_operand" "j,q")) 101 (clobber (match_scratch:QI 1 "=k,u"))] 102 "reload_completed" 103 [(set (match_dup 1) 104 (const_int 0)) 105 (parallel [(set (cc0) 106 (match_dup 0)) 107 (use (match_dup 1))])] 108 "") 109 110(define_insn "tstqi_split" 111 [(set (cc0) 112 (match_operand:QI 0 "register_operand" "j,q")) 113 (use (match_scratch:QI 1 "=k,u"))] 114 "" 115 "@ 116 %b0-0 117 %b0-0" 118 [(set_attr "type" "f3_alu_i,f3_alu_i")]) 119 120(define_insn "tstqi_1" 121 [(set (cc0) 122 (match_operand:QI 0 "register_operand" "j,q")) 123 (clobber (match_scratch:QI 1 "=k,u"))] 124 "" 125 "@ 126 %1=0\;%b0-0 127 %1=0\;%b0-0" 128 [(set_attr "type" "tstqi,tstqi")]) 129 130 131;; 132;; .................... 133;; 134;; Bit test instructions 135;; 136;; .................... 137 138(define_insn "" 139 [(set (cc0) 140 (and:HI (match_operand:HI 0 "register_operand" "A,!A") 141 (match_operand:HI 1 "register_operand" "Z,A")))] 142 "" 143 "* 144{ 145 switch (which_alternative) 146 { 147 case 0: 148 case 1: 149 return \"%0&%1\"; 150 default: 151 abort(); 152 } 153}" 154 [(set_attr "type" "f3_alu,f3_alu")]) 155 156 157;;(define_insn "" 158;; [(set (cc0) 159;; (and:QI (match_operand:QI 0 "register_operand" "h") 160;; (match_operand:QI 1 "const_int_operand" "I")))] 161;; "" 162;; "%b0&%H1" 163;; [(set_attr "type" "f3_alu_i")]) 164 165;; 166;; 167;; Compare Instructions 168;; 169 170(define_expand "cmphi" 171 [(parallel [(set (cc0) 172 (compare (match_operand:HI 0 "general_operand" "") 173 (match_operand:HI 1 "general_operand" ""))) 174 (clobber (match_scratch:QI 2 "")) 175 (clobber (match_scratch:QI 3 "")) 176 (clobber (match_scratch:QI 4 "")) 177 (clobber (match_scratch:QI 5 ""))])] 178 "" 179 " 180{ 181 if (GET_CODE (operands[1]) == CONST_INT) 182 operands[1] = force_reg (HImode, operands[1]); 183 184 dsp16xx_compare_gen = gen_compare_reg; 185 dsp16xx_compare_op0 = operands[0]; 186 dsp16xx_compare_op1 = operands[1]; 187 DONE; 188}") 189 190(define_insn "" 191 [(set (cc0) 192 (compare (match_operand:HI 0 "general_operand" "Z*r*m*i") 193 (match_operand:HI 1 "general_operand" "Z*r*m*i"))) 194 (clobber (match_scratch:QI 2 "=&A")) 195 (clobber (match_scratch:QI 3 "=&A")) 196 (clobber (match_scratch:QI 4 "=&A")) 197 (clobber (match_scratch:QI 5 "=&A"))] 198 "next_cc_user_unsigned (insn)" 199 "* 200{ 201 if (GET_CODE(operands[0]) == REG) 202 { 203 if (REGNO (operands[0]) == REG_Y || 204 REGNO (operands[0]) == REG_PROD) 205 { 206 output_asm_insn (\"a0=%0\", operands); 207 } 208 else if (IS_YBASE_REGISTER_WINDOW (REGNO (operands[0]))) 209 output_asm_insn (\"a0=%u0\;a0l=%w0\", operands); 210 else 211 fatal_error (\"Invalid register for compare\"); 212 } 213 else if (GET_CODE(operands[0]) == CONST_INT) 214 output_asm_insn (\"a0=%U0\;a0l=%H0\", operands); 215 else if (GET_CODE (operands[0]) == MEM) 216 { 217 rtx xoperands[2]; 218 219 xoperands[0] = gen_rtx_REG (HImode, REG_A0); 220 xoperands[1] = operands[0]; 221 double_reg_from_memory (xoperands); 222 } 223 224 if (GET_CODE(operands[1]) == REG) 225 { 226 if (REGNO (operands[1]) == REG_Y || REGNO (operands[1]) == REG_PROD) 227 output_asm_insn (\"a1=%1\", operands); 228 else if (IS_YBASE_REGISTER_WINDOW (REGNO (operands[1]))) 229 output_asm_insn (\"a1=%u1\;a1l=%w1\", operands); 230 else 231 fatal_error (\"Invalid register for compare\"); 232 } 233 else if (GET_CODE (operands[1]) == MEM) 234 { 235 rtx xoperands[2]; 236 237 xoperands[0] = gen_rtx_REG (HImode, REG_A1); 238 xoperands[1] = operands[1]; 239 double_reg_from_memory (xoperands); 240 } 241 else if (GET_CODE(operands[1]) == CONST_INT) 242 { 243 output_asm_insn (\"a1=%U1\;a1l=%H1\", operands); 244 } 245 246 return \"psw = 0\;a0 - a1\"; 247}") 248 249(define_insn "" 250 [(set (cc0) (compare (match_operand:HI 0 "register_operand" "A,!A") 251 (match_operand:HI 1 "register_operand" "Z,*A")))] 252 "" 253 "@ 254 %0-%1 255 %0-%1" 256 [(set_attr "type" "malu,f3_alu")]) 257 258(define_expand "cmpqi" 259 [(parallel [(set (cc0) 260 (compare (match_operand:QI 0 "register_operand" "") 261 (match_operand:QI 1 "nonmemory_operand" ""))) 262 (clobber (match_operand:QI 2 "register_operand" "")) 263 (clobber (match_operand:QI 3 "register_operand" ""))])] 264 "" 265 " 266 { 267 if (operands[0]) /* Avoid unused code warning */ 268 { 269 dsp16xx_compare_gen = gen_compare_reg; 270 dsp16xx_compare_op0 = operands[0]; 271 dsp16xx_compare_op1 = operands[1]; 272 DONE; 273 } 274 }") 275 276(define_split 277 [(set (cc0) 278 (compare (match_operand:QI 0 "register_operand" "") 279 (match_operand:QI 1 "register_operand" ""))) 280 (clobber (match_scratch:QI 2 "")) 281 (clobber (match_scratch:QI 3 ""))] 282 "reload_completed && next_cc_user_unsigned (insn)" 283 [(set (match_dup 2) 284 (const_int 0)) 285 (set (match_dup 3) 286 (const_int 0)) 287 (parallel [(set (cc0) 288 (compare (match_dup 0) 289 (match_dup 1))) 290 (use (match_dup 2)) 291 (use (match_dup 3))])] 292 "") 293 294(define_split 295 [(set (cc0) 296 (compare (match_operand:QI 0 "register_operand" "") 297 (match_operand:QI 1 "const_int_operand" ""))) 298 (clobber (match_scratch:QI 2 "")) 299 (clobber (match_scratch:QI 3 ""))] 300 "reload_completed && next_cc_user_unsigned (insn)" 301 [(set (match_dup 2) 302 (const_int 0)) 303 (parallel [(set (cc0) 304 (compare (match_dup 0) 305 (match_dup 1))) 306 (use (match_dup 2))])] 307 "") 308 309(define_insn "cmpqi_split_unsigned_reg" 310 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "k,k,!k,u,u,!u") 311 (match_operand:QI 1 "register_operand" "w,z,u,w,z,k"))) 312 (use (match_scratch:QI 2 "=j,j,j,q,q,q")) 313 (use (match_scratch:QI 3 "=v,y,q,v,y,j"))] 314 "next_cc_user_unsigned (insn)" 315 "@ 316 %2-%3 317 %2-%3 318 %2-%3 319 %2-%3 320 %2-%3 321 %2-%3" 322 [(set_attr "type" "malu,malu,malu,malu,malu,malu")]) 323 324(define_insn "cmpqi_split_unsigned_int" 325 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "k,u") 326 (match_operand:QI 1 "const_int_operand" "i,i"))) 327 (use (match_scratch:QI 2 "=j,q"))] 328 "next_cc_user_unsigned (insn)" 329 "@ 330 %0-%H1 331 %0-%H1" 332 [(set_attr "type" "f3_alu_i,f3_alu_i")]) 333 334(define_insn "" 335 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "k,k,!k,k,u,u,!u,u") 336 (match_operand:QI 1 "nonmemory_operand" "w,z,u,i,w,z,k,i"))) 337 (clobber (match_scratch:QI 2 "=j,j,j,j,q,q,q,q")) 338 (clobber (match_scratch:QI 3 "=v,y,q,X,v,y,j,X"))] 339 "next_cc_user_unsigned (insn)" 340 "@ 341 %2=0\;%3=0\;%2-%3 342 %2=0\;%3=0\;%2-%3 343 %2=0\;%3=0\;%2-%3 344 %2=0\;%0-%H1 345 %2=0\;%3=0\;%2-%3 346 %2=0\;%3=0\;%2-%3 347 %2=0\;%3=0\;%2-%3 348 %2=0\;%0-%H1") 349 350(define_split 351 [(set (cc0) 352 (compare (match_operand:QI 0 "register_operand" "") 353 (match_operand:QI 1 "register_operand" ""))) 354 (clobber (match_scratch:QI 2 "")) 355 (clobber (match_scratch:QI 3 ""))] 356 "reload_completed" 357 [(set (match_dup 2) 358 (const_int 0)) 359 (set (match_dup 3) 360 (const_int 0)) 361 (parallel [(set (cc0) 362 (compare (match_dup 0) 363 (match_dup 1))) 364 (use (match_dup 2)) 365 (use (match_dup 3))])] 366 "") 367 368(define_split 369 [(set (cc0) 370 (compare (match_operand:QI 0 "register_operand" "") 371 (match_operand:QI 1 "const_int_operand" ""))) 372 (clobber (match_scratch:QI 2 "")) 373 (clobber (match_scratch:QI 3 ""))] 374 "reload_completed" 375 [(set (match_dup 2) 376 (const_int 0)) 377 (parallel [(set (cc0) 378 (compare (match_dup 0) 379 (match_dup 1))) 380 (use (match_dup 2))])] 381 "") 382 383(define_insn "cmpqi_split_reg" 384 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "j,j,!j,q,q,!q") 385 (match_operand:QI 1 "register_operand" "v,y,q,v,y,j"))) 386 (use (match_scratch:QI 2 "=k,k,k,u,u,u")) 387 (use (match_scratch:QI 3 "=w,z,u,w,z,k"))] 388 "" 389 "@ 390 %0-%1 391 %0-%1 392 %0-%1 393 %0-%1 394 %0-%1 395 %0-%1" 396 [(set_attr "type" "malu,malu,malu,malu,malu,malu")]) 397 398 399(define_insn "cmpqi_split_int" 400 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "j,q") 401 (match_operand:QI 1 "const_int_operand" "i,i"))) 402 (use (match_scratch:QI 2 "=k,u"))] 403 "" 404 "@ 405 %b0-%H1 406 %b0-%H1" 407 [(set_attr "type" "f3_alu_i,f3_alu_i")]) 408 409(define_insn "" 410 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "j,j,!j,j,q,q,!q,q") 411 (match_operand:QI 1 "nonmemory_operand" "v,y,q,i,v,y,j,i"))) 412 (clobber (match_scratch:QI 2 "=k,k,k,k,u,u,u,u")) 413 (clobber (match_scratch:QI 3 "=w,z,u,X,w,z,k,X"))] 414 "" 415 "@ 416 %2=0\;%3=0\;%0-%1 417 %2=0\;%3=0\;%0-%1 418 %2=0\;%3=0\;%0-%1 419 %2=0\;%b0-%H1 420 %2=0\;%3=0\;%0-%1 421 %2=0\;%3=0\;%0-%1 422 %2=0\;%3=0\;%0-%1 423 %2=0\;%b0-%H1") 424 425 426(define_expand "cmphf" 427 [(set (cc0) 428 (compare (match_operand:HF 0 "register_operand" "") 429 (match_operand:HF 1 "nonmemory_operand" "")))] 430 "" 431 " 432{ 433 if (!dsp16xx_cmphf3_libcall) 434 dsp16xx_cmphf3_libcall = gen_rtx_SYMBOL_REF (Pmode, CMPHF3_LIBCALL); 435 436 dsp16xx_compare_gen = gen_compare_reg; 437 dsp16xx_compare_op0 = operands[0]; 438 dsp16xx_compare_op1 = operands[1]; 439 emit_library_call (dsp16xx_cmphf3_libcall, 1, HImode, 2, 440 operands[0], HFmode, 441 operands[1], HFmode); 442 emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode)))); 443 DONE; 444}") 445 446 447;; .................... 448;; 449;; Add instructions 450;; 451;; .................... 452 453(define_split 454 [(set (match_operand:HI 0 "register_operand" "") 455 (plus:HI (match_operand:HI 1 "register_operand" "") 456 (match_operand:HI 2 "const_int_operand" "")))] 457 "reload_completed && !ADD_LOW_16(INTVAL(operands[2])) && 458 !ADD_HIGH_16(INTVAL(operands[2]))" 459 [(parallel [(set (match_dup 3) 460 (plus:QI (match_dup 4) 461 (match_dup 5))) 462 (clobber (match_dup 6))]) 463 464 (parallel [(set (match_dup 6) 465 (plus:QI (match_dup 7) 466 (match_dup 8))) 467 (clobber (match_scratch:QI 9 ""))])] 468 " 469{ 470 operands[3] = gen_lowpart(QImode, operands[0]); 471 operands[4] = gen_lowpart(QImode, operands[1]); 472 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 473 474 operands[6] = gen_highpart(QImode, operands[0]); 475 operands[7] = gen_highpart(QImode, operands[0]); 476 operands[8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 477}") 478 479 480(define_insn "addhi3" 481 [(set (match_operand:HI 0 "register_operand" "=A,A,A,A,A") 482 (plus:HI (match_operand:HI 1 "register_operand" "%A,A,A,A,A") 483 (match_operand:HI 2 "nonmemory_operand" "Z,d,L,M,?i")))] 484 "" 485 "@ 486 %0=%1+%2 487 %0=%1+%2 488 %0=%w1+%H2 489 %0=%b1+%U2 490 %0=%w1+%H2\;%0=%b0+%U2" 491 [(set_attr "type" "malu,malu,f3_alu_i,f3_alu_i,f3_alu_i")]) 492 493(define_insn "" 494 [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u") 495 (plus:QI (plus:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk") 496 (match_operand:QI 2 "register_operand" "wz,wz,uk,uk")) 497 (match_operand:QI 3 "immediate_operand" "i,i,i,i"))) 498 (clobber (match_scratch:QI 4 "=j,q,j,q"))] 499 "" 500 "@ 501 %m0=%m1+%m2\;%m0=%0+%H3 502 %m0=%m1+%m2\;%m0=%0+%H3 503 %m0=%m1+%m2\;%m0=%0+%H3 504 %m0=%m1+%m2\;%m0=%0+%H3") 505 506(define_expand "addqi3" 507 [(parallel [(set (match_operand:QI 0 "register_operand" "") 508 (plus:QI (match_operand:QI 1 "register_operand" "") 509 (match_operand:QI 2 "nonmemory_operand" ""))) 510 (clobber (match_scratch:QI 3 ""))])] 511 "" 512 " 513{ 514 if (reload_in_progress) 515 { 516 if (REG_P (operands[1]) && 517 (REGNO(operands[1]) == STACK_POINTER_REGNUM || 518 REGNO(operands[1]) == FRAME_POINTER_REGNUM) && 519 GET_CODE (operands[2]) == CONST_INT) 520 { 521 if (REG_P (operands[0]) && IS_ACCUM_REG(REGNO(operands[0]))) 522 emit_move_insn (operands[0], operands[1]); 523 524 operands[1] = operands[0]; 525 } 526 } 527}") 528 529 530(define_insn "match_addqi3" 531 [(set (match_operand:QI 0 "register_operand" "=a,a,k,u,k,u,!k,!u,j,j,q,q") 532 (plus:QI (match_operand:QI 1 "register_operand" "0,0,uk,uk,uk,uk,uk,uk,0,q,0,j") 533 (match_operand:QI 2 "nonmemory_operand" "W,N,i,i,wz,wz,uk,uk,i,i,i,i"))) 534 (clobber (match_scratch:QI 3 "=X,X,j,q,j,q,j,q,X,k,X,u"))] 535 "" 536 "* 537{ 538 switch (which_alternative) 539 { 540 case 0: 541 return \"*%0++%2\"; 542 543 case 1: 544 switch (INTVAL (operands[2])) 545 { 546 case -1: 547 return \"*%0--\"; 548 549 case 1: 550 return \"*%0++\"; 551 552 case -2: 553 return \"*%0--\;*%0--\"; 554 555 case 2: 556 return \"*%0++\;*%0++\"; 557 default: 558 abort(); 559 } 560 561 case 2: 562 case 3: 563 return \"%m0=%1+%H2\"; 564 565 case 4: 566 case 5: 567 return \"%m0=%m1+%m2\"; 568 569 570 case 6: 571 case 7: 572 return \"%m0=%m1+%m2\"; 573 574 case 8: 575 case 9: 576 case 10: 577 case 11: 578 return \"%0=%b1+%H2\"; 579 default: 580 abort(); 581 } 582}" 583[(set_attr "type" "data_move_memory,data_move_multiple,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")]) 584 585 586(define_expand "addhf3" 587 [(set (match_operand:HF 0 "register_operand" "") 588 (plus:HF (match_operand:HF 1 "register_operand" "") 589 (match_operand:HF 2 "nonmemory_operand" "")))] 590 "" 591 " 592{ 593 if (!dsp16xx_addhf3_libcall) 594 dsp16xx_addhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, ADDHF3_LIBCALL); 595 596 emit_library_call (dsp16xx_addhf3_libcall, 1, HFmode, 2, 597 operands[1], HFmode, 598 operands[2], HFmode); 599 emit_move_insn (operands[0], hard_libcall_value(HFmode)); 600 DONE; 601}") 602 603 604;; 605;; .................... 606;; 607;; Subtract instructions 608;; 609;; .................... 610 611(define_split 612 [(set (match_operand:HI 0 "register_operand" "") 613 (minus:HI (match_operand:HI 1 "register_operand" "") 614 (match_operand:HI 2 "const_int_operand" "")))] 615 "reload_completed && !ADD_LOW_16(INTVAL(operands[2])) && 616 !ADD_HIGH_16(INTVAL(operands[2]))" 617 [(parallel [(set (match_dup 3) 618 (minus:QI (match_dup 4) 619 (match_dup 5))) 620 (clobber (match_dup 6))]) 621 622 (parallel [(set (match_dup 6) 623 (minus:QI (match_dup 7) 624 (match_dup 8))) 625 (clobber (match_scratch:QI 9 ""))])] 626 " 627{ 628 operands[3] = gen_lowpart(QImode, operands[0]); 629 operands[4] = gen_lowpart(QImode, operands[1]); 630 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 631 632 operands[6] = gen_highpart(QImode, operands[0]); 633 operands[7] = gen_highpart(QImode, operands[0]); 634 operands[8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 635}") 636 637 638(define_insn "subhi3" 639 [(set (match_operand:HI 0 "register_operand" "=A,A,A,A,A") 640 (minus:HI (match_operand:HI 1 "register_operand" "A,A,A,A,A") 641 (match_operand:HI 2 "nonmemory_operand" "Z,d,L,M,?i")))] 642 "" 643 "@ 644 %0=%1-%2 645 %0=%1-%2 646 %0=%w1-%H2 647 %0=%b1-%U2 648 %0=%w1-%H2\;%0=%b0-%U2" 649 [(set_attr "type" "malu,malu,f3_alu_i,f3_alu_i,f3_alu_i")]) 650 651(define_insn "subqi3" 652 [(set (match_operand:QI 0 "register_operand" "=a,k,u,k,u,!k,!u,j,j,q,q") 653 (minus:QI (match_operand:QI 1 "register_operand" "0,uk,uk,uk,uk,uk,uk,0,q,0,j") 654 (match_operand:QI 2 "nonmemory_operand" "N,i,i,wz,wz,uk,uk,i,i,i,i"))) 655 (clobber (match_scratch:QI 3 "=X,j,q,j,q,j,q,X,k,X,u"))] 656 "" 657 "* 658{ 659 switch (which_alternative) 660 { 661 case 0: 662 switch (INTVAL (operands[2])) 663 { 664 case 1: 665 return \"*%0--\"; 666 667 case -1: 668 return \"*%0++\"; 669 670 default: 671 operands[2] = GEN_INT (-INTVAL (operands[2])); 672 673 if (SHORT_IMMEDIATE(operands[2])) 674 return \"set %3=%H2\;*%0++%3\"; 675 else 676 return \"%3=%H2\;*%0++%3\"; 677 } 678 679 case 1: 680 case 2: 681 return \"%m0=%1-%H2\"; 682 683 case 3: 684 case 4: 685 return \"%m0=%m1-%m2\"; 686 687 case 5: 688 case 6: 689 return \"%m0=%m1-%m2\"; 690 691 case 7: case 8: 692 case 9: case 10: 693 return \"%0=%b1-%H2\"; 694 default: 695 abort(); 696 } 697}" 698[(set_attr "type" "data_move_multiple,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")]) 699 700(define_expand "subhf3" 701 [(set (match_operand:HF 0 "register_operand" "") 702 (minus:HF (match_operand:HF 1 "register_operand" "") 703 (match_operand:HF 2 "nonmemory_operand" "")))] 704 "" 705 " 706{ 707 if (!dsp16xx_subhf3_libcall) 708 dsp16xx_subhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, SUBHF3_LIBCALL); 709 710 emit_library_call (dsp16xx_subhf3_libcall, 1, HFmode, 2, 711 operands[1], HFmode, 712 operands[2], HFmode); 713 emit_move_insn (operands[0], hard_libcall_value(HFmode)); 714 DONE; 715}") 716 717(define_insn "neghi2" 718 [(set (match_operand:HI 0 "register_operand" "=A") 719 (neg:HI (match_operand:HI 1 "register_operand" "A")))] 720 "" 721 "%0=-%1" 722 [(set_attr "type" "special")]) 723 724(define_expand "neghf2" 725 [(set (match_operand:HF 0 "register_operand" "") 726 (neg:HF (match_operand:HF 1 "register_operand" "")))] 727 "" 728 " 729{ 730 rtx result; 731 rtx target; 732 733 { 734 target = gen_lowpart(HImode, operands[0]); 735 result = expand_binop (HImode, xor_optab, 736 gen_lowpart(HImode, operands[1]), 737 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); 738 if (result == 0) 739 abort (); 740 741 if (result != target) 742 emit_move_insn (result, target); 743 744 /* Make a place for REG_EQUAL. */ 745 emit_move_insn (operands[0], operands[0]); 746 DONE; 747 } 748}") 749 750;; 751;; .................... 752;; 753;; Multiply instructions 754;; 755 756(define_expand "mulhi3" 757 [(set (match_operand:HI 0 "register_operand" "") 758 (mult:HI (match_operand:HI 1 "register_operand" "") 759 (match_operand:HI 2 "nonmemory_operand" "")))] 760 "" 761 " 762{ 763 if (!dsp16xx_mulhi3_libcall) 764 dsp16xx_mulhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHI3_LIBCALL); 765 766 emit_library_call (dsp16xx_mulhi3_libcall, 1, HImode, 2, 767 operands[1], HImode, 768 operands[2], HImode); 769 emit_move_insn (operands[0], hard_libcall_value(HImode)); 770 DONE; 771}") 772 773(define_insn "mulqi3" 774 [(set (match_operand:QI 0 "register_operand" "=w") 775 (mult:QI (match_operand:QI 1 "register_operand" "%x") 776 (match_operand:QI 2 "register_operand" "y"))) 777 (clobber (match_scratch:QI 3 "=v"))] 778 "" 779 "%m0=%1*%2" 780 [(set_attr "type" "malu_mul")]) 781 782(define_insn "mulqihi3" 783 [(set (match_operand:HI 0 "register_operand" "=t") 784 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%x")) 785 (sign_extend:HI (match_operand:QI 2 "register_operand" "y"))))] 786 "" 787 "%0=%1*%2" 788 [(set_attr "type" "malu_mul")]) 789 790(define_expand "mulhf3" 791 [(set (match_operand:HF 0 "register_operand" "") 792 (mult:HF (match_operand:HF 1 "register_operand" "") 793 (match_operand:HF 2 "nonmemory_operand" "")))] 794 "" 795 " 796{ 797 if (!dsp16xx_mulhf3_libcall) 798 dsp16xx_mulhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHF3_LIBCALL); 799 800 emit_library_call (dsp16xx_mulhf3_libcall, 1, HFmode, 2, 801 operands[1], HFmode, 802 operands[2], HFmode); 803 emit_move_insn (operands[0], hard_libcall_value(HFmode)); 804 DONE; 805}") 806 807 808 809;; 810;; ******************* 811;; 812;; Divide Instructions 813;; 814 815(define_expand "divhi3" 816 [(set (match_operand:HI 0 "register_operand" "") 817 (div:HI (match_operand:HI 1 "register_operand" "") 818 (match_operand:HI 2 "nonmemory_operand" "")))] 819 "" 820 " 821{ 822 if (!dsp16xx_divhi3_libcall) 823 dsp16xx_divhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHI3_LIBCALL); 824 825 emit_library_call (dsp16xx_divhi3_libcall, 1, HImode, 2, 826 operands[1], HImode, 827 operands[2], HImode); 828 emit_move_insn (operands[0], hard_libcall_value(HImode)); 829 DONE; 830}") 831 832(define_expand "udivhi3" 833 [(set (match_operand:HI 0 "register_operand" "") 834 (udiv:HI (match_operand:HI 1 "register_operand" "") 835 (match_operand:HI 2 "nonmemory_operand" "")))] 836 "" 837 " 838{ 839 if (!dsp16xx_udivhi3_libcall) 840 dsp16xx_udivhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVHI3_LIBCALL); 841 842 emit_library_call (dsp16xx_udivhi3_libcall, 1, HImode, 2, 843 operands[1], HImode, 844 operands[2], HImode); 845 emit_move_insn (operands[0], hard_libcall_value(HImode)); 846 DONE; 847}") 848 849(define_expand "divqi3" 850 [(set (match_operand:QI 0 "register_operand" "") 851 (div:QI (match_operand:QI 1 "register_operand" "") 852 (match_operand:QI 2 "nonmemory_operand" "")))] 853 "" 854 " 855{ 856 if (!dsp16xx_divqi3_libcall) 857 dsp16xx_divqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVQI3_LIBCALL); 858 859 emit_library_call (dsp16xx_divqi3_libcall, 1, QImode, 2, 860 operands[1], QImode, 861 operands[2], QImode); 862 emit_move_insn (operands[0], hard_libcall_value(QImode)); 863 DONE; 864}") 865 866(define_expand "udivqi3" 867 [(set (match_operand:QI 0 "register_operand" "") 868 (udiv:QI (match_operand:QI 1 "register_operand" "") 869 (match_operand:QI 2 "nonmemory_operand" "")))] 870 "" 871 " 872{ 873 if (!dsp16xx_udivqi3_libcall) 874 dsp16xx_udivqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVQI3_LIBCALL); 875 876 emit_library_call (dsp16xx_udivqi3_libcall, 1, QImode, 2, 877 operands[1], QImode, 878 operands[2], QImode); 879 emit_move_insn (operands[0], hard_libcall_value(QImode)); 880 DONE; 881}") 882 883;; 884;; .................... 885;; 886;; Modulo instructions 887;; 888;; .................... 889 890(define_expand "modhi3" 891 [(set (match_operand:HI 0 "register_operand" "") 892 (mod:HI (match_operand:HI 1 "register_operand" "") 893 (match_operand:HI 2 "nonmemory_operand" "")))] 894 "" 895 " 896{ 897 if (!dsp16xx_modhi3_libcall) 898 dsp16xx_modhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODHI3_LIBCALL); 899 900 emit_library_call (dsp16xx_modhi3_libcall, 1, HImode, 2, 901 operands[1], HImode, 902 operands[2], HImode); 903 emit_move_insn (operands[0], hard_libcall_value(HImode)); 904 DONE; 905}") 906 907(define_expand "umodhi3" 908 [(set (match_operand:HI 0 "register_operand" "") 909 (umod:HI (match_operand:HI 1 "register_operand" "") 910 (match_operand:HI 2 "nonmemory_operand" "")))] 911 "" 912 " 913{ 914 if (!dsp16xx_umodhi3_libcall) 915 dsp16xx_umodhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODHI3_LIBCALL); 916 917 emit_library_call (dsp16xx_umodhi3_libcall, 1, HImode, 2, 918 operands[1], HImode, 919 operands[2], HImode); 920 emit_move_insn (operands[0], hard_libcall_value(HImode)); 921 DONE; 922}") 923 924(define_expand "modqi3" 925 [(set (match_operand:QI 0 "register_operand" "") 926 (mod:QI (match_operand:QI 1 "register_operand" "") 927 (match_operand:QI 2 "nonmemory_operand" "")))] 928 "" 929 " 930{ 931 if (!dsp16xx_modqi3_libcall) 932 dsp16xx_modqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODQI3_LIBCALL); 933 934 emit_library_call (dsp16xx_modqi3_libcall, 1, QImode, 2, 935 operands[1], QImode, 936 operands[2], QImode); 937 emit_move_insn (operands[0], hard_libcall_value(QImode)); 938 DONE; 939}") 940 941(define_expand "umodqi3" 942 [(set (match_operand:QI 0 "register_operand" "") 943 (umod:QI (match_operand:QI 1 "register_operand" "") 944 (match_operand:QI 2 "nonmemory_operand" "")))] 945 "" 946 " 947{ 948 if (!dsp16xx_umodqi3_libcall) 949 dsp16xx_umodqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODQI3_LIBCALL); 950 951 emit_library_call (dsp16xx_umodqi3_libcall, 1, QImode, 2, 952 operands[1], QImode, 953 operands[2], QImode); 954 emit_move_insn (operands[0], hard_libcall_value(QImode)); 955 DONE; 956}") 957 958(define_expand "divhf3" 959 [(set (match_operand:HF 0 "register_operand" "") 960 (div:HF (match_operand:HF 1 "register_operand" "") 961 (match_operand:HF 2 "nonmemory_operand" "")))] 962 "" 963 " 964{ 965 if (!dsp16xx_divhf3_libcall) 966 dsp16xx_divhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHF3_LIBCALL); 967 968 emit_library_call (dsp16xx_divhf3_libcall, 1, HFmode, 2, 969 operands[1], HFmode, 970 operands[2], HFmode); 971 emit_move_insn (operands[0], hard_libcall_value(HFmode)); 972 DONE; 973}") 974 975 976 977;; 978;; ******************** 979;; 980;; Logical Instructions 981;; 982 983(define_split 984 [(set (match_operand:HI 0 "register_operand" "") 985 (and:HI (match_operand:HI 1 "register_operand" "") 986 (match_operand:HI 2 "const_int_operand" "")))] 987 "reload_completed && !AND_LOW_16(INTVAL(operands[2])) && 988 !AND_HIGH_16(INTVAL(operands[2])) 989 && (REGNO (operands[0]) == REGNO (operands[1]))" 990 [(parallel [(set (match_dup 3) 991 (and:QI (match_dup 4) 992 (match_dup 5))) 993 (clobber (match_scratch:QI 6 ""))]) 994 (parallel [(set (match_dup 7) 995 (and:QI (match_dup 8) 996 (match_dup 9))) 997 (clobber (match_scratch:QI 10 ""))])] 998 " 999{ 1000 operands[3] = gen_lowpart(QImode, operands[0]); 1001 operands[4] = gen_lowpart(QImode, operands[1]); 1002 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1003 1004 operands[7] = gen_highpart(QImode, operands[0]); 1005 operands[8] = gen_highpart(QImode, operands[0]); 1006 operands[9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1007}") 1008 1009(define_split 1010 [(set (match_operand:HI 0 "register_operand" "") 1011 (and:HI (match_operand:HI 1 "register_operand" "") 1012 (match_operand:HI 2 "const_int_operand" "")))] 1013 "reload_completed && !AND_LOW_16(INTVAL(operands[2])) && 1014 !AND_HIGH_16(INTVAL(operands[2])) 1015 && (REGNO (operands[0]) != REGNO (operands[1]))" 1016 [(parallel [(set (match_dup 3) 1017 (and:QI (match_dup 4) 1018 (match_dup 5))) 1019 (clobber (match_dup 6))]) 1020 (parallel [(set (match_dup 6) 1021 (and:QI (match_dup 7) 1022 (match_dup 8))) 1023 (clobber (match_scratch:QI 9 ""))])] 1024 " 1025{ 1026 operands[3] = gen_lowpart(QImode, operands[0]); 1027 operands[4] = gen_lowpart(QImode, operands[1]); 1028 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1029 1030 operands[6] = gen_highpart(QImode, operands[0]); 1031 operands[7] = gen_highpart(QImode, operands[0]); 1032 operands[8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1033}") 1034 1035(define_insn "andhi3" 1036 [(set (match_operand:HI 0 "register_operand" "=A,A,A,A,?A") 1037 (and:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A,A") 1038 (match_operand:HI 2 "nonmemory_operand" "Z,A,O,P,i")))] 1039 "" 1040 "@ 1041 %0=%1&%2 1042 %0=%1&%2 1043 %0=%w1&%H2 1044 %0=%b1&%U2 1045 %0=%w1&%H2\;%0=%b0&%U2" 1046 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")]) 1047 1048(define_insn "andqi3" 1049 [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q") 1050 (and:QI (match_operand:QI 1 "register_operand" "%uk,uk,uk,uk,0,0,u,k,jq,jq,0,0,q,j,jq,jq") 1051 (match_operand:QI 2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq"))) 1052 (clobber (match_scratch:QI 3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))] 1053 "" 1054 "@ 1055 %m0=%m1&%m2 1056 %m0=%m1&%m2 1057 %m0=%m1&%m2 1058 %m0=%m1&%m2 1059 %m0=%1&%H2 1060 %m0=%1&%H2 1061 %m0=%1&%H2 1062 %m0=%1&%H2 1063 %m0=%m1&%m2 1064 %m0=%m1&%m2 1065 %m0=%b1&%H2 1066 %m0=%b1&%H2 1067 %m0=%b1&%H2 1068 %m0=%b1&%H2 1069 %m0=%m1&%m2 1070 %m0=%m1&%m2" 1071 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")]) 1072 1073 1074(define_split 1075 [(set (match_operand:HI 0 "register_operand" "") 1076 (ior:HI (match_operand:HI 1 "register_operand" "") 1077 (match_operand:HI 2 "const_int_operand" "")))] 1078 "reload_completed && !SMALL_INTVAL(INTVAL(operands[2])) && 1079 !ADD_HIGH_16(INTVAL(operands[2])) 1080 && (REGNO (operands[0]) == REGNO (operands[1]))" 1081 [(parallel [(set (match_dup 3) 1082 (ior:QI (match_dup 4) 1083 (match_dup 5))) 1084 (clobber (match_scratch:QI 6 ""))]) 1085 (parallel [(set (match_dup 7) 1086 (ior:QI (match_dup 8) 1087 (match_dup 9))) 1088 (clobber (match_scratch:QI 10 ""))])] 1089 " 1090{ 1091 operands[3] = gen_lowpart(QImode, operands[0]); 1092 operands[4] = gen_lowpart(QImode, operands[1]); 1093 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1094 1095 operands[7] = gen_highpart(QImode, operands[0]); 1096 operands[8] = gen_highpart(QImode, operands[0]); 1097 operands[9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1098}") 1099 1100(define_split 1101 [(set (match_operand:HI 0 "register_operand" "") 1102 (ior:HI (match_operand:HI 1 "register_operand" "") 1103 (match_operand:HI 2 "const_int_operand" "")))] 1104 "reload_completed && !SMALL_INTVAL(INTVAL(operands[2])) && 1105 !ADD_HIGH_16(INTVAL(operands[2])) 1106 && (REGNO (operands[0]) != REGNO (operands[1]))" 1107 [(parallel [(set (match_dup 3) 1108 (ior:QI (match_dup 4) 1109 (match_dup 5))) 1110 (clobber (match_dup 6))]) 1111 (parallel [(set (match_dup 6) 1112 (ior:QI (match_dup 7) 1113 (match_dup 8))) 1114 (clobber (match_scratch:QI 9 ""))])] 1115 " 1116{ 1117 operands[3] = gen_lowpart(QImode, operands[0]); 1118 operands[4] = gen_lowpart(QImode, operands[1]); 1119 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1120 1121 operands[6] = gen_highpart(QImode, operands[0]); 1122 operands[7] = gen_highpart(QImode, operands[0]); 1123 operands[8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1124}") 1125 1126 1127(define_insn "iorhi3" 1128 [(set (match_operand:HI 0 "register_operand" "=A,A,A,A,?A") 1129 (ior:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A,A") 1130 (match_operand:HI 2 "nonmemory_operand" "Z,A,I,M,i")))] 1131 "" 1132 "@ 1133 %0=%u1|%u2 1134 %0=%u1|%u2 1135 %0=%w1|%H2 1136 %0=%b1|%U2 1137 %0=%w1|%H2\;%0=%b0|%U2" 1138 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")]) 1139 1140(define_insn "iorqi3" 1141 [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q") 1142 (ior:QI (match_operand:QI 1 "register_operand" "%uk,uk,uk,uk,0,0,u,k,jq,jq,0,0,q,j,jq,jq") 1143 (match_operand:QI 2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq"))) 1144 (clobber (match_scratch:QI 3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))] 1145 "" 1146 "@ 1147 %m0=%m1|%m2 1148 %m0=%m1|%m2 1149 %m0=%m1|%m2 1150 %m0=%m1|%m2 1151 %m0=%1|%H2 1152 %m0=%1|%H2 1153 %m0=%1|%H2 1154 %m0=%1|%H2 1155 %m0=%m1|%m2 1156 %m0=%m1|%m2 1157 %m0=%b1|%H2 1158 %m0=%b1|%H2 1159 %m0=%b1|%H2 1160 %m0=%b1|%H2 1161 %m0=%m1|%m2 1162 %m0=%m1|%m2" 1163 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")]) 1164 1165 1166 1167(define_split 1168 [(set (match_operand:HI 0 "register_operand" "") 1169 (xor:HI (match_operand:HI 1 "register_operand" "") 1170 (match_operand:HI 2 "const_int_operand" "")))] 1171 "reload_completed && !SMALL_INTVAL(INTVAL(operands[2])) && 1172 !ADD_HIGH_16(INTVAL(operands[2])) 1173 && (REGNO (operands[0]) == REGNO (operands[1]))" 1174 [(parallel [(set (match_dup 3) 1175 (xor:QI (match_dup 4) 1176 (match_dup 5))) 1177 (clobber (match_scratch:QI 6 ""))]) 1178 (parallel [(set (match_dup 7) 1179 (xor:QI (match_dup 8) 1180 (match_dup 9))) 1181 (clobber (match_scratch:QI 10 ""))])] 1182 " 1183{ 1184 operands[3] = gen_lowpart(QImode, operands[0]); 1185 operands[4] = gen_lowpart(QImode, operands[1]); 1186 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1187 1188 operands[7] = gen_highpart(QImode, operands[0]); 1189 operands[8] = gen_highpart(QImode, operands[0]); 1190 operands[9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1191}") 1192 1193(define_split 1194 [(set (match_operand:HI 0 "register_operand" "") 1195 (xor:HI (match_operand:HI 1 "register_operand" "") 1196 (match_operand:HI 2 "const_int_operand" "")))] 1197 "reload_completed && !SMALL_INTVAL(INTVAL(operands[2])) && 1198 !ADD_HIGH_16(INTVAL(operands[2])) 1199 && (REGNO (operands[0]) != REGNO (operands[1]))" 1200 [(parallel [(set (match_dup 3) 1201 (xor:QI (match_dup 4) 1202 (match_dup 5))) 1203 (clobber (match_dup 6))]) 1204 (parallel [(set (match_dup 6) 1205 (xor:QI (match_dup 7) 1206 (match_dup 8))) 1207 (clobber (match_scratch:QI 9 ""))])] 1208 " 1209{ 1210 operands[3] = gen_lowpart(QImode, operands[0]); 1211 operands[4] = gen_lowpart(QImode, operands[1]); 1212 operands[5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1213 1214 operands[6] = gen_highpart(QImode, operands[0]); 1215 operands[7] = gen_highpart(QImode, operands[0]); 1216 operands[8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[2]) & 0xffff0000) >> 16) & 0xffff)); 1217}") 1218 1219(define_insn "xorhi3" 1220 [(set (match_operand:HI 0 "register_operand" "=A,A,A,A,?A") 1221 (xor:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A,A") 1222 (match_operand:HI 2 "nonmemory_operand" "Z,A,I,M,i")))] 1223 "" 1224 "@ 1225 %0=%1^%2 1226 %0=%1^%2 1227 %0=%w1^%H2 1228 %0=%b1^%U2 1229 %0=%w1^%H2\;%0=%b0^%U2" 1230 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")]) 1231 1232(define_insn "xorqi3" 1233 [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q") 1234 (xor:QI (match_operand:QI 1 "register_operand" "%uk,uk,uk,uk,0,0,u,k,jq,jq,0,0,q,j,jq,jq") 1235 (match_operand:QI 2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq"))) 1236 (clobber (match_scratch:QI 3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))] 1237 "" 1238 "@ 1239 %m0=%m1^%m2 1240 %m0=%m1^%m2 1241 %m0=%m1^%m2 1242 %m0=%m1^%m2 1243 %m0=%1^%H2 1244 %m0=%1^%H2 1245 %m0=%1^%H2 1246 %m0=%1^%H2 1247 %m0=%m1^%m2 1248 %m0=%m1^%m2 1249 %m0=%b1^%H2 1250 %m0=%b1^%H2 1251 %m0=%b1^%H2 1252 %m0=%b1^%H2 1253 %m0=%m1^%m2 1254 %m0=%m1^%m2" 1255 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")]) 1256 1257(define_insn "one_cmplhi2" 1258 [(set (match_operand:HI 0 "register_operand" "=A") 1259 (not:HI (match_operand:HI 1 "register_operand" "A")))] 1260 "" 1261 "%0= ~%1" 1262 [(set_attr "type" "special")]) 1263 1264 1265(define_insn "one_cmplqi2" 1266 [(set (match_operand:QI 0 "register_operand" "=k,k,u,u,j,j,q,q") 1267 (not:QI (match_operand:QI 1 "register_operand" "0,u,0,q,0,q,0,j"))) 1268 (clobber (match_scratch:QI 2 "=X,j,X,q,X,k,X,u"))] 1269 "" 1270 "@ 1271 %m0= %1 ^ 0xffff 1272 %m0= %1 ^ 0xffff 1273 %m0= %1 ^ 0xffff 1274 %m0= %1 ^ 0xffff 1275 %m0= %b1 ^ 0xffff 1276 %m0= %b1 ^ 0xffff 1277 %m0= %b1 ^ 0xffff 1278 %m0= %b1 ^ 0xffff" 1279 [(set_attr "type" "f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")]) 1280 1281 1282;; 1283;; MOVE INSTRUCTIONS 1284;; 1285 1286(define_split 1287 [(set (mem:HI (match_operand:QI 0 "register_operand" "")) 1288 (match_operand:HI 1 "register_operand" ""))] 1289 "reload_completed && (operands[0] != stack_pointer_rtx)" 1290 [(set (mem:QI (post_inc:QI (match_dup 0))) 1291 (match_dup 2)) 1292 (set (mem:QI (post_dec:QI (match_dup 0))) 1293 (match_dup 3))] 1294 " 1295{ 1296 operands[2] = gen_highpart(QImode, operands[1]); 1297 operands[3] = gen_lowpart(QImode, operands[1]); 1298}") 1299 1300 1301(define_split 1302 [(set (match_operand:HI 0 "register_operand" "") 1303 (mem:HI (match_operand:QI 1 "register_operand" "")))] 1304 "reload_completed && (operands[1] != stack_pointer_rtx)" 1305 [(set (match_dup 2) 1306 (mem:QI (post_inc:QI (match_dup 1)))) 1307 (set (match_dup 3) 1308 (mem:QI (post_dec:QI (match_dup 1))))] 1309 " 1310{ 1311 operands[2] = gen_highpart(QImode, operands[0]); 1312 operands[3] = gen_lowpart(QImode, operands[0]); 1313}") 1314 1315(define_split 1316 [(set (mem:HI (post_inc:HI (match_operand:QI 0 "register_operand" ""))) 1317 (match_operand:HI 1 "register_operand" ""))] 1318 "reload_completed" 1319 [(set (mem:QI (post_inc:QI (match_dup 0))) 1320 (match_dup 2)) 1321 (set (mem:QI (post_inc:QI (match_dup 0))) 1322 (match_dup 3))] 1323 " 1324{ 1325 operands[2] = gen_highpart(QImode, operands[1]); 1326 operands[3] = gen_lowpart(QImode, operands[1]); 1327}") 1328 1329(define_split 1330 [(set (match_operand:HI 0 "register_operand" "") 1331 (mem:HI (post_inc:HI (match_operand:QI 1 "register_operand" ""))))] 1332 "reload_completed" 1333 [(set (match_dup 2) 1334 (mem:QI (post_inc:QI (match_dup 1)))) 1335 (set (match_dup 3) 1336 (mem:QI (post_inc:QI (match_dup 1))))] 1337 " 1338{ 1339 operands[2] = gen_highpart(QImode, operands[0]); 1340 operands[3] = gen_lowpart(QImode, operands[0]); 1341}") 1342 1343 1344(define_split 1345 [(set (match_operand:HI 0 "register_operand" "") 1346 (match_operand:HI 1 "register_operand" ""))] 1347 "reload_completed && 1348 !(IS_ACCUM_REG (REGNO(operands[0])) && 1349 (REGNO(operands[1]) == REG_PROD || REGNO(operands[1]) == REG_Y))" 1350 [(set (match_dup 2) 1351 (match_dup 3)) 1352 (set (match_dup 4) 1353 (match_dup 5))] 1354 " 1355{ 1356 operands[2] = gen_highpart(QImode, operands[0]); 1357 operands[3] = gen_highpart(QImode, operands[1]); 1358 operands[4] = gen_lowpart(QImode, operands[0]); 1359 operands[5] = gen_lowpart(QImode, operands[1]); 1360}") 1361 1362(define_split 1363 [(set (match_operand:HI 0 "register_operand" "") 1364 (match_operand:HI 1 "const_int_operand" ""))] 1365 "reload_completed" 1366 [(set (match_dup 2) 1367 (match_dup 3)) 1368 (set (match_dup 4) 1369 (match_dup 5))] 1370 " 1371{ 1372 operands[2] = gen_lowpart(QImode, operands[0]); 1373 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); 1374 1375 operands[4] = gen_highpart(QImode, operands[0]); 1376 operands[5] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[1]) & 0xffff0000) >> 16) & 0xffff)); 1377}") 1378 1379(define_expand "movhi" 1380 [(set (match_operand:HI 0 "general_operand" "") 1381 (match_operand:HI 1 "general_operand" ""))] 1382 "" 1383 " 1384{ 1385 if (emit_move_sequence (operands, HImode)) 1386 DONE; 1387}") 1388 1389 1390(define_insn "match_movhi1" 1391 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,Z,A,d,d,m,?d,*Y,t,f") 1392 (match_operand:HI 1 "general_operand" "d,A,K,i,m,d,*Y,?d,t,f"))] 1393 "register_operand(operands[0], HImode) 1394 || register_operand(operands[1], HImode)" 1395 "* 1396{ 1397 switch (which_alternative) 1398 { 1399 /* register to accumulator */ 1400 case 0: 1401 return \"%0=%1\"; 1402 case 1: 1403 return \"%u0=%u1\;%w0=%w1\"; 1404 case 2: 1405 return \"%0=%0^%0\"; 1406 case 3: 1407 return \"%u0=%U1\;%w0=%H1\"; 1408 case 4: 1409 double_reg_from_memory(operands); 1410 return \"\"; 1411 case 5: 1412 double_reg_to_memory(operands); 1413 return \"\"; 1414 case 6: 1415 case 7: 1416 return \"%u0=%u1\;%w0=%w1\"; 1417 case 8: 1418 case 9: 1419 return \"\"; 1420 default: 1421 abort(); 1422 } 1423}" 1424[(set_attr "type" "special,data_move_multiple,f3_alu,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,nothing,nothing")]) 1425 1426 1427;; NOTE: It is cheaper to do 'y = *r0', than 'r0 = *r0'. 1428 1429(define_expand "movqi" 1430 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1431 (match_operand:QI 1 "general_operand" ""))] 1432 "" 1433 " 1434{ 1435 if (emit_move_sequence (operands, QImode)) 1436 DONE; 1437}") 1438 1439;; The movqi pattern with the parallel is used for addqi insns (which have a parallel) 1440;; that are turned into moveqi insns by the flow phase. This happens when an auto-increment 1441;; is detected. 1442 1443(define_insn "match_movqi1" 1444 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>") 1445 (match_operand:QI 1 "general_operand" "r,A,J,i,m<>,D,Y,e,0,m<>,xyz")) 1446 (clobber (match_scratch:QI 2 "=X,X,X,X,X,X,X,X,X,X,X"))])] 1447 "register_operand(operands[0], QImode) 1448 || register_operand(operands[1], QImode)" 1449 "* 1450{ 1451 switch (which_alternative) 1452 { 1453 case 0: 1454 /* We have to use the move mneumonic otherwise the 1610 will 1455 attempt to transfer all 32-bits of 'y', 'p' or an accumulator 1456 , which we don't want */ 1457 if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1458 || IS_ACCUM_REG(REGNO(operands[1]))) 1459 return \"move %0=%1\"; 1460 else 1461 return \"%0=%1\"; 1462 1463 case 1: 1464 return \"%0=%1\"; 1465 1466 case 2: 1467 return \"set %0=%H1\"; 1468 1469 case 3: 1470 return \"%0=%H1\"; 1471 1472 case 4: 1473 return \"%0=%1\"; 1474 1475 case 5: 1476 case 6: 1477 return \"%0=%1\"; 1478 1479 case 7: 1480 return \"%0=%1\"; 1481 1482 case 8: 1483 return \"\"; 1484 1485 case 9: case 10: 1486 return \"%0=%1\"; 1487 default: 1488 abort(); 1489 } 1490}" 1491[(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")]) 1492 1493(define_insn "match_movqi2" 1494 [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>") 1495 (match_operand:QI 1 "general_operand" "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))] 1496 "register_operand(operands[0], QImode) 1497 || register_operand(operands[1], QImode)" 1498 "* 1499{ 1500 switch (which_alternative) 1501 { 1502 case 0: 1503 /* We have to use the move mneumonic otherwise the 1610 will 1504 attempt to transfer all 32-bits of 'y', 'p' or an accumulator 1505 , which we don't want */ 1506 if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1507 || IS_ACCUM_REG(REGNO(operands[1]))) 1508 return \"move %0=%1\"; 1509 else 1510 return \"%0=%1\"; 1511 1512 case 1: 1513 return \"%0=%1\"; 1514 1515 case 2: 1516 return \"set %0=%H1\"; 1517 1518 case 3: 1519 return \"%0=%H1\"; 1520 1521 case 4: 1522 return \"%0=%1\"; 1523 1524 case 5: 1525 case 6: 1526 return \"%0=%1\"; 1527 1528 case 7: 1529 return \"%0=%1\"; 1530 1531 case 8: 1532 return \"\"; 1533 1534 case 9: case 10: 1535 return \"%0=%1\"; 1536 default: 1537 abort(); 1538 } 1539}" 1540[(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")]) 1541 1542(define_expand "reload_inqi" 1543 [(set (match_operand:QI 0 "register_operand" "=u") 1544 (match_operand:QI 1 "sp_operand" "")) 1545 (clobber (match_operand:QI 2 "register_operand" "=&q"))] 1546 "" 1547 " 1548{ 1549 rtx addr_reg = XEXP (operands[1], 0); 1550 rtx offset = XEXP (operands[1], 1); 1551 1552 /* First, move the frame or stack pointer to the accumulator */ 1553 emit_move_insn (operands[0], addr_reg); 1554 1555 /* Then generate the add insn */ 1556 emit_insn (gen_rtx_PARALLEL 1557 (VOIDmode, 1558 gen_rtvec (2, 1559 gen_rtx_SET (VOIDmode, operands[0], 1560 gen_rtx_PLUS (QImode, operands[0], 1561 offset)), 1562 gen_rtx_CLOBBER (VOIDmode, operands[2])))); 1563 DONE; 1564}") 1565 1566(define_expand "reload_inhi" 1567 [(set (match_operand:HI 0 "register_operand" "=r") 1568 (match_operand:HI 1 "register_operand" "r")) 1569 (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1570 "" 1571 " 1572{ 1573 /* Check for an overlap of operand 2 (an accumulator) with 1574 the msw of operand 0. If we have an overlap we must reverse 1575 the order of the moves. */ 1576 1577 if (REGNO(operands[2]) == REGNO(operands[0])) 1578 { 1579 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1580 emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1581 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1582 emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1583 } 1584 else 1585 { 1586 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1587 emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1588 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1589 emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1590 } 1591 1592 DONE; 1593}") 1594 1595 1596(define_expand "reload_outhi" 1597 [(set (match_operand:HI 0 "register_operand" "=r") 1598 (match_operand:HI 1 "register_operand" "r")) 1599 (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1600 "" 1601 " 1602{ 1603 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1604 emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1605 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1606 emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1607 DONE; 1608}") 1609 1610(define_expand "movstrqi" 1611 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 1612 (match_operand:BLK 1 "memory_operand" "")) 1613 (use (match_operand:QI 2 "const_int_operand" "")) 1614 (use (match_operand:QI 3 "const_int_operand" "")) 1615 (clobber (match_scratch:QI 4 "")) 1616 (clobber (match_dup 5)) 1617 (clobber (match_dup 6))])] 1618 "" 1619 " 1620{ 1621 rtx addr0, addr1; 1622 1623 if (GET_CODE (operands[2]) != CONST_INT) 1624 FAIL; 1625 1626 if (INTVAL(operands[2]) > 127) 1627 FAIL; 1628 1629 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 1630 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 1631 1632 operands[5] = addr0; 1633 operands[6] = addr1; 1634 1635 operands[0] = change_address (operands[0], VOIDmode, addr0); 1636 operands[1] = change_address (operands[1], VOIDmode, addr1); 1637}") 1638 1639(define_insn "" 1640 [(set (mem:BLK (match_operand:QI 0 "register_operand" "a")) 1641 (mem:BLK (match_operand:QI 1 "register_operand" "a"))) 1642 (use (match_operand:QI 2 "const_int_operand" "n")) 1643 (use (match_operand:QI 3 "immediate_operand" "i")) 1644 (clobber (match_scratch:QI 4 "=x")) 1645 (clobber (match_dup 0)) 1646 (clobber (match_dup 1))] 1647 "" 1648 "* 1649{ return output_block_move (operands); }") 1650 1651 1652;; Floating point move insns 1653 1654 1655(define_expand "movhf" 1656 [(set (match_operand:HF 0 "general_operand" "") 1657 (match_operand:HF 1 "general_operand" ""))] 1658 "" 1659 " 1660{ 1661 if (emit_move_sequence (operands, HFmode)) 1662 DONE; 1663}") 1664 1665(define_insn "match_movhf" 1666 [(set (match_operand:HF 0 "nonimmediate_operand" "=A,Z,d,d,m,d,Y") 1667 (match_operand:HF 1 "general_operand" "d,A,F,m,d,Y,d"))] 1668 "" 1669 "* 1670{ 1671 /* NOTE: When loading the register 16 bits at a time we 1672 MUST load the high half FIRST (because the 1610 zeros 1673 the low half) and then load the low half */ 1674 1675 switch (which_alternative) 1676 { 1677 /* register to accumulator */ 1678 case 0: 1679 return \"%0=%1\"; 1680 case 1: 1681 return \"%u0=%u1\;%w0=%w1\"; 1682 case 2: 1683 output_dsp16xx_float_const(operands); 1684 return \"\"; 1685 case 3: 1686 double_reg_from_memory(operands); 1687 return \"\"; 1688 case 4: 1689 double_reg_to_memory(operands); 1690 return \"\"; 1691 case 5: 1692 case 6: 1693 return \"%u0=%u1\;%w0=%w1\"; 1694 default: 1695 abort(); 1696 } 1697}" 1698[(set_attr "type" "move,move,load_i,load,store,load,store")]) 1699 1700 1701 1702(define_expand "reload_inhf" 1703 [(set (match_operand:HF 0 "register_operand" "=r") 1704 (match_operand:HF 1 "register_operand" "r")) 1705 (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1706 "" 1707 " 1708{ 1709 /* Check for an overlap of operand 2 (an accumulator) with 1710 the msw of operand 0. If we have an overlap we must reverse 1711 the order of the moves. */ 1712 1713 if (REGNO(operands[2]) == REGNO(operands[0])) 1714 { 1715 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1716 emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1717 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1718 emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1719 } 1720 else 1721 { 1722 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1723 emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1724 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1725 emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1726 } 1727 1728 DONE; 1729}") 1730 1731(define_expand "reload_outhf" 1732 [(set (match_operand:HF 0 "register_operand" "=r") 1733 (match_operand:HF 1 "register_operand" "r")) 1734 (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1735 "" 1736 " 1737{ 1738 emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1739 emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1740 emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1741 emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1742 DONE; 1743}") 1744 1745 1746;; 1747;; CONVERSION INSTRUCTIONS 1748;; 1749 1750(define_expand "extendqihi2" 1751 [(clobber (match_dup 2)) 1752 (set (match_dup 3) (match_operand:QI 1 "register_operand" "")) 1753 (set (match_operand:HI 0 "register_operand" "") 1754 (ashift:HI (match_dup 2) 1755 (const_int 16))) 1756 (set (match_dup 0) 1757 (ashiftrt:HI (match_dup 0) (const_int 16)))] 1758 "" 1759 " 1760{ 1761 operands[2] = gen_reg_rtx (HImode); 1762 operands[3] = gen_rtx_SUBREG (QImode, operands[2], 1); 1763}") 1764 1765(define_insn "internal_extendqihi2" 1766 [(set (match_operand:HI 0 "register_operand" "=A") 1767 (sign_extend:HI (match_operand:QI 1 "register_operand" "ku")))] 1768 "TARGET_BMU" 1769 "%0 = extracts(%m1, 0x1000)" 1770[(set_attr "type" "shift_i")]) 1771 1772;;(define_insn "extendqihi2" 1773;; [(set (match_operand:HI 0 "register_operand" "=A") 1774;; (sign_extend:HI (match_operand:QI 1 "register_operand" "h")))] 1775;; "" 1776;; "%0 = %1 >> 16") 1777 1778;;(define_insn "zero_extendqihi2" 1779;; [(set (match_operand:HI 0 "register_operand" "=t,f,A,?d,?A") 1780;; (zero_extend:HI (match_operand:QI 1 "register_operand" "w,z,ku,A,r")))] 1781;; "" 1782;; "* 1783;; { 1784;; switch (which_alternative) 1785;; { 1786;; case 0: 1787;; case 1: 1788;; return \"%0=0\"; 1789;; 1790;; case 2: 1791;; if (REGNO(operands[1]) == (REGNO(operands[0]) + 1)) 1792;; return \"%0=0\"; 1793;; else 1794;; return \"%w0=%1\;%0=0\"; 1795;; case 3: 1796;; return \"%w0=%1\;%0=0\"; 1797;; 1798;; case 4: 1799;; if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1800;; || IS_ACCUM_REG(REGNO(operands[1]))) 1801;; return \"move %w0=%1\;%0=0\"; 1802;; else 1803;; return \"%w0=%1\;%0=0\"; 1804;; default: 1805;; abort(); 1806;; } 1807;; }") 1808 1809;;(define_expand "zero_extendqihi2" 1810;; [(clobber (match_dup 2)) 1811;; (set (match_dup 3) (match_operand:QI 1 "register_operand" "")) 1812;; (set (match_operand:HI 0 "register_operand" "") 1813;; (ashift:HI (match_dup 2) 1814;; (const_int 16))) 1815;; (set (match_dup 0) 1816;; (lshiftrt:HI (match_dup 0) (const_int 16)))] 1817;; "" 1818;; " 1819;;{ 1820;; operands[2] = gen_reg_rtx (HImode); 1821;; operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1); 1822;;}") 1823 1824(define_expand "zero_extendqihi2" 1825 [(set (match_operand:HI 0 "register_operand" "") 1826 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 1827 "" 1828 "") 1829 1830 1831(define_insn "match_zero_extendqihi_bmu" 1832 [(set (match_operand:HI 0 "register_operand" "=?*Z,?*Z,?A,A") 1833 (zero_extend:HI (match_operand:QI 1 "register_operand" "?A,?*Y,*Z*x*a*W*Y,ku")))] 1834 "TARGET_BMU" 1835 "* 1836 { 1837 switch (which_alternative) 1838 { 1839 case 0: 1840 return \"%w0=%1\;%0=0\"; 1841 1842 case 1: 1843 return \"%w0=%1\;%0=0\"; 1844 1845 case 2: 1846 if (REGNO(operands[1]) == (REGNO(operands[0]) + 1)) 1847 return \"%0=0\"; 1848 else if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1849 || IS_ACCUM_REG(REGNO(operands[1]))) 1850 { 1851 return \"move %w0=%1\;%0=0\"; 1852 } 1853 else 1854 return \"%w0=%1\;%0=0\"; 1855 1856 case 3: 1857 return \"%0 = extractz(%m1, 0x1000)\"; 1858 default: 1859 abort(); 1860 } 1861 }" 1862 [(set_attr "type" "data_move_2,data_move_2,data_move_2,shift_i")]) 1863 1864(define_insn "match_zero_extendqihi2_nobmu" 1865 [(set (match_operand:HI 0 "register_operand" "=?Z,?Z,A") 1866 (zero_extend:HI (match_operand:QI 1 "register_operand" "A,Y,r")))] 1867 "" 1868 "* 1869 { 1870 switch (which_alternative) 1871 { 1872 case 0: 1873 return \"%w0=%1\;%0=0\"; 1874 1875 case 1: 1876 return \"%w0=%1\;%0=0\"; 1877 1878 case 2: 1879 if (REGNO(operands[1]) + 1 == (REGNO(operands[0]) + 1)) 1880 return \"%0=0\"; 1881 else if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1882 || IS_ACCUM_REG(REGNO(operands[1]))) 1883 { 1884 return \"move %w0=%1\;%0=0\"; 1885 } 1886 else 1887 return \"%w0=%1\;%0=0\"; 1888 default: 1889 abort(); 1890 } 1891 }" 1892 [(set_attr "type" "data_move_2,data_move_2,data_move_2")]) 1893 1894;; 1895;; Floating point conversions 1896;; 1897(define_expand "floathihf2" 1898 [(set (match_operand:HF 0 "register_operand" "") 1899 (float:HF (match_operand:HI 1 "register_operand" "")))] 1900 "" 1901 " 1902{ 1903 if (!dsp16xx_floathihf2_libcall) 1904 dsp16xx_floathihf2_libcall = gen_rtx_SYMBOL_REF (Pmode, FLOATHIHF2_LIBCALL); 1905 1906 emit_library_call (dsp16xx_floathihf2_libcall, 1, HFmode, 1, 1907 operands[1], HImode); 1908 emit_move_insn (operands[0], hard_libcall_value(HFmode)); 1909 DONE; 1910}") 1911 1912(define_expand "fix_trunchfhi2" 1913 [(set (match_operand:HI 0 "register_operand" "") 1914 (fix:HI (match_operand:HF 1 "register_operand" "")))] 1915 "" 1916 " 1917{ 1918 if (!dsp16xx_fixhfhi2_libcall) 1919 dsp16xx_fixhfhi2_libcall = gen_rtx_SYMBOL_REF (Pmode, FIXHFHI2_LIBCALL); 1920 1921 emit_library_call (dsp16xx_fixhfhi2_libcall, 1, HImode, 1, 1922 operands[1], HFmode); 1923 emit_move_insn (operands[0], hard_libcall_value(HImode)); 1924 DONE; 1925}") 1926 1927(define_expand "fixuns_trunchfhi2" 1928 [(set (match_operand:HI 0 "register_operand" "") 1929 (unsigned_fix:HI (match_operand:HF 1 "register_operand" "")))] 1930 "" 1931 " 1932{ 1933 rtx reg1 = gen_reg_rtx (HFmode); 1934 rtx reg2 = gen_reg_rtx (HFmode); 1935 rtx reg3 = gen_reg_rtx (HImode); 1936 rtx label1 = gen_label_rtx (); 1937 rtx label2 = gen_label_rtx (); 1938 REAL_VALUE_TYPE offset; 1939 1940 real_2expN (&offset, 31); 1941 1942 if (reg1) /* turn off complaints about unreached code */ 1943 { 1944 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, HFmode)); 1945 do_pending_stack_adjust (); 1946 1947 emit_insn (gen_cmphf (operands[1], reg1)); 1948 emit_jump_insn (gen_bge (label1)); 1949 1950 emit_insn (gen_fix_trunchfhi2 (operands[0], operands[1])); 1951 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 1952 gen_rtx_LABEL_REF (VOIDmode, label2))); 1953 emit_barrier (); 1954 1955 emit_label (label1); 1956 emit_insn (gen_subhf3 (reg2, operands[1], reg1)); 1957 emit_move_insn (reg3, GEN_INT (0x80000000));; 1958 1959 emit_insn (gen_fix_trunchfhi2 (operands[0], reg2)); 1960 emit_insn (gen_iorhi3 (operands[0], operands[0], reg3)); 1961 1962 emit_label (label2); 1963 1964 /* allow REG_NOTES to be set on last insn (labels don't have enough 1965 fields, and can't be used for REG_NOTES anyway). */ 1966 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 1967 DONE; 1968 } 1969}") 1970 1971;; 1972;; SHIFT INSTRUCTIONS 1973;; 1974 1975(define_insn "" 1976 [(set (match_operand:HI 0 "register_operand" "=A") 1977 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1978 (const_int 1)))] 1979 "" 1980 "%0=%1>>1" 1981 [(set_attr "type" "special")]) 1982 1983(define_insn "" 1984 [(set (match_operand:HI 0 "register_operand" "=A") 1985 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1986 (const_int 4)))] 1987 "" 1988 "%0=%1>>4" 1989 [(set_attr "type" "special")]) 1990 1991(define_insn "" 1992 [(set (match_operand:HI 0 "register_operand" "=A") 1993 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1994 (const_int 8)))] 1995 "" 1996 "%0=%1>>8" 1997 [(set_attr "type" "special")]) 1998 1999(define_insn "" 2000 [(set (match_operand:HI 0 "register_operand" "=A") 2001 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 2002 (const_int 16)))] 2003 "" 2004 "%0=%1>>16" 2005 [(set_attr "type" "special")]) 2006 2007;; 2008;; Arithmetic Right shift 2009 2010(define_expand "ashrhi3" 2011 [(set (match_operand:HI 0 "register_operand" "") 2012 (ashiftrt:HI (match_operand:HI 1 "register_operand" "") 2013 (match_operand:QI 2 "nonmemory_operand" "")))] 2014 "" 2015 " 2016{ 2017 if (!TARGET_BMU) 2018 { 2019 /* If we are shifting by a constant we can do it in 1 or more 2020 1600 core shift instructions. The core instructions can 2021 shift by 1, 4, 8, or 16. */ 2022 2023 if (GET_CODE(operands[2]) == CONST_INT) 2024 ; 2025 else 2026 { 2027 rtx label1 = gen_label_rtx (); 2028 rtx label2 = gen_label_rtx (); 2029 2030#if 0 2031 if (!dsp16xx_ashrhi3_libcall) 2032 dsp16xx_ashrhi3_libcall 2033 = gen_rtx_SYMBOL_REF (Pmode, ASHRHI3_LIBCALL); 2034 2035 emit_library_call (dsp16xx_ashrhi3_libcall, 1, HImode, 2, 2036 operands[1], HImode, 2037 operands[2], QImode); 2038 emit_move_insn (operands[0], hard_libcall_value(HImode)); 2039 DONE; 2040#else 2041 do_pending_stack_adjust (); 2042 emit_insn (gen_tstqi (operands[2])); 2043 emit_jump_insn (gen_bne (label1)); 2044 emit_move_insn (operands[0], operands[1]); 2045 emit_jump_insn (gen_jump (label2)); 2046 emit_barrier (); 2047 emit_label (label1); 2048 2049 if (GET_CODE(operands[2]) != MEM) 2050 { 2051 rtx stack_slot; 2052 2053 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 2054 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 2055 emit_move_insn (stack_slot, operands[2]); 2056 operands[2] = stack_slot; 2057 } 2058 2059 emit_insn (gen_match_ashrhi3_nobmu (operands[0], operands[1], operands[2])); 2060 emit_label (label2); 2061 DONE; 2062#endif 2063 } 2064 } 2065}") 2066 2067(define_insn "match_ashrhi3_bmu" 2068 [(set (match_operand:HI 0 "register_operand" "=A,A,A") 2069 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A") 2070 (match_operand:QI 2 "nonmemory_operand" "B,I,h")))] 2071 "TARGET_BMU" 2072 "@ 2073 %0=%1>>%2 2074 %0=%1>>%H2 2075 %0=%1>>%2" 2076 [(set_attr "type" "shift,shift_i,shift")]) 2077 2078(define_insn "match_ashrhi3_nobmu" 2079 [(set (match_operand:HI 0 "register_operand" "=A,A") 2080 (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,0") 2081 (match_operand:QI 2 "general_operand" "n,m")))] 2082 "!TARGET_BMU" 2083 "* 2084{ 2085 if (which_alternative == 0) 2086 { 2087 emit_1600_core_shift (ASHIFTRT, operands, INTVAL(operands[2])); 2088 return \"\"; 2089 } 2090 else 2091 { 2092 output_asm_insn (\"cloop=%2\", operands); 2093 output_asm_insn (\"do 0 {\", operands); 2094 output_asm_insn (\"%0=%0>>1\", operands); 2095 return \"}\"; 2096 } 2097}") 2098 2099 2100 2101;; 2102;; Logical Right Shift 2103 2104(define_insn "" 2105 [(set (match_operand:HI 0 "register_operand" "=A") 2106 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 2107 (const_int 1)))] 2108 "!TARGET_BMU" 2109 "%0=%1>>1\;%0=%b0&0x7fff" 2110 [(set_attr "type" "special")]) 2111 2112(define_insn "" 2113 [(set (match_operand:HI 0 "register_operand" "=A") 2114 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 2115 (const_int 4)))] 2116 "!TARGET_BMU" 2117 "%0=%1>>4\;%0=%b0&0x0fff" 2118 [(set_attr "type" "special")]) 2119 2120(define_insn "" 2121 [(set (match_operand:HI 0 "register_operand" "=A") 2122 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 2123 (const_int 8)))] 2124 "!TARGET_BMU" 2125 "%0=%1>>8\;%0=%b0&0x00ff" 2126 [(set_attr "type" "special")]) 2127 2128(define_insn "" 2129 [(set (match_operand:HI 0 "register_operand" "=A") 2130 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 2131 (const_int 16)))] 2132 "!TARGET_BMU" 2133 "%0=%1>>16\;%0=%b0&0x0000" 2134 [(set_attr "type" "special")]) 2135 2136(define_expand "lshrhi3" 2137 [(set (match_operand:HI 0 "register_operand" "") 2138 (lshiftrt:HI (match_operand:HI 1 "register_operand" "") 2139 (match_operand:QI 2 "nonmemory_operand" "")))] 2140 "" 2141 " 2142{ 2143 if (!TARGET_BMU) 2144 { 2145 /* If we are shifting by a constant we can do it in 1 or more 2146 1600 core shift instructions. The core instructions can 2147 shift by 1, 4, 8, or 16. */ 2148 2149 if (GET_CODE(operands[2]) == CONST_INT) 2150 emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2])); 2151 else 2152 { 2153 rtx label1 = gen_label_rtx (); 2154 rtx label2 = gen_label_rtx (); 2155#if 0 2156 if (!dsp16xx_lshrhi3_libcall) 2157 dsp16xx_lshrhi3_libcall 2158 = gen_rtx_SYMBOL_REF (Pmode, LSHRHI3_LIBCALL); 2159 2160 emit_library_call (dsp16xx_lshrhi3_libcall, 1, HImode, 2, 2161 operands[1], HImode, 2162 operands[2], QImode); 2163 emit_move_insn (operands[0], hard_libcall_value(HImode)); 2164 DONE; 2165#else 2166 do_pending_stack_adjust (); 2167 emit_insn (gen_tstqi (operands[2])); 2168 emit_jump_insn (gen_bne (label1)); 2169 emit_move_insn (operands[0], operands[1]); 2170 emit_jump_insn (gen_jump (label2)); 2171 emit_barrier (); 2172 emit_label (label1); 2173 2174 if (GET_CODE(operands[2]) != MEM) 2175 { 2176 rtx stack_slot; 2177 2178 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 2179 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 2180 emit_move_insn (stack_slot, operands[2]); 2181 operands[2] = stack_slot; 2182 } 2183 2184 emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2])); 2185 emit_label (label2); 2186 DONE; 2187#endif 2188 } 2189 } 2190}") 2191 2192(define_insn "match_lshrhi3" 2193 [(set (match_operand:HI 0 "register_operand" "=A,A,A") 2194 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A") 2195 (match_operand:QI 2 "nonmemory_operand" "B,I,h")))] 2196 "TARGET_BMU" 2197 "@ 2198 %0=%1>>>%2 2199 %0=%1>>>%H2 2200 %0=%1>>>%2" 2201 [(set_attr "type" "shift,shift_i,shift")]) 2202 2203(define_insn "match_lshrhi3_nobmu" 2204 [(set (match_operand:HI 0 "register_operand" "=A,A") 2205 (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,0") 2206 (match_operand:QI 2 "general_operand" "n,m"))) 2207 (clobber (match_scratch:QI 3 "=X,Y"))] 2208 "!TARGET_BMU" 2209 "* 2210{ 2211 if (which_alternative == 0) 2212 { 2213 emit_1600_core_shift (LSHIFTRT, operands, INTVAL(operands[2])); 2214 return \"\"; 2215 } 2216 else 2217 { 2218 output_asm_insn (\"%3=psw\;psw=0\",operands); 2219 output_asm_insn (\"cloop=%2\", operands); 2220 output_asm_insn (\"do 0 {\", operands); 2221 output_asm_insn (\"%0=%0>>1\", operands); 2222 output_asm_insn (\"}\", operands); 2223 return \"psw=%3\"; 2224 } 2225}") 2226 2227 2228;; 2229;; Arithmetic Left shift 2230 2231;; Start off with special case arithmetic left shift by 1,4,8 or 16. 2232 2233 2234(define_insn "" 2235 [(set (match_operand:HI 0 "register_operand" "=A") 2236 (ashift:HI (match_operand:HI 1 "register_operand" "A") 2237 (const_int 1)))] 2238 "" 2239 "%0=%1<<1" 2240 [(set_attr "type" "special")]) 2241 2242(define_insn "" 2243 [(set (match_operand:HI 0 "register_operand" "=A") 2244 (ashift:HI (match_operand:HI 1 "register_operand" "A") 2245 (const_int 4)))] 2246 "" 2247 "%0=%1<<4" 2248 [(set_attr "type" "special")]) 2249 2250(define_insn "" 2251 [(set (match_operand:HI 0 "register_operand" "=A") 2252 (ashift:HI (match_operand:HI 1 "register_operand" "A") 2253 (const_int 8)))] 2254 "" 2255 "%0=%1<<8" 2256 [(set_attr "type" "special")]) 2257 2258(define_insn "" 2259 [(set (match_operand:HI 0 "register_operand" "=A") 2260 (ashift:HI (match_operand:HI 1 "general_operand" "A") 2261 (const_int 16)))] 2262 "" 2263 "%0=%1<<16" 2264 [(set_attr "type" "special")]) 2265 2266 2267 2268;; Normal Arithmetic Shift Left 2269 2270 2271(define_expand "ashlhi3" 2272 [(set (match_operand:HI 0 "register_operand" "") 2273 (ashift:HI (match_operand:HI 1 "register_operand" "") 2274 (match_operand:QI 2 "nonmemory_operand" "")))] 2275 "" 2276 " 2277{ 2278 if (!TARGET_BMU) 2279 { 2280 /* If we are shifting by a constant we can do it in 1 or more 2281 1600 core shift instructions. The core instructions can 2282 shift by 1, 4, 8, or 16. */ 2283 2284 if (GET_CODE(operands[2]) == CONST_INT) 2285 ; 2286 else 2287 { 2288 rtx label1 = gen_label_rtx (); 2289 rtx label2 = gen_label_rtx (); 2290#if 0 2291 if (!dsp16xx_ashlhi3_libcall) 2292 dsp16xx_ashlhi3_libcall 2293 = gen_rtx_SYMBOL_REF (Pmode, ASHLHI3_LIBCALL); 2294 2295 emit_library_call (dsp16xx_ashlhi3_libcall, 1, HImode, 2, 2296 operands[1], HImode, operands[2], QImode); 2297 emit_move_insn (operands[0], hard_libcall_value(HImode)); 2298 DONE; 2299#else 2300 do_pending_stack_adjust (); 2301 emit_insn (gen_tstqi (operands[2])); 2302 emit_jump_insn (gen_bne (label1)); 2303 emit_move_insn (operands[0], operands[1]); 2304 emit_jump_insn (gen_jump (label2)); 2305 emit_barrier (); 2306 emit_label (label1); 2307 2308 if (GET_CODE(operands[2]) != MEM) 2309 { 2310 rtx stack_slot; 2311 2312 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 2313 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 2314 emit_move_insn (stack_slot, operands[2]); 2315 operands[2] = stack_slot; 2316 } 2317 emit_insn (gen_match_ashlhi3_nobmu (operands[0], operands[1], operands[2])); 2318 emit_label (label2); 2319 DONE; 2320#endif 2321 } 2322 } 2323}") 2324 2325(define_insn "match_ashlhi3" 2326 [(set (match_operand:HI 0 "register_operand" "=A,A,A") 2327 (ashift:HI (match_operand:HI 1 "register_operand" "A,A,A") 2328 (match_operand:QI 2 "nonmemory_operand" "B,I,!h")))] 2329 "TARGET_BMU" 2330 "@ 2331 %0=%1<<%2\;move %u0=%u0 2332 %0=%1<<%H2\;move %u0=%u0 2333 %0=%1<<%2\;move %u0=%u0" 2334 [(set_attr "type" "shift_multiple,shift_multiple,shift_multiple")]) 2335 2336(define_insn "match_ashlhi3_nobmu" 2337 [(set (match_operand:HI 0 "register_operand" "=A,A") 2338 (ashift:HI (match_operand:HI 1 "register_operand" "A,0") 2339 (match_operand:QI 2 "general_operand" "n,m")))] 2340 "!TARGET_BMU" 2341 "* 2342{ 2343 if (which_alternative == 0) 2344 { 2345 emit_1600_core_shift (ASHIFT, operands, INTVAL(operands[2])); 2346 return \"\"; 2347 } 2348 else 2349 { 2350 output_asm_insn (\"cloop=%2\", operands); 2351 output_asm_insn (\"do 0 {\", operands); 2352 output_asm_insn (\"%0=%0<<1\", operands); 2353 return \"}\"; 2354 } 2355}") 2356 2357 2358 2359 2360(define_insn "extv" 2361 [(set (match_operand:QI 0 "register_operand" "=k,u") 2362 (sign_extract:QI (match_operand:QI 1 "register_operand" "ku,ku") 2363 (match_operand:QI 2 "const_int_operand" "n,n") 2364 (match_operand:QI 3 "const_int_operand" "n,n"))) 2365 (clobber (match_scratch:QI 4 "=j,q"))] 2366 "TARGET_BMU" 2367 "* 2368{ 2369 operands[5] 2370 = GEN_INT ((INTVAL (operands[2]) << 8) + (INTVAL (operands[3]) & 0xff)); 2371 return \"%m0 = extracts (%m1, %H5)\"; 2372}" 2373[(set_attr "type" "shift_i")]) 2374 2375(define_insn "extzv" 2376 [(set (match_operand:QI 0 "register_operand" "=k,u") 2377 (zero_extract:QI (match_operand:QI 1 "register_operand" "ku,ku") 2378 (match_operand:QI 2 "const_int_operand" "n,n") 2379 (match_operand:QI 3 "const_int_operand" "n,n"))) 2380 (clobber (match_scratch:QI 4 "=j,q"))] 2381 "TARGET_BMU" 2382 "* 2383{ 2384 operands[5] 2385 = GEN_INT ((INTVAL (operands[2]) << 8) + (INTVAL (operands[3]) & 0xff)); 2386 return \"%m0 = extractz (%m1, %H5)\"; 2387}" 2388[(set_attr "type" "shift_i")]) 2389 2390;; 2391;; conditional instructions 2392;; 2393 2394(define_expand "seq" 2395 [(set (match_operand:QI 0 "register_operand" "") 2396 (eq:QI (match_dup 1) (const_int 0)))] 2397 "" 2398 " 2399{ 2400 if (dsp16xx_compare_gen == gen_compare_reg) 2401 operands[1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1); 2402 else 2403 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2404}") 2405 2406(define_expand "sne" 2407 [(set (match_operand:QI 0 "register_operand" "") 2408 (ne:QI (match_dup 1) (const_int 0)))] 2409 "" 2410 " 2411{ 2412 if (dsp16xx_compare_gen == gen_compare_reg) 2413 operands[1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2414 else 2415 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2416}") 2417 2418 2419(define_expand "sgt" 2420 [(set (match_operand:QI 0 "register_operand" "") 2421 (gt:QI (match_dup 1) (const_int 0)))] 2422 "" 2423 " 2424{ 2425 if (dsp16xx_compare_gen == gen_compare_reg) 2426 operands[1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1); 2427 else 2428 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2429}") 2430 2431 2432(define_expand "slt" 2433 [(set (match_operand:QI 0 "register_operand" "") 2434 (lt:QI (match_dup 1) (const_int 0)))] 2435 "" 2436 " 2437{ 2438 if (dsp16xx_compare_gen == gen_compare_reg) 2439 operands[1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1); 2440 else 2441 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2442}") 2443 2444(define_expand "sge" 2445 [(set (match_operand:QI 0 "register_operand" "") 2446 (ge:QI (match_dup 1) (const_int 0)))] 2447 "" 2448 " 2449{ 2450 if (dsp16xx_compare_gen == gen_compare_reg) 2451 operands[1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2452 else 2453 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2454}") 2455 2456 2457(define_expand "sle" 2458 [(set (match_operand:QI 0 "register_operand" "") 2459 (le:QI (match_dup 1) (const_int 0)))] 2460 "" 2461 " 2462{ 2463 if (dsp16xx_compare_gen == gen_compare_reg) 2464 operands[1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2465 else 2466 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2467}") 2468 2469 2470(define_expand "sgtu" 2471 [(set (match_operand:QI 0 "register_operand" "") 2472 (gtu:QI (match_dup 1) (const_int 0)))] 2473 "" 2474 " 2475{ 2476 if (dsp16xx_compare_gen == gen_compare_reg) 2477 operands[1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2478 else 2479 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2480}") 2481 2482 2483(define_expand "sltu" 2484 [(set (match_operand:QI 0 "register_operand" "") 2485 (ltu:QI (match_dup 1) (const_int 0)))] 2486 "" 2487 " 2488{ 2489 if (dsp16xx_compare_gen == gen_compare_reg) 2490 operands[1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2491 else 2492 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2493}") 2494 2495 2496(define_expand "sgeu" 2497 [(set (match_operand:QI 0 "register_operand" "") 2498 (geu:QI (match_dup 1) (const_int 0)))] 2499 "" 2500 " 2501{ 2502 if (dsp16xx_compare_gen == gen_compare_reg) 2503 operands[1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2504 else 2505 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2506}") 2507 2508 2509(define_expand "sleu" 2510 [(set (match_operand:QI 0 "register_operand" "") 2511 (leu:QI (match_dup 1) (const_int 0)))] 2512 "" 2513 " 2514{ 2515 if (dsp16xx_compare_gen == gen_compare_reg) 2516 operands[1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2517 else 2518 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2519}") 2520 2521 2522(define_insn "scc" 2523 [(set (match_operand:QI 0 "register_operand" "=jq") 2524 (match_operator:QI 1 "comparison_operator" [(cc0) (const_int 0)]))] 2525 "" 2526 "%0 = 0\;if %C1 %b0 = %b0 + 1" 2527 [(set_attr "type" "special_2")]) 2528 2529;; 2530;; Jump Instructions 2531;; 2532 2533(define_expand "beq" 2534 [(set (pc) 2535 (if_then_else (eq (match_dup 1) 2536 (const_int 0)) 2537 (label_ref (match_operand 0 "" "")) 2538 (pc)))] 2539 "" 2540 " 2541{ 2542 if (dsp16xx_compare_gen == gen_compare_reg) 2543 operands[1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1); 2544 else 2545 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2546}") 2547 2548(define_expand "bne" 2549 [(set (pc) 2550 (if_then_else (ne (match_dup 1) 2551 (const_int 0)) 2552 (label_ref (match_operand 0 "" "")) 2553 (pc)))] 2554 "" 2555 " 2556{ 2557 if (dsp16xx_compare_gen == gen_compare_reg) 2558 operands[1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2559 else 2560 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2561}") 2562 2563 2564(define_expand "bgt" 2565 [(set (pc) 2566 (if_then_else (gt (match_dup 1) 2567 (const_int 0)) 2568 (label_ref (match_operand 0 "" "")) 2569 (pc)))] 2570 "" 2571 " 2572{ 2573 if (dsp16xx_compare_gen == gen_compare_reg) 2574 operands[1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1); 2575 else 2576 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2577}") 2578 2579 2580(define_expand "bge" 2581 [(set (pc) 2582 (if_then_else (ge (match_dup 1) 2583 (const_int 0)) 2584 (label_ref (match_operand 0 "" "")) 2585 (pc)))] 2586 "" 2587 " 2588{ 2589 if (dsp16xx_compare_gen == gen_compare_reg) 2590 operands[1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2591 else 2592 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2593}") 2594 2595 2596(define_expand "blt" 2597 [(set (pc) 2598 (if_then_else (lt (match_dup 1) 2599 (const_int 0)) 2600 (label_ref (match_operand 0 "" "")) 2601 (pc)))] 2602 "" 2603 " 2604{ 2605 if (dsp16xx_compare_gen == gen_compare_reg) 2606 operands[1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1); 2607 else 2608 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2609}") 2610 2611 2612(define_expand "ble" 2613 [(set (pc) 2614 (if_then_else (le (match_dup 1) 2615 (const_int 0)) 2616 (label_ref (match_operand 0 "" "")) 2617 (pc)))] 2618 "" 2619 " 2620{ 2621 if (dsp16xx_compare_gen == gen_compare_reg) 2622 operands[1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1); 2623 else 2624 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2625}") 2626 2627 2628(define_expand "bgtu" 2629 [(set (pc) 2630 (if_then_else (gtu (match_dup 1) 2631 (const_int 0)) 2632 (label_ref (match_operand 0 "" "")) 2633 (pc)))] 2634 "" 2635 " 2636{ 2637 if (dsp16xx_compare_gen == gen_compare_reg) 2638 operands[1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2639 else 2640 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2641}") 2642 2643 2644(define_expand "bgeu" 2645 [(set (pc) 2646 (if_then_else (geu (match_dup 1) 2647 (const_int 0)) 2648 (label_ref (match_operand 0 "" "")) 2649 (pc)))] 2650 "" 2651 " 2652{ 2653 if (dsp16xx_compare_gen == gen_compare_reg) 2654 operands[1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2655 else 2656 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2657}") 2658 2659 2660(define_expand "bltu" 2661 [(set (pc) 2662 (if_then_else (ltu (match_dup 1) 2663 (const_int 0)) 2664 (label_ref (match_operand 0 "" "")) 2665 (pc)))] 2666 "" 2667 " 2668{ 2669 if (dsp16xx_compare_gen == gen_compare_reg) 2670 operands[1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2671 else 2672 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2673}") 2674 2675 2676(define_expand "bleu" 2677 [(set (pc) 2678 (if_then_else (leu (match_dup 1) 2679 (const_int 0)) 2680 (label_ref (match_operand 0 "" "")) 2681 (pc)))] 2682 "" 2683 " 2684{ 2685 if (dsp16xx_compare_gen == gen_compare_reg) 2686 operands[1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 2687 else 2688 operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 2689}") 2690 2691 2692(define_insn "" 2693 [(set (pc) 2694 (if_then_else (match_operator 1 "comparison_operator" 2695 [(cc0) (const_int 0)]) 2696 (label_ref (match_operand 0 "" "")) 2697 (pc)))] 2698 "!TARGET_NEAR_JUMP" 2699 "pt=%l0\;if %C1 goto pt" 2700 [(set_attr "type" "cond_jump")]) 2701 2702(define_insn "" 2703 [(set (pc) 2704 (if_then_else (match_operator 1 "comparison_operator" 2705 [(cc0) (const_int 0)]) 2706 (label_ref (match_operand 0 "" "")) 2707 (pc)))] 2708 "TARGET_NEAR_JUMP" 2709 "if %C1 goto %l0" 2710 [(set_attr "type" "cond_jump")]) 2711 2712;; 2713;; Negated conditional jump instructions. 2714;; These are necessary because jump optimization can turn 2715;; direct-conditional branches into reverse-conditional 2716;; branches. 2717 2718(define_insn "" 2719 [(set (pc) 2720 (if_then_else (match_operator 1 "comparison_operator" 2721 [(cc0) (const_int 0)]) 2722 (pc) 2723 (label_ref (match_operand 0 "" ""))))] 2724 "!TARGET_NEAR_JUMP" 2725 "pt=%l0\;if %I1 goto pt" 2726 [(set_attr "type" "cond_jump")]) 2727 2728(define_insn "" 2729 [(set (pc) 2730 (if_then_else (match_operator 1 "comparison_operator" 2731 [(cc0) (const_int 0)]) 2732 (pc) 2733 (label_ref (match_operand 0 "" ""))))] 2734 "TARGET_NEAR_JUMP" 2735 "if %I1 goto %l0" 2736 [(set_attr "type" "cond_jump")]) 2737 2738 2739;; 2740;; JUMPS 2741;; 2742 2743(define_insn "jump" 2744 [(set (pc) 2745 (label_ref (match_operand 0 "" "")))] 2746 "" 2747 "* 2748 { 2749 if (TARGET_NEAR_JUMP) 2750 return \"goto %l0\"; 2751 else 2752 return \"pt=%l0\;goto pt\"; 2753 }" 2754 [(set_attr "type" "jump")]) 2755 2756 2757(define_insn "indirect_jump" 2758 [(set (pc) (match_operand:QI 0 "register_operand" "A"))] 2759 "" 2760 "pt=%0\;goto pt" 2761 [(set_attr "type" "jump")]) 2762 2763(define_insn "tablejump" 2764 [(set (pc) (match_operand:QI 0 "register_operand" "A")) 2765 (use (label_ref (match_operand 1 "" "")))] 2766 "" 2767 "pt=%0\;goto pt" 2768 [(set_attr "type" "jump")]) 2769 2770;; 2771;; FUNCTION CALLS 2772;; 2773 2774;; Call subroutine with no return value. 2775 2776 2777(define_expand "call" 2778 [(parallel [(call (match_operand:QI 0 "" "") 2779 (match_operand 1 "" "")) 2780 (clobber (reg:QI 24))])] 2781 "" 2782 " 2783{ 2784 if (GET_CODE (operands[0]) == MEM 2785 && ! call_address_operand (XEXP (operands[0], 0), QImode)) 2786 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]), 2787 force_reg (Pmode, XEXP (operands[0], 0))); 2788}") 2789 2790(define_insn "" 2791 [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" "hR")) 2792 (match_operand 1 "" "")) 2793 (clobber (reg:QI 24))])] 2794 "" 2795 "* 2796{ 2797 if (GET_CODE (operands[0]) == REG || 2798 (GET_CODE(operands[0]) == SYMBOL_REF && !TARGET_NEAR_CALL)) 2799 return \"pt=%0\;call pt\"; 2800 else 2801 return \"call %0\"; 2802}" 2803[(set_attr "type" "call")]) 2804 2805;; Call subroutine with return value. 2806 2807(define_expand "call_value" 2808 [(parallel [(set (match_operand 0 "register_operand" "=f") 2809 (call (match_operand:QI 1 "call_address_operand" "hR") 2810 (match_operand:QI 2 "" ""))) 2811 (clobber (reg:QI 24))])] 2812 "" 2813 " 2814{ 2815 if (GET_CODE (operands[1]) == MEM 2816 && ! call_address_operand (XEXP (operands[1], 0), QImode)) 2817 operands[1] = gen_rtx_MEM (GET_MODE (operands[1]), 2818 force_reg (Pmode, XEXP (operands[1], 0))); 2819}") 2820 2821(define_insn "" 2822 [(parallel [(set (match_operand 0 "register_operand" "=f") 2823 (call (mem:QI (match_operand:QI 1 "call_address_operand" "hR")) 2824 (match_operand:QI 2 "" ""))) 2825 (clobber (reg:QI 24))])] 2826 "" 2827 "* 2828{ 2829 if (GET_CODE (operands[1]) == REG || 2830 (GET_CODE(operands[1]) == SYMBOL_REF && !TARGET_NEAR_CALL)) 2831 return \"pt=%1\;call pt\"; 2832 else 2833 return \"call %1\"; 2834}" 2835[(set_attr "type" "call")]) 2836 2837 2838(define_expand "untyped_call" 2839 [(parallel [(call (match_operand 0 "" "") 2840 (const_int 0)) 2841 (match_operand 1 "" "") 2842 (match_operand 2 "" "")])] 2843 "" 2844 " 2845{ 2846 int i; 2847 2848 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 2849 2850 for (i = 0; i < XVECLEN (operands[2], 0); i++) 2851 { 2852 rtx set = XVECEXP (operands[2], 0, i); 2853 emit_move_insn (SET_DEST (set), SET_SRC (set)); 2854 } 2855 2856 /* The optimizer does not know that the call sets the function value 2857 registers we stored in the result block. We avoid problems by 2858 claiming that all hard registers are used and clobbered at this 2859 point. */ 2860 emit_insn (gen_blockage ()); 2861 2862 DONE; 2863}") 2864 2865;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2866;; all of memory. This blocks insns from being moved across this point. 2867 2868(define_insn "blockage" 2869 [(unspec_volatile [(const_int 0)] 0)] 2870 "" 2871 "") 2872 2873(define_insn "nop" 2874 [(const_int 0)] 2875 "" 2876 "nop" 2877 [(set_attr "type" "nop")]) 2878 2879;; 2880;; PEEPHOLE PATTERNS 2881;; 2882 2883 2884(define_peephole 2885 [(parallel [(set (cc0) 2886 (compare (match_operand:QI 0 "register_operand" "k,k,!k,u,u,!u") 2887 (match_operand:QI 1 "register_operand" "w,z,u,w,z,k"))) 2888 (use (match_operand:QI 2 "register_operand" "=j,j,j,q,q,q")) 2889 (use (match_operand:QI 3 "register_operand" "=v,y,q,v,y,j"))]) 2890 (set (pc) 2891 (if_then_else (match_operator 5 "uns_comparison_operator" 2892 [(cc0) (const_int 0)]) 2893 (label_ref (match_operand 4 "" "")) 2894 (pc)))] 2895 "!TARGET_NEAR_JUMP" 2896 "pt=%l4\;%2-%3\;if %C5 goto pt") 2897 2898(define_peephole 2899 [(parallel [(set (cc0) 2900 (compare (match_operand:QI 0 "register_operand" "k,k,!k,u,u,!u") 2901 (match_operand:QI 1 "register_operand" "w,z,u,w,z,k"))) 2902 (use (match_operand:QI 2 "register_operand" "=j,j,j,q,q,q")) 2903 (use (match_operand:QI 3 "register_operand" "=v,y,q,v,y,j"))]) 2904 (set (pc) 2905 (if_then_else (match_operator 5 "uns_comparison_operator" 2906 [(cc0) (const_int 0)]) 2907 (pc) 2908 (label_ref (match_operand 4 "" ""))))] 2909 "!TARGET_NEAR_JUMP" 2910 "pt=%l4\;%2-%3\;if %I5 goto pt") 2911 2912 2913(define_peephole 2914 [(parallel [(set (cc0) 2915 (compare (match_operand:QI 0 "register_operand" "k,u") 2916 (match_operand:QI 1 "const_int_operand" "i,i"))) 2917 (use (match_operand:QI 2 "register_operand" "=j,q"))]) 2918 (set (pc) 2919 (if_then_else (match_operator 4 "uns_comparison_operator" 2920 [(cc0) (const_int 0)]) 2921 (label_ref (match_operand 3 "" "")) 2922 (pc)))] 2923 "!TARGET_NEAR_JUMP" 2924 "pt=%l3\;%0-%H1\;if %C4 goto pt") 2925 2926(define_peephole 2927 [(parallel [(set (cc0) 2928 (compare (match_operand:QI 0 "register_operand" "k,u") 2929 (match_operand:QI 1 "const_int_operand" "i,i"))) 2930 (use (match_operand:QI 2 "register_operand" "=j,q"))]) 2931 (set (pc) 2932 (if_then_else (match_operator 4 "uns_comparison_operator" 2933 [(cc0) (const_int 0)]) 2934 (pc) 2935 (label_ref (match_operand 3 "" ""))))] 2936 "!TARGET_NEAR_JUMP" 2937 "pt=%l3\;%0-%H1\;if %I4 goto pt") 2938 2939;; 2940;;; QImode SIGNED COMPARE PEEPHOLE OPTIMIZATIONS 2941;; 2942 2943(define_peephole 2944 [(parallel [(set (cc0) 2945 (compare (match_operand:QI 0 "register_operand" "j,j,h,q,q,q") 2946 (match_operand:QI 1 "register_operand" "v,y,q,v,y,j"))) 2947 (use (match_operand:QI 2 "register_operand" "=k,k,k,u,u,u")) 2948 (use (match_operand:QI 3 "register_operand" "=w,z,u,w,z,k"))]) 2949 (set (pc) 2950 (if_then_else (match_operator 5 "signed_comparison_operator" 2951 [(cc0) (const_int 0)]) 2952 (label_ref (match_operand 4 "" "")) 2953 (pc)))] 2954 "!TARGET_NEAR_JUMP" 2955 "pt=%l4\;%0-%1\;if %C5 goto pt") 2956 2957 2958(define_peephole 2959 [(parallel [(set (cc0) 2960 (compare (match_operand:QI 0 "register_operand" "j,j,j,q,q,q") 2961 (match_operand:QI 1 "register_operand" "v,y,q,v,y,j"))) 2962 (use (match_operand:QI 2 "register_operand" "=k,k,k,u,u,u")) 2963 (use (match_operand:QI 3 "register_operand" "=w,z,u,w,z,k"))]) 2964 (set (pc) 2965 (if_then_else (match_operator 5 "signed_comparison_operator" 2966 [(cc0) (const_int 0)]) 2967 (pc) 2968 (label_ref (match_operand 4 "" ""))))] 2969 "!TARGET_NEAR_JUMP" 2970 "pt=%l4\;%0-%1\;if %I5 goto pt") 2971 2972 2973(define_peephole 2974 [(parallel [(set (cc0) 2975 (compare (match_operand:QI 0 "register_operand" "j,q") 2976 (match_operand:QI 1 "const_int_operand" "i,i"))) 2977 (use (match_operand:QI 2 "register_operand" "=k,u"))]) 2978 (set (pc) 2979 (if_then_else (match_operator 4 "signed_comparison_operator" 2980 [(cc0) (const_int 0)]) 2981 (label_ref (match_operand 3 "" "")) 2982 (pc)))] 2983 "!TARGET_NEAR_JUMP" 2984 "pt=%l3\;%b0-%H1\;if %C4 goto pt") 2985 2986(define_peephole 2987 [(parallel [(set (cc0) 2988 (compare (match_operand:QI 0 "register_operand" "j,q") 2989 (match_operand:QI 1 "const_int_operand" "i,i"))) 2990 (use (match_operand:QI 2 "register_operand" "=k,u"))]) 2991 (set (pc) 2992 (if_then_else (match_operator 4 "signed_comparison_operator" 2993 [(cc0) (const_int 0)]) 2994 (pc) 2995 (label_ref (match_operand 3 "" ""))))] 2996 "!TARGET_NEAR_JUMP" 2997 "pt=%l3\;%b0-%H1\;if %I4 goto pt") 2998 2999;; TST PEEPHOLE PATTERNS 3000 3001(define_peephole 3002 [(parallel [(set (cc0) 3003 (match_operand:QI 0 "register_operand" "j,q")) 3004 (use (match_operand:QI 1 "register_operand" "=k,u"))]) 3005 (set (pc) 3006 (if_then_else (match_operator 3 "signed_comparison_operator" 3007 [(cc0) (const_int 0)]) 3008 (pc) 3009 (label_ref (match_operand 2 "" ""))))] 3010 "!TARGET_NEAR_JUMP" 3011 "pt=%l2\;%b0-0\;if %I3 goto pt") 3012 3013(define_peephole 3014 [(parallel [(set (cc0) 3015 (match_operand:QI 0 "register_operand" "j,q")) 3016 (use (match_operand:QI 1 "register_operand" "=k,u"))]) 3017 (set (pc) 3018 (if_then_else (match_operator 3 "signed_comparison_operator" 3019 [(cc0) (const_int 0)]) 3020 (label_ref (match_operand 2 "" "")) 3021 (pc)))] 3022 "!TARGET_NEAR_JUMP" 3023 "pt=%l2\;%b0-0\;if %C3 goto pt") 3024 3025;; HImode peephole patterns 3026 3027(define_peephole 3028 [(set (cc0) 3029 (compare (match_operand:HI 0 "register_operand" "A,A") 3030 (match_operand:HI 1 "register_operand" "Z,A"))) 3031 (set (pc) 3032 (if_then_else (match_operator 3 "signed_comparison_operator" 3033 [(cc0) (const_int 0)]) 3034 (label_ref (match_operand 2 "" "")) 3035 (pc)))] 3036 "!TARGET_NEAR_JUMP" 3037 "pt=%l2\;%0-%1\;if %C3 goto pt") 3038 3039(define_peephole 3040 [(set (cc0) 3041 (compare (match_operand:HI 0 "register_operand" "A,A") 3042 (match_operand:HI 1 "register_operand" "Z,A"))) 3043 (set (pc) 3044 (if_then_else (match_operator 3 "signed_comparison_operator" 3045 [(cc0) (const_int 0)]) 3046 (pc) 3047 (label_ref (match_operand 2 "" ""))))] 3048 "!TARGET_NEAR_JUMP" 3049 "pt=%l2\;%0-%1\;if %I3 goto pt") 3050