1 /*-
2 * Copyright(c) 2002-2011 Exar Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*$FreeBSD$*/
32
33 #include <dev/vxge/vxgehal/vxgehal.h>
34
35 #define VXGE_HAL_AUX_SEPA ' '
36
37 #define __hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \
38 if (bufsize <= 0) \
39 return (VXGE_HAL_ERR_OUT_OF_SPACE); \
40 retsize = vxge_os_snprintf(retbuf, bufsize, fmt, key, \
41 VXGE_HAL_AUX_SEPA, value); \
42 if (retsize < 0 || retsize >= bufsize) \
43 return (VXGE_HAL_ERR_OUT_OF_SPACE);
44
45 #define __HAL_AUX_ENTRY_DECLARE(size, buf) \
46 int entrysize = 0, leftsize = size; \
47 char *ptr; ptr = buf;
48
49 #define __HAL_AUX_ENTRY(key, value, fmt) \
50 __hal_aux_snprintf(ptr, leftsize, "%s%c"fmt"\n", key, value, entrysize)\
51 ptr += entrysize; leftsize -= entrysize;
52
53 #define __HAL_AUX_CONFIG_ENTRY(key, value, fmt) \
54 if (value == VXGE_HAL_USE_FLASH_DEFAULT) { \
55 __HAL_AUX_ENTRY(key, "FLASH DEFAULT", "%s"); \
56 } else { \
57 __HAL_AUX_ENTRY(key, value, fmt); \
58 }
59
60 #define __HAL_AUX_ENTRY_END(bufsize, retsize) \
61 *retsize = bufsize - leftsize;
62
63 #define __hal_aux_pci_link_info(name, index, var) { \
64 __HAL_AUX_ENTRY(name, \
65 (u64)pcim.link_info[index].var, "%llu") \
66 }
67
68 #define __hal_aux_pci_aggr_info(name, index, var) { \
69 __HAL_AUX_ENTRY(name, \
70 (u64)pcim.aggr_info[index].var, "%llu") \
71 }
72
73 /*
74 * vxge_hal_aux_about_read - Retrieve and format about info.
75 * @devh: HAL device handle.
76 * @bufsize: Buffer size.
77 * @retbuf: Buffer pointer.
78 * @retsize: Size of the result. Cannot be greater than @bufsize.
79 *
80 * Retrieve about info (using vxge_hal_mgmt_about()) and sprintf it
81 * into the provided @retbuf.
82 *
83 * Returns: VXGE_HAL_OK - success.
84 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
85 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
86 * VXGE_HAL_FAIL - Failed to retrieve the information.
87 *
88 * See also: vxge_hal_mgmt_about(), vxge_hal_aux_device_dump().
89 */
90 vxge_hal_status_e
vxge_hal_aux_about_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)91 vxge_hal_aux_about_read(vxge_hal_device_h devh, int bufsize,
92 char *retbuf, int *retsize)
93 {
94 u32 size = sizeof(vxge_hal_mgmt_about_info_t);
95 vxge_hal_status_e status;
96 vxge_hal_mgmt_about_info_t about_info;
97
98 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
99
100 status = vxge_hal_mgmt_about(devh, &about_info, &size);
101 if (status != VXGE_HAL_OK)
102 return (status);
103
104 __HAL_AUX_ENTRY("vendor", about_info.vendor, "0x%x");
105 __HAL_AUX_ENTRY("device", about_info.device, "0x%x");
106 __HAL_AUX_ENTRY("subsys_vendor", about_info.subsys_vendor, "0x%x");
107 __HAL_AUX_ENTRY("subsys_device", about_info.subsys_device, "0x%x");
108 __HAL_AUX_ENTRY("board_rev", about_info.board_rev, "0x%x");
109 __HAL_AUX_ENTRY("vendor_name", about_info.vendor_name, "%s");
110 __HAL_AUX_ENTRY("chip_name", about_info.chip_name, "%s");
111 __HAL_AUX_ENTRY("media", about_info.media, "%s");
112 __HAL_AUX_ENTRY("hal_major", about_info.hal_major, "%s");
113 __HAL_AUX_ENTRY("hal_minor", about_info.hal_minor, "%s");
114 __HAL_AUX_ENTRY("hal_fix", about_info.hal_fix, "%s");
115 __HAL_AUX_ENTRY("hal_build", about_info.hal_build, "%s");
116 __HAL_AUX_ENTRY("ll_major", about_info.ll_major, "%s");
117 __HAL_AUX_ENTRY("ll_minor", about_info.ll_minor, "%s");
118 __HAL_AUX_ENTRY("ll_fix", about_info.ll_fix, "%s");
119 __HAL_AUX_ENTRY("ll_build", about_info.ll_build, "%s");
120
121 __HAL_AUX_ENTRY_END(bufsize, retsize);
122
123 return (VXGE_HAL_OK);
124 }
125
126 /*
127 * vxge_hal_aux_driver_config_read - Read Driver configuration.
128 * @bufsize: Buffer size.
129 * @retbuf: Buffer pointer.
130 * @retsize: Size of the result. Cannot be greater than @bufsize.
131 *
132 * Read driver configuration,
133 *
134 * Returns: VXGE_HAL_OK - success.
135 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
136 *
137 * See also: vxge_hal_aux_device_config_read().
138 */
139 vxge_hal_status_e
vxge_hal_aux_driver_config_read(int bufsize,char * retbuf,int * retsize)140 vxge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize)
141 {
142 u32 size = sizeof(vxge_hal_driver_config_t);
143 vxge_hal_status_e status;
144 vxge_hal_driver_config_t drv_config;
145
146 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
147
148 status = vxge_hal_mgmt_driver_config(&drv_config, &size);
149 if (status != VXGE_HAL_OK)
150 return (status);
151
152 __HAL_AUX_ENTRY("Debug Level",
153 g_vxge_hal_driver->debug_level, "%u");
154 __HAL_AUX_ENTRY_END(bufsize, retsize);
155
156 return (VXGE_HAL_OK);
157 }
158
159 /*
160 * vxge_hal_aux_pci_config_read - Retrieve and format PCI Configuration
161 * info.
162 * @devh: HAL device handle.
163 * @bufsize: Buffer size.
164 * @retbuf: Buffer pointer.
165 * @retsize: Size of the result. Cannot be greater than @bufsize.
166 *
167 * Retrieve about info (using vxge_hal_mgmt_pci_config()) and sprintf it
168 * into the provided @retbuf.
169 *
170 * Returns: VXGE_HAL_OK - success.
171 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
172 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
173 *
174 * See also: vxge_hal_mgmt_pci_config(), vxge_hal_aux_device_dump().
175 */
176 vxge_hal_status_e
vxge_hal_aux_pci_config_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)177 vxge_hal_aux_pci_config_read(
178 vxge_hal_device_h devh,
179 int bufsize,
180 char *retbuf,
181 int *retsize)
182 {
183 u8 cap_id;
184 u16 ext_cap_id;
185 u16 next_ptr;
186 u32 size = sizeof(vxge_hal_pci_config_t);
187 vxge_hal_status_e status;
188 vxge_hal_pci_config_t *pci_config =
189 &((__hal_device_t *) devh)->pci_config_space;
190 vxge_hal_mgmt_pm_cap_t pm_cap;
191 vxge_hal_mgmt_sid_cap_t sid_cap;
192 vxge_hal_mgmt_msi_cap_t msi_cap;
193 vxge_hal_mgmt_msix_cap_t msix_cap;
194 vxge_hal_pci_err_cap_t err_cap;
195
196 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
197
198 status = vxge_hal_mgmt_pci_config(devh, (u8 *) pci_config, &size);
199 if (status != VXGE_HAL_OK)
200 return (status);
201
202 __HAL_AUX_ENTRY("vendor_id", pci_config->vendor_id, "0x%04X");
203 __HAL_AUX_ENTRY("device_id", pci_config->device_id, "0x%04X");
204 __HAL_AUX_ENTRY("command", pci_config->command, "0x%04X");
205 __HAL_AUX_ENTRY("status", pci_config->status, "0x%04X");
206 __HAL_AUX_ENTRY("revision", pci_config->revision, "0x%02X");
207 __HAL_AUX_ENTRY("pciClass1", pci_config->pciClass[0], "0x%02X");
208 __HAL_AUX_ENTRY("pciClass2", pci_config->pciClass[1], "0x%02X");
209 __HAL_AUX_ENTRY("pciClass3", pci_config->pciClass[2], "0x%02X");
210 __HAL_AUX_ENTRY("cache_line_size",
211 pci_config->cache_line_size, "0x%02X");
212 __HAL_AUX_ENTRY("header_type", pci_config->header_type, "0x%02X");
213 __HAL_AUX_ENTRY("bist", pci_config->bist, "0x%02X");
214 __HAL_AUX_ENTRY("base_addr0_lo", pci_config->base_addr0_lo, "0x%08X");
215 __HAL_AUX_ENTRY("base_addr0_hi", pci_config->base_addr0_hi, "0x%08X");
216 __HAL_AUX_ENTRY("base_addr1_lo", pci_config->base_addr1_lo, "0x%08X");
217 __HAL_AUX_ENTRY("base_addr1_hi", pci_config->base_addr1_hi, "0x%08X");
218 __HAL_AUX_ENTRY("not_Implemented1",
219 pci_config->not_Implemented1, "0x%08X");
220 __HAL_AUX_ENTRY("not_Implemented2", pci_config->not_Implemented2,
221 "0x%08X");
222 __HAL_AUX_ENTRY("cardbus_cis_pointer", pci_config->cardbus_cis_pointer,
223 "0x%08X");
224 __HAL_AUX_ENTRY("subsystem_vendor_id", pci_config->subsystem_vendor_id,
225 "0x%04X");
226 __HAL_AUX_ENTRY("subsystem_id", pci_config->subsystem_id, "0x%04X");
227 __HAL_AUX_ENTRY("rom_base", pci_config->rom_base, "0x%08X");
228 __HAL_AUX_ENTRY("capabilities_pointer",
229 pci_config->capabilities_pointer, "0x%02X");
230 __HAL_AUX_ENTRY("interrupt_line", pci_config->interrupt_line, "0x%02X");
231 __HAL_AUX_ENTRY("interrupt_pin", pci_config->interrupt_pin, "0x%02X");
232 __HAL_AUX_ENTRY("min_grant", pci_config->min_grant, "0x%02X");
233 __HAL_AUX_ENTRY("max_latency", pci_config->max_latency, "0x%02X");
234
235 next_ptr = pci_config->capabilities_pointer;
236
237 while (next_ptr != 0) {
238
239 cap_id = VXGE_HAL_PCI_CAP_ID((((u8 *) pci_config) + next_ptr));
240
241 switch (cap_id) {
242
243 case VXGE_HAL_PCI_CAP_ID_PM:
244 status = vxge_hal_mgmt_pm_capabilities_get(devh,
245 &pm_cap);
246 if (status != VXGE_HAL_OK)
247 return (status);
248
249 __HAL_AUX_ENTRY("PM Capability",
250 cap_id, "0x%02X");
251 __HAL_AUX_ENTRY("pm_cap_ver",
252 pm_cap.pm_cap_ver, "%u");
253 __HAL_AUX_ENTRY("pm_cap_pme_clock",
254 pm_cap.pm_cap_pme_clock, "%u");
255 __HAL_AUX_ENTRY("pm_cap_aux_power",
256 pm_cap.pm_cap_aux_power, "%u");
257 __HAL_AUX_ENTRY("pm_cap_dsi",
258 pm_cap.pm_cap_dsi, "%u");
259 __HAL_AUX_ENTRY("pm_cap_aux_current",
260 pm_cap.pm_cap_aux_current, "%u");
261 __HAL_AUX_ENTRY("pm_cap_cap_d0",
262 pm_cap.pm_cap_cap_d0, "%u");
263 __HAL_AUX_ENTRY("pm_cap_cap_d1",
264 pm_cap.pm_cap_cap_d1, "%u");
265 __HAL_AUX_ENTRY("pm_cap_pme_d0",
266 pm_cap.pm_cap_pme_d0, "%u");
267 __HAL_AUX_ENTRY("pm_cap_pme_d1",
268 pm_cap.pm_cap_pme_d1, "%u");
269 __HAL_AUX_ENTRY("pm_cap_pme_d2",
270 pm_cap.pm_cap_pme_d2, "%u");
271 __HAL_AUX_ENTRY("pm_cap_pme_d3_hot",
272 pm_cap.pm_cap_pme_d3_hot, "%u");
273 __HAL_AUX_ENTRY("pm_cap_pme_d3_cold",
274 pm_cap.pm_cap_pme_d3_cold, "%u");
275 __HAL_AUX_ENTRY("pm_ctrl_state",
276 pm_cap.pm_ctrl_state, "%u");
277 __HAL_AUX_ENTRY("pm_ctrl_no_soft_reset",
278 pm_cap.pm_ctrl_no_soft_reset, "%u");
279 __HAL_AUX_ENTRY("pm_ctrl_pme_enable",
280 pm_cap.pm_ctrl_pme_enable, "%u");
281 __HAL_AUX_ENTRY("pm_ctrl_pme_data_sel",
282 pm_cap.pm_ctrl_pme_data_sel, "%u");
283 __HAL_AUX_ENTRY("pm_ctrl_pme_data_scale",
284 pm_cap.pm_ctrl_pme_data_scale, "%u");
285 __HAL_AUX_ENTRY("pm_ctrl_pme_status",
286 pm_cap.pm_ctrl_pme_status, "%u");
287 __HAL_AUX_ENTRY("pm_ppb_ext_b2_b3",
288 pm_cap.pm_ppb_ext_b2_b3, "%u");
289 __HAL_AUX_ENTRY("pm_ppb_ext_ecc_en",
290 pm_cap.pm_ppb_ext_ecc_en, "%u");
291 __HAL_AUX_ENTRY("pm_data_reg",
292 pm_cap.pm_data_reg, "%u");
293 break;
294 case VXGE_HAL_PCI_CAP_ID_VPD:
295 break;
296 case VXGE_HAL_PCI_CAP_ID_SLOTID:
297 status = vxge_hal_mgmt_sid_capabilities_get(devh,
298 &sid_cap);
299 if (status != VXGE_HAL_OK)
300 return (status);
301
302 __HAL_AUX_ENTRY("SID Capability", cap_id, "0x%02X");
303 __HAL_AUX_ENTRY("sid_number_of_slots",
304 sid_cap.sid_number_of_slots, "%u");
305 __HAL_AUX_ENTRY("sid_first_in_chasis",
306 sid_cap.sid_first_in_chasis, "%u");
307 __HAL_AUX_ENTRY("sid_chasis_number",
308 sid_cap.sid_chasis_number, "0x%u");
309 break;
310 case VXGE_HAL_PCI_CAP_ID_MSI:
311 status = vxge_hal_mgmt_msi_capabilities_get(devh,
312 &msi_cap);
313 if (status != VXGE_HAL_OK)
314 return (status);
315
316 __HAL_AUX_ENTRY("MSI Capability", cap_id, "0x%02X");
317 __HAL_AUX_ENTRY("MSI Enable", msi_cap.enable, "%u");
318 __HAL_AUX_ENTRY("MSI 64bit Address Capable",
319 msi_cap.is_64bit_addr_capable, "%u");
320 __HAL_AUX_ENTRY("MSI PVM Capable",
321 msi_cap.is_pvm_capable, "0x%02X");
322 __HAL_AUX_ENTRY("MSI Vectors Allocated",
323 msi_cap.vectors_allocated, "0x%02X");
324 __HAL_AUX_ENTRY("MSI Max Vectors",
325 msi_cap.max_vectors_capable, "0x%02X");
326 if (msi_cap.is_64bit_addr_capable) {
327 __HAL_AUX_ENTRY("MSI address",
328 msi_cap.address, "0x%016llX");
329 } else {
330 __HAL_AUX_ENTRY("MSI address",
331 msi_cap.address, "0x%08llX");
332 }
333 __HAL_AUX_ENTRY("MSI Data", msi_cap.data, "0x%04X");
334 if (msi_cap.is_pvm_capable) {
335 __HAL_AUX_ENTRY("MSI Mask bits",
336 msi_cap.mask_bits, "0x%08X");
337 __HAL_AUX_ENTRY("MSI Pending bits",
338 msi_cap.pending_bits, "0x%08X");
339 }
340 break;
341 case VXGE_HAL_PCI_CAP_ID_VS:
342 break;
343 case VXGE_HAL_PCI_CAP_ID_SHPC:
344 break;
345 case VXGE_HAL_PCI_CAP_ID_PCIE:
346 break;
347 case VXGE_HAL_PCI_CAP_ID_MSIX:
348 status = vxge_hal_mgmt_msix_capabilities_get(devh,
349 &msix_cap);
350 if (status != VXGE_HAL_OK)
351 return (status);
352
353 __HAL_AUX_ENTRY("MSIX Capability", cap_id, "0x%02X");
354 __HAL_AUX_ENTRY("MSIX Enable", msix_cap.enable, "%u");
355 __HAL_AUX_ENTRY("MSIX Mask All vectors",
356 msix_cap.mask_all_vect, "%u");
357 __HAL_AUX_ENTRY("MSIX Table Size",
358 msix_cap.table_size, "%u");
359 __HAL_AUX_ENTRY("MSIX Table Offset",
360 msix_cap.table_offset, "%u");
361 __HAL_AUX_ENTRY("MSIX Table BIR",
362 msix_cap.table_bir, "%u");
363 __HAL_AUX_ENTRY("MSIX PBA Offset",
364 msix_cap.pba_offset, "%u");
365 __HAL_AUX_ENTRY("MSIX PBA BIR", msix_cap.pba_bir, "%u");
366 break;
367 case VXGE_HAL_PCI_CAP_ID_AGP:
368 case VXGE_HAL_PCI_CAP_ID_CHSWP:
369 case VXGE_HAL_PCI_CAP_ID_PCIX:
370 case VXGE_HAL_PCI_CAP_ID_HT:
371 case VXGE_HAL_PCI_CAP_ID_DBGPORT:
372 case VXGE_HAL_PCI_CAP_ID_CPCICSR:
373 case VXGE_HAL_PCI_CAP_ID_PCIBSVID:
374 case VXGE_HAL_PCI_CAP_ID_AGP8X:
375 case VXGE_HAL_PCI_CAP_ID_SECDEV:
376 __HAL_AUX_ENTRY("Unexpected Capability",
377 cap_id, "0x%02X");
378 break;
379 default:
380 __HAL_AUX_ENTRY("Unknown Capability",
381 cap_id, "0x%02X");
382 break;
383 }
384
385 next_ptr =
386 VXGE_HAL_PCI_CAP_NEXT((((u8 *) pci_config) + next_ptr));
387
388 }
389
390 /* CONSTCOND */
391 if (VXGE_HAL_PCI_CONFIG_SPACE_SIZE > 0x100) {
392
393 next_ptr = 0x100;
394
395 while (next_ptr != 0) {
396
397 ext_cap_id = (u16) VXGE_HAL_PCI_EXT_CAP_ID(
398 *(u32 *)((void *)(((u8 *) pci_config) + next_ptr)));
399
400 switch (ext_cap_id) {
401
402 case VXGE_HAL_PCI_EXT_CAP_ID_ERR:
403 status =
404 vxge_hal_mgmt_pci_err_capabilities_get(devh,
405 &err_cap);
406 if (status != VXGE_HAL_OK)
407 return (status);
408
409 __HAL_AUX_ENTRY("pci_err_header",
410 err_cap.pci_err_header, "0x%08X");
411 __HAL_AUX_ENTRY("pci_err_uncor_status",
412 err_cap.pci_err_uncor_status, "0x%08X");
413 __HAL_AUX_ENTRY("pci_err_uncor_mask",
414 err_cap.pci_err_uncor_mask, "0x%08X");
415 __HAL_AUX_ENTRY("pci_err_uncor_server",
416 err_cap.pci_err_uncor_server, "0x%08X");
417 __HAL_AUX_ENTRY("pci_err_cor_status",
418 err_cap.pci_err_cor_status, "0x%08X");
419 __HAL_AUX_ENTRY("pci_err_cap",
420 err_cap.pci_err_cap, "0x%08X");
421 __HAL_AUX_ENTRY("err_header_log",
422 err_cap.err_header_log, "%u");
423 __HAL_AUX_ENTRY("pci_err_root_command",
424 err_cap.pci_err_root_command, "0x%08X");
425 __HAL_AUX_ENTRY("pci_err_root_status",
426 err_cap.pci_err_root_status, "0x%08X");
427 __HAL_AUX_ENTRY("pci_err_root_cor_src",
428 err_cap.pci_err_root_cor_src, "0x%04X");
429 __HAL_AUX_ENTRY("pci_err_root_src",
430 err_cap.pci_err_root_src, "0x%04X");
431 break;
432 case VXGE_HAL_PCI_EXT_CAP_ID_VC:
433 break;
434 case VXGE_HAL_PCI_EXT_CAP_ID_DSN:
435 break;
436 case VXGE_HAL_PCI_EXT_CAP_ID_PWR:
437 break;
438 default:
439 __HAL_AUX_ENTRY("Unknown Capability", cap_id,
440 "0x%02X");
441 break;
442 }
443 next_ptr = (u16) VXGE_HAL_PCI_EXT_CAP_NEXT(
444 *(u32 *)((void *)(((u8 *) pci_config) + next_ptr)));
445
446 }
447
448 }
449
450 __HAL_AUX_ENTRY_END(bufsize, retsize);
451
452 return (VXGE_HAL_OK);
453 }
454
455 /*
456 * vxge_hal_aux_device_config_read - Read device configuration.
457 * @devh: HAL device handle.
458 * @bufsize: Buffer size.
459 * @retbuf: Buffer pointer.
460 * @retsize: Size of the result. Cannot be greater than @bufsize.
461 *
462 * Read device configuration,
463 *
464 * Returns: VXGE_HAL_OK - success.
465 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
466 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
467 *
468 * See also: vxge_hal_aux_driver_config_read().
469 */
470 vxge_hal_status_e
vxge_hal_aux_device_config_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)471 vxge_hal_aux_device_config_read(vxge_hal_device_h devh,
472 int bufsize, char *retbuf, int *retsize)
473 {
474 int i;
475 u32 size = sizeof(vxge_hal_device_config_t);
476 vxge_hal_status_e status;
477 vxge_hal_mac_config_t *mac_config;
478 vxge_hal_device_config_t *dev_config;
479 vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
480
481 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
482
483 dev_config = (vxge_hal_device_config_t *) vxge_os_malloc(hldev->pdev,
484 sizeof(vxge_hal_device_config_t));
485 if (dev_config == NULL) {
486 return (VXGE_HAL_FAIL);
487 }
488
489 status = vxge_hal_mgmt_device_config(devh, dev_config, &size);
490 if (status != VXGE_HAL_OK) {
491 vxge_os_free(hldev->pdev, dev_config,
492 sizeof(vxge_hal_device_config_t));
493 return (status);
494 }
495
496 __HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Minimum",
497 dev_config->dma_blockpool_min, "%u");
498 __HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Initial",
499 dev_config->dma_blockpool_initial, "%u");
500 __HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Increment",
501 dev_config->dma_blockpool_incr, "%u");
502 __HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Maximum",
503 dev_config->dma_blockpool_max, "%u");
504 for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
505 mac_config = &dev_config->mrpcim_config.mac_config;
506 __HAL_AUX_CONFIG_ENTRY("port_id",
507 mac_config->wire_port_config[i].port_id, "%u");
508 __HAL_AUX_CONFIG_ENTRY("media",
509 mac_config->wire_port_config[i].media, "%u");
510 __HAL_AUX_CONFIG_ENTRY("mtu",
511 mac_config->wire_port_config[i].mtu, "%u");
512 __HAL_AUX_CONFIG_ENTRY("autoneg_mode",
513 mac_config->wire_port_config[i].autoneg_mode, "%u");
514 __HAL_AUX_CONFIG_ENTRY("fixed_use_fsm",
515 mac_config->wire_port_config[i].fixed_use_fsm, "%u");
516 __HAL_AUX_CONFIG_ENTRY("antp_use_fsm",
517 mac_config->wire_port_config[i].antp_use_fsm, "%u");
518 __HAL_AUX_CONFIG_ENTRY("anbe_use_fsm",
519 mac_config->wire_port_config[i].anbe_use_fsm, "%u");
520 __HAL_AUX_CONFIG_ENTRY("link_stability_period",
521 mac_config->wire_port_config[i].link_stability_period,
522 "%u");
523 __HAL_AUX_CONFIG_ENTRY("port_stability_period",
524 mac_config->wire_port_config[i].port_stability_period,
525 "%u");
526 __HAL_AUX_CONFIG_ENTRY("tmac_en",
527 mac_config->wire_port_config[i].tmac_en, "%u");
528 __HAL_AUX_CONFIG_ENTRY("rmac_en",
529 mac_config->wire_port_config[i].rmac_en, "%u");
530 __HAL_AUX_CONFIG_ENTRY("tmac_pad",
531 mac_config->wire_port_config[i].tmac_pad, "%u");
532 __HAL_AUX_CONFIG_ENTRY("tmac_pad_byte",
533 mac_config->wire_port_config[i].tmac_pad_byte, "%u");
534 __HAL_AUX_CONFIG_ENTRY("tmac_util_period",
535 mac_config->wire_port_config[i].tmac_util_period, "%u");
536 __HAL_AUX_CONFIG_ENTRY("rmac_strip_fcs",
537 mac_config->wire_port_config[i].rmac_strip_fcs, "%u");
538 __HAL_AUX_CONFIG_ENTRY("rmac_prom_en",
539 mac_config->wire_port_config[i].rmac_prom_en, "%u");
540 __HAL_AUX_CONFIG_ENTRY("rmac_discard_pfrm",
541 mac_config->wire_port_config[i].rmac_discard_pfrm, "%u");
542 __HAL_AUX_CONFIG_ENTRY("rmac_util_period",
543 mac_config->wire_port_config[i].rmac_util_period, "%u");
544 __HAL_AUX_CONFIG_ENTRY("rmac_pause_gen_en",
545 mac_config->wire_port_config[i].rmac_pause_gen_en, "%u");
546 __HAL_AUX_CONFIG_ENTRY("rmac_pause_rcv_en",
547 mac_config->wire_port_config[i].rmac_pause_rcv_en, "%u");
548 __HAL_AUX_CONFIG_ENTRY("rmac_pause_time",
549 mac_config->wire_port_config[i].rmac_pause_time, "%u");
550 __HAL_AUX_CONFIG_ENTRY("limiter_en",
551 mac_config->wire_port_config[i].limiter_en, "%u");
552 __HAL_AUX_CONFIG_ENTRY("max_limit",
553 mac_config->wire_port_config[i].max_limit, "%u");
554 }
555
556 /* CONSTCOND */
557 __HAL_AUX_CONFIG_ENTRY("port_id",
558 VXGE_HAL_MAC_SWITCH_PORT, "%u");
559 __HAL_AUX_CONFIG_ENTRY("mtu",
560 mac_config->switch_port_config.mtu, "%u");
561 __HAL_AUX_CONFIG_ENTRY("tmac_en",
562 mac_config->switch_port_config.tmac_en, "%u");
563 __HAL_AUX_CONFIG_ENTRY("rmac_en",
564 mac_config->switch_port_config.rmac_en, "%u");
565 __HAL_AUX_CONFIG_ENTRY("tmac_pad",
566 mac_config->switch_port_config.tmac_pad, "%u");
567 __HAL_AUX_CONFIG_ENTRY("tmac_pad_byte",
568 mac_config->switch_port_config.tmac_pad_byte, "%u");
569 __HAL_AUX_CONFIG_ENTRY("tmac_util_period",
570 mac_config->switch_port_config.tmac_util_period, "%u");
571 __HAL_AUX_CONFIG_ENTRY("rmac_strip_fcs",
572 mac_config->switch_port_config.rmac_strip_fcs, "%u");
573 __HAL_AUX_CONFIG_ENTRY("rmac_prom_en",
574 mac_config->switch_port_config.rmac_prom_en, "%u");
575 __HAL_AUX_CONFIG_ENTRY("rmac_discard_pfrm",
576 mac_config->switch_port_config.rmac_discard_pfrm, "%u");
577 __HAL_AUX_CONFIG_ENTRY("rmac_util_period",
578 mac_config->switch_port_config.rmac_util_period, "%u");
579 __HAL_AUX_CONFIG_ENTRY("rmac_pause_gen_en",
580 mac_config->switch_port_config.rmac_pause_gen_en, "%u");
581 __HAL_AUX_CONFIG_ENTRY("rmac_pause_rcv_en",
582 mac_config->switch_port_config.rmac_pause_rcv_en, "%u");
583 __HAL_AUX_CONFIG_ENTRY("rmac_pause_time",
584 mac_config->switch_port_config.rmac_pause_time, "%u");
585 __HAL_AUX_CONFIG_ENTRY("limiter_en",
586 mac_config->switch_port_config.limiter_en, "%u");
587 __HAL_AUX_CONFIG_ENTRY("max_limit",
588 mac_config->switch_port_config.max_limit, "%u");
589
590 __HAL_AUX_CONFIG_ENTRY("network_stability_period",
591 mac_config->network_stability_period, "%u");
592 for (i = 0; i < 16; i++) {
593 __HAL_AUX_CONFIG_ENTRY("mc_pause_threshold[i]",
594 mac_config->mc_pause_threshold[i], "%u");
595 }
596 __HAL_AUX_CONFIG_ENTRY("tmac_perma_stop_en",
597 mac_config->tmac_perma_stop_en, "%u");
598 __HAL_AUX_CONFIG_ENTRY("tmac_tx_switch_dis",
599 mac_config->tmac_tx_switch_dis, "%u");
600 __HAL_AUX_CONFIG_ENTRY("tmac_lossy_switch_en",
601 mac_config->tmac_lossy_switch_en, "%u");
602 __HAL_AUX_CONFIG_ENTRY("tmac_lossy_wire_en",
603 mac_config->tmac_lossy_wire_en, "%u");
604 __HAL_AUX_CONFIG_ENTRY("tmac_bcast_to_wire_dis",
605 mac_config->tmac_bcast_to_wire_dis, "%u");
606 __HAL_AUX_CONFIG_ENTRY("tmac_bcast_to_switch_dis",
607 mac_config->tmac_bcast_to_switch_dis, "%u");
608 __HAL_AUX_CONFIG_ENTRY("tmac_host_append_fcs_en",
609 mac_config->tmac_host_append_fcs_en, "%u");
610 __HAL_AUX_CONFIG_ENTRY("tpa_support_snap_ab_n",
611 mac_config->tpa_support_snap_ab_n, "%u");
612 __HAL_AUX_CONFIG_ENTRY("tpa_ecc_enable_n",
613 mac_config->tpa_ecc_enable_n, "%u");
614 __HAL_AUX_CONFIG_ENTRY("rpa_ignore_frame_err",
615 mac_config->rpa_ignore_frame_err, "%u");
616 __HAL_AUX_CONFIG_ENTRY("rpa_support_snap_ab_n",
617 mac_config->rpa_support_snap_ab_n, "%u");
618 __HAL_AUX_CONFIG_ENTRY("rpa_search_for_hao",
619 mac_config->rpa_search_for_hao, "%u");
620 __HAL_AUX_CONFIG_ENTRY("rpa_support_ipv6_mobile_hdrs",
621 mac_config->rpa_support_ipv6_mobile_hdrs, "%u");
622 __HAL_AUX_CONFIG_ENTRY("rpa_ipv6_stop_searching",
623 mac_config->rpa_ipv6_stop_searching, "%u");
624 __HAL_AUX_CONFIG_ENTRY("rpa_no_ps_if_unknown",
625 mac_config->rpa_no_ps_if_unknown, "%u");
626 __HAL_AUX_CONFIG_ENTRY("rpa_search_for_etype",
627 mac_config->rpa_search_for_etype, "%u");
628 __HAL_AUX_CONFIG_ENTRY("rpa_repl_l4_comp_csum",
629 mac_config->rpa_repl_l4_comp_csum, "%u");
630 __HAL_AUX_CONFIG_ENTRY("rpa_repl_l3_incl_cf",
631 mac_config->rpa_repl_l3_incl_cf, "%u");
632 __HAL_AUX_CONFIG_ENTRY("rpa_repl_l3_comp_csum",
633 mac_config->rpa_repl_l3_comp_csum, "%u");
634 __HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv4_tcp_incl_ph",
635 mac_config->rpa_repl_ipv4_tcp_incl_ph, "%u");
636 __HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv6_tcp_incl_ph",
637 mac_config->rpa_repl_ipv6_tcp_incl_ph, "%u");
638 __HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv4_udp_incl_ph",
639 mac_config->rpa_repl_ipv4_udp_incl_ph, "%u");
640 __HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv6_udp_incl_ph",
641 mac_config->rpa_repl_ipv6_udp_incl_ph, "%u");
642 __HAL_AUX_CONFIG_ENTRY("rpa_repl_l4_incl_cf",
643 mac_config->rpa_repl_l4_incl_cf, "%u");
644 __HAL_AUX_CONFIG_ENTRY("rpa_repl_strip_vlan_tag",
645 mac_config->rpa_repl_strip_vlan_tag, "%u");
646 __HAL_AUX_CONFIG_ENTRY("ISR Polling count",
647 dev_config->isr_polling_cnt, "%u");
648 __HAL_AUX_CONFIG_ENTRY("Maximum Payload Size",
649 dev_config->max_payload_size, "%u");
650 __HAL_AUX_CONFIG_ENTRY("MMRB Count",
651 dev_config->mmrb_count, "%u");
652 __HAL_AUX_CONFIG_ENTRY("Statistics Refresh Time",
653 dev_config->stats_refresh_time_sec, "%u");
654 __HAL_AUX_CONFIG_ENTRY("Interrupt Mode",
655 dev_config->intr_mode, "%u");
656 __HAL_AUX_CONFIG_ENTRY("Dump on Unknwon Error",
657 dev_config->dump_on_unknown, "%u");
658 __HAL_AUX_CONFIG_ENTRY("Dump on Serious Error",
659 dev_config->dump_on_serr, "%u");
660 __HAL_AUX_CONFIG_ENTRY("Dump on Critical Error",
661 dev_config->dump_on_critical, "%u");
662 __HAL_AUX_CONFIG_ENTRY("Dump on ECC Error",
663 dev_config->dump_on_eccerr, "%u");
664 __HAL_AUX_CONFIG_ENTRY("RTH Enable",
665 dev_config->rth_en, "%u");
666 __HAL_AUX_CONFIG_ENTRY("RTS MAC Enable",
667 dev_config->rts_mac_en, "%u");
668 __HAL_AUX_CONFIG_ENTRY("RTS QOS Enable",
669 dev_config->rts_qos_en, "%u");
670 __HAL_AUX_CONFIG_ENTRY("RTS Port Enable",
671 dev_config->rts_port_en, "%u");
672 __HAL_AUX_CONFIG_ENTRY("Max CQE Groups",
673 dev_config->max_cqe_groups, "%u");
674 __HAL_AUX_CONFIG_ENTRY("Max Number of OD Groups",
675 dev_config->max_num_wqe_od_groups, "%u");
676 __HAL_AUX_CONFIG_ENTRY("No WQE Threshold",
677 dev_config->no_wqe_threshold, "%u");
678 __HAL_AUX_CONFIG_ENTRY("Refill Threshold-High",
679 dev_config->refill_threshold_high, "%u");
680 __HAL_AUX_CONFIG_ENTRY("Refill Threshold-Low",
681 dev_config->refill_threshold_low, "%u");
682 __HAL_AUX_CONFIG_ENTRY("Ack Block Limit",
683 dev_config->ack_blk_limit, "%u");
684 __HAL_AUX_CONFIG_ENTRY("Poll or Doorbell",
685 dev_config->poll_or_doorbell, "%u");
686 __HAL_AUX_CONFIG_ENTRY("stats_read_method",
687 dev_config->stats_read_method, "%u");
688 __HAL_AUX_CONFIG_ENTRY("Device Poll Timeout",
689 dev_config->device_poll_millis, "%u");
690 __HAL_AUX_CONFIG_ENTRY("debug_level",
691 dev_config->debug_level, "%u");
692 __HAL_AUX_CONFIG_ENTRY("debug_mask",
693 dev_config->debug_mask, "%u");
694
695 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
696 __HAL_AUX_CONFIG_ENTRY("Trace buffer size",
697 dev_config->tracebuf_size, "%u");
698 #endif
699
700 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
701 if (!(((__hal_device_t *) hldev)->vpath_assignments & mBIT(i)))
702 continue;
703
704 __HAL_AUX_CONFIG_ENTRY("Virtual Path id",
705 dev_config->vp_config[i].vp_id, "%u");
706 __HAL_AUX_CONFIG_ENTRY("No Snoop",
707 dev_config->vp_config[i].no_snoop, "%u");
708 __HAL_AUX_CONFIG_ENTRY("mtu",
709 dev_config->vp_config[i].mtu, "%u");
710 __HAL_AUX_CONFIG_ENTRY("TPA LSOv2 Enable",
711 dev_config->vp_config[i].tpa_lsov2_en, "%u");
712 __HAL_AUX_CONFIG_ENTRY("TPA Ignore Frame Error",
713 dev_config->vp_config[i].tpa_ignore_frame_error, "%u");
714 __HAL_AUX_CONFIG_ENTRY("TPA IPv6 Keep Searching",
715 dev_config->vp_config[i].tpa_ipv6_keep_searching, "%u");
716 __HAL_AUX_CONFIG_ENTRY("TPA L4 pseudo header present",
717 dev_config->vp_config[i].tpa_l4_pshdr_present, "%u");
718 __HAL_AUX_CONFIG_ENTRY("TPA support mobile IPv6 Headers",
719 dev_config->vp_config[i].tpa_support_mobile_ipv6_hdrs,
720 "%u");
721 __HAL_AUX_CONFIG_ENTRY("RPA IPv4 TCP Include pseudo header",
722 dev_config->vp_config[i].rpa_ipv4_tcp_incl_ph, "%u");
723 __HAL_AUX_CONFIG_ENTRY("RPA IPv6 TCP Include pseudo header",
724 dev_config->vp_config[i].rpa_ipv6_tcp_incl_ph, "%u");
725 __HAL_AUX_CONFIG_ENTRY("RPA IPv4 UDP Include pseudo header",
726 dev_config->vp_config[i].rpa_ipv4_udp_incl_ph, "%u");
727 __HAL_AUX_CONFIG_ENTRY("RPA IPv6 UDP Include pseudo header",
728 dev_config->vp_config[i].rpa_ipv6_udp_incl_ph, "%u");
729 __HAL_AUX_CONFIG_ENTRY("RPA L4 Include CF",
730 dev_config->vp_config[i].rpa_l4_incl_cf, "%u");
731 __HAL_AUX_CONFIG_ENTRY("RPA Strip VLAN Tag",
732 dev_config->vp_config[i].rpa_strip_vlan_tag, "%u");
733 __HAL_AUX_CONFIG_ENTRY("RPA L4 Comp Csum Enable",
734 dev_config->vp_config[i].rpa_l4_comp_csum, "%u");
735 __HAL_AUX_CONFIG_ENTRY("RPA L3 Include CF Enable",
736 dev_config->vp_config[i].rpa_l3_incl_cf, "%u");
737 __HAL_AUX_CONFIG_ENTRY("RPA L3 Comp Csum",
738 dev_config->vp_config[i].rpa_l3_comp_csum, "%u");
739 __HAL_AUX_CONFIG_ENTRY("RPA Unicast All Address Enable",
740 dev_config->vp_config[i].rpa_ucast_all_addr_en, "%u");
741 __HAL_AUX_CONFIG_ENTRY("RPA Unicast All Address Enable",
742 dev_config->vp_config[i].rpa_ucast_all_addr_en, "%u");
743 __HAL_AUX_CONFIG_ENTRY("RPA Multicast All Address Enable",
744 dev_config->vp_config[i].rpa_mcast_all_addr_en, "%u");
745 __HAL_AUX_CONFIG_ENTRY("RPA Broadcast Enable",
746 dev_config->vp_config[i].rpa_bcast_en, "%u");
747 __HAL_AUX_CONFIG_ENTRY("RPA All VID Enable",
748 dev_config->vp_config[i].rpa_all_vid_en, "%u");
749 __HAL_AUX_CONFIG_ENTRY("VP Queue L2 Flow",
750 dev_config->vp_config[i].vp_queue_l2_flow, "%u");
751
752 __HAL_AUX_CONFIG_ENTRY("Ring blocks",
753 dev_config->vp_config[i].ring.ring_length, "%u");
754 __HAL_AUX_CONFIG_ENTRY("Buffer Mode",
755 dev_config->vp_config[i].ring.buffer_mode, "%u");
756 __HAL_AUX_CONFIG_ENTRY("Scatter Mode",
757 dev_config->vp_config[i].ring.scatter_mode, "%u");
758 __HAL_AUX_CONFIG_ENTRY("Post Mode",
759 dev_config->vp_config[i].ring.post_mode, "%u");
760 __HAL_AUX_CONFIG_ENTRY("Maximum Frame Length",
761 dev_config->vp_config[i].ring.max_frm_len, "%u");
762 __HAL_AUX_CONFIG_ENTRY("No Snoop Bits",
763 dev_config->vp_config[i].ring.no_snoop_bits, "%u");
764 __HAL_AUX_CONFIG_ENTRY("Rx Timer Value",
765 dev_config->vp_config[i].ring.rx_timer_val, "%u");
766 __HAL_AUX_CONFIG_ENTRY("Greedy return",
767 dev_config->vp_config[i].ring.greedy_return, "%u");
768 __HAL_AUX_CONFIG_ENTRY("Rx Timer CI",
769 dev_config->vp_config[i].ring.rx_timer_ci, "%u");
770 __HAL_AUX_CONFIG_ENTRY("Backoff Interval",
771 dev_config->vp_config[i].ring.backoff_interval_us, "%u");
772 __HAL_AUX_CONFIG_ENTRY("Indicate Max Packets",
773 dev_config->vp_config[i].ring.indicate_max_pkts, "%u");
774
775
776 __HAL_AUX_CONFIG_ENTRY("FIFO Blocks",
777 dev_config->vp_config[i].fifo.fifo_length, "%u");
778 __HAL_AUX_CONFIG_ENTRY("Max Frags",
779 dev_config->vp_config[i].fifo.max_frags, "%u");
780 __HAL_AUX_CONFIG_ENTRY("Alignment Size",
781 dev_config->vp_config[i].fifo.alignment_size, "%u");
782 __HAL_AUX_CONFIG_ENTRY("Maximum Aligned Frags",
783 dev_config->vp_config[i].fifo.max_aligned_frags, "%u");
784 __HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
785 dev_config->vp_config[i].fifo.intr, "%u");
786 __HAL_AUX_CONFIG_ENTRY("No Snoop Bits",
787 dev_config->vp_config[i].fifo.no_snoop_bits, "%u");
788
789
790 __HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
791 dev_config->vp_config[i].tti.intr_enable, "%u");
792 __HAL_AUX_CONFIG_ENTRY("BTimer Value",
793 dev_config->vp_config[i].tti.btimer_val, "%u");
794 __HAL_AUX_CONFIG_ENTRY("Timer AC Enable",
795 dev_config->vp_config[i].tti.timer_ac_en, "%u");
796 __HAL_AUX_CONFIG_ENTRY("Timer CI Enable",
797 dev_config->vp_config[i].tti.timer_ci_en, "%u");
798 __HAL_AUX_CONFIG_ENTRY("Timer RI Enable",
799 dev_config->vp_config[i].tti.timer_ri_en, "%u");
800 __HAL_AUX_CONFIG_ENTRY("Timer Event SF",
801 dev_config->vp_config[i].tti.rtimer_event_sf, "%u");
802 __HAL_AUX_CONFIG_ENTRY("RTimer Value",
803 dev_config->vp_config[i].tti.rtimer_val, "%u");
804 __HAL_AUX_CONFIG_ENTRY("Util Sel",
805 dev_config->vp_config[i].tti.util_sel, "%u");
806 __HAL_AUX_CONFIG_ENTRY("LTimer Value",
807 dev_config->vp_config[i].tti.ltimer_val, "%u");
808 __HAL_AUX_CONFIG_ENTRY("Tx Frame Count Enable",
809 dev_config->vp_config[i].tti.txfrm_cnt_en, "%u");
810 __HAL_AUX_CONFIG_ENTRY("Txd Count Enable",
811 dev_config->vp_config[i].tti.txd_cnt_en, "%u");
812 __HAL_AUX_CONFIG_ENTRY("Util Range A",
813 dev_config->vp_config[i].tti.urange_a, "%u");
814 __HAL_AUX_CONFIG_ENTRY("Util Event Count A",
815 dev_config->vp_config[i].tti.uec_a, "%u");
816 __HAL_AUX_CONFIG_ENTRY("Util Range B",
817 dev_config->vp_config[i].tti.urange_b, "%u");
818 __HAL_AUX_CONFIG_ENTRY("Util Event Count B",
819 dev_config->vp_config[i].tti.uec_b, "%u");
820 __HAL_AUX_CONFIG_ENTRY("Util Range C",
821 dev_config->vp_config[i].tti.urange_c, "%u");
822 __HAL_AUX_CONFIG_ENTRY("Util Event Count C",
823 dev_config->vp_config[i].tti.uec_c, "%u");
824 __HAL_AUX_CONFIG_ENTRY("Util Event Count D",
825 dev_config->vp_config[i].tti.uec_d, "%u");
826 __HAL_AUX_CONFIG_ENTRY("Ufca Interrupt Threshold",
827 dev_config->vp_config[i].tti.ufca_intr_thres, "%u");
828 __HAL_AUX_CONFIG_ENTRY("Ufca Low Limit",
829 dev_config->vp_config[i].tti.ufca_lo_lim, "%u");
830 __HAL_AUX_CONFIG_ENTRY("Ufca High Limit",
831 dev_config->vp_config[i].tti.ufca_hi_lim, "%u");
832 __HAL_AUX_CONFIG_ENTRY("Ufca lbolt period",
833 dev_config->vp_config[i].tti.ufca_lbolt_period, "%u");
834
835 __HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
836 dev_config->vp_config[i].rti.intr_enable, "%u");
837 __HAL_AUX_CONFIG_ENTRY("BTimer Value",
838 dev_config->vp_config[i].rti.btimer_val, "%u");
839 __HAL_AUX_CONFIG_ENTRY("Timer AC Enable",
840 dev_config->vp_config[i].rti.timer_ac_en, "%u");
841 __HAL_AUX_CONFIG_ENTRY("Timer CI Enable",
842 dev_config->vp_config[i].rti.timer_ci_en, "%u");
843 __HAL_AUX_CONFIG_ENTRY("Timer RI Enable",
844 dev_config->vp_config[i].rti.timer_ri_en, "%u");
845 __HAL_AUX_CONFIG_ENTRY("Timer Event SF",
846 dev_config->vp_config[i].rti.rtimer_event_sf, "%u");
847 __HAL_AUX_CONFIG_ENTRY("RTimer Value",
848 dev_config->vp_config[i].rti.rtimer_val, "%u");
849 __HAL_AUX_CONFIG_ENTRY("Util Sel",
850 dev_config->vp_config[i].rti.util_sel, "%u");
851 __HAL_AUX_CONFIG_ENTRY("LTimer Value",
852 dev_config->vp_config[i].rti.ltimer_val, "%u");
853 __HAL_AUX_CONFIG_ENTRY("Tx Frame Count Enable",
854 dev_config->vp_config[i].rti.txfrm_cnt_en, "%u");
855 __HAL_AUX_CONFIG_ENTRY("Txd Count Enable",
856 dev_config->vp_config[i].rti.txd_cnt_en, "%u");
857 __HAL_AUX_CONFIG_ENTRY("Util Range A",
858 dev_config->vp_config[i].rti.urange_a, "%u");
859 __HAL_AUX_CONFIG_ENTRY("Util Event Count A",
860 dev_config->vp_config[i].rti.uec_a, "%u");
861 __HAL_AUX_CONFIG_ENTRY("Util Range B",
862 dev_config->vp_config[i].rti.urange_b, "%u");
863 __HAL_AUX_CONFIG_ENTRY("Util Event Count B",
864 dev_config->vp_config[i].rti.uec_b, "%u");
865 __HAL_AUX_CONFIG_ENTRY("Util Range C",
866 dev_config->vp_config[i].rti.urange_c, "%u");
867 __HAL_AUX_CONFIG_ENTRY("Util Event Count C",
868 dev_config->vp_config[i].rti.uec_c, "%u");
869 __HAL_AUX_CONFIG_ENTRY("Util Event Count D",
870 dev_config->vp_config[i].rti.uec_d, "%u");
871 __HAL_AUX_CONFIG_ENTRY("Ufca Interrupt Threshold",
872 dev_config->vp_config[i].rti.ufca_intr_thres, "%u");
873 __HAL_AUX_CONFIG_ENTRY("Ufca Low Limit",
874 dev_config->vp_config[i].rti.ufca_lo_lim, "%u");
875 __HAL_AUX_CONFIG_ENTRY("Ufca High Limit",
876 dev_config->vp_config[i].rti.ufca_hi_lim, "%u");
877 __HAL_AUX_CONFIG_ENTRY("Ufca lbolt period",
878 dev_config->vp_config[i].rti.ufca_lbolt_period, "%u");
879 }
880
881 __HAL_AUX_ENTRY_END(bufsize, retsize);
882
883 vxge_os_free(hldev->pdev, dev_config,
884 sizeof(vxge_hal_device_config_t));
885
886 return (VXGE_HAL_OK);
887 }
888
889 /*
890 * vxge_hal_aux_bar0_read - Read and format X3100 BAR0 register.
891 * @devh: HAL device handle.
892 * @offset: Register offset in the BAR0 space.
893 * @bufsize: Buffer size.
894 * @retbuf: Buffer pointer.
895 * @retsize: Size of the result. Cannot be greater than @bufsize.
896 *
897 * Read X3100 register from BAR0 space.
898 *
899 * Returns: VXGE_HAL_OK - success.
900 * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
901 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
902 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
903 * valid.
904 *
905 * See also: vxge_hal_mgmt_reg_read().
906 */
907 vxge_hal_status_e
vxge_hal_aux_bar0_read(vxge_hal_device_h devh,unsigned int offset,int bufsize,char * retbuf,int * retsize)908 vxge_hal_aux_bar0_read(vxge_hal_device_h devh,
909 unsigned int offset, int bufsize, char *retbuf,
910 int *retsize)
911 {
912 vxge_hal_status_e status;
913 u64 retval;
914
915 status = vxge_hal_mgmt_bar0_read(devh, offset, &retval);
916 if (status != VXGE_HAL_OK)
917 return (status);
918
919 if (bufsize < VXGE_OS_SPRINTF_STRLEN)
920 return (VXGE_HAL_ERR_OUT_OF_SPACE);
921
922 *retsize = vxge_os_snprintf(retbuf, bufsize,
923 "0x%04X%c0x%08X%08X\n", offset,
924 VXGE_HAL_AUX_SEPA, (u32) (retval >> 32), (u32) retval);
925
926 return (VXGE_HAL_OK);
927 }
928
929 /*
930 * vxge_hal_aux_bar1_read - Read and format X3100 BAR1 register.
931 * @devh: HAL device handle.
932 * @offset: Register offset in the BAR1 space.
933 * @bufsize: Buffer size.
934 * @retbuf: Buffer pointer.
935 * @retsize: Size of the result. Cannot be greater than @bufsize.
936 *
937 * Read X3100 register from BAR1 space.
938 * Returns: VXGE_HAL_OK - success.
939 * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
940 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
941 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
942 * valid.
943 *
944 * See also: vxge_hal_mgmt_reg_read().
945 */
946 vxge_hal_status_e
vxge_hal_aux_bar1_read(vxge_hal_device_h devh,unsigned int offset,int bufsize,char * retbuf,int * retsize)947 vxge_hal_aux_bar1_read(vxge_hal_device_h devh,
948 unsigned int offset, int bufsize, char *retbuf,
949 int *retsize)
950 {
951 vxge_hal_status_e status;
952 u64 retval;
953
954 status = vxge_hal_mgmt_bar1_read(devh, offset, &retval);
955 if (status != VXGE_HAL_OK)
956 return (status);
957
958 if (bufsize < VXGE_OS_SPRINTF_STRLEN)
959 return (VXGE_HAL_ERR_OUT_OF_SPACE);
960
961 *retsize = vxge_os_snprintf(retbuf, bufsize, "0x%04X%c0x%08X%08X\n",
962 offset, VXGE_HAL_AUX_SEPA, (u32) (retval >> 32), (u32) retval);
963
964 return (VXGE_HAL_OK);
965 }
966
967 /*
968 * vxge_hal_aux_bar0_write - Write BAR0 register.
969 * @devh: HAL device handle.
970 * @offset: Register offset in the BAR0 space.
971 * @value: Regsister value (to write).
972 *
973 * Write BAR0 register.
974 *
975 * Returns: VXGE_HAL_OK - success.
976 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
977 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
978 * valid.
979 *
980 * See also: vxge_hal_mgmt_reg_write().
981 */
982 vxge_hal_status_e
vxge_hal_aux_bar0_write(vxge_hal_device_h devh,unsigned int offset,u64 value)983 vxge_hal_aux_bar0_write(vxge_hal_device_h devh,
984 unsigned int offset, u64 value)
985 {
986 vxge_hal_status_e status;
987
988 status = vxge_hal_mgmt_bar0_write(devh, offset, value);
989 if (status != VXGE_HAL_OK)
990 return (status);
991
992 return (VXGE_HAL_OK);
993 }
994
995 /*
996 * vxge_hal_aux_stats_vpath_hw_read - Read vpath hardware statistics.
997 * @vpath_handle: HAL Vpath handle.
998 * @bufsize: Buffer size.
999 * @retbuf: Buffer pointer.
1000 * @retsize: Size of the result. Cannot be greater than @bufsize.
1001 *
1002 * Read vpath hardware statistics. This is a subset of stats counters
1003 * from vxge_hal_vpath_stats_hw_info_t {}.
1004 *
1005 */
1006 vxge_hal_status_e
vxge_hal_aux_stats_vpath_hw_read(vxge_hal_vpath_h vpath_handle,int bufsize,char * retbuf,int * retsize)1007 vxge_hal_aux_stats_vpath_hw_read(
1008 vxge_hal_vpath_h vpath_handle,
1009 int bufsize,
1010 char *retbuf,
1011 int *retsize)
1012 {
1013 vxge_hal_status_e status;
1014 vxge_hal_vpath_stats_hw_info_t hw_info;
1015
1016 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1017
1018 vxge_assert(vpath_handle != NULL);
1019
1020 status = vxge_hal_vpath_hw_stats_enable(vpath_handle);
1021 if (status != VXGE_HAL_OK)
1022 return (status);
1023
1024 status = vxge_hal_vpath_hw_stats_get(vpath_handle, &hw_info);
1025 if (status != VXGE_HAL_OK)
1026 return (status);
1027
1028 __HAL_AUX_ENTRY("ini_num_mwr_sent",
1029 hw_info.ini_num_mwr_sent, "%u");
1030 __HAL_AUX_ENTRY("ini_num_mrd_sent",
1031 hw_info.ini_num_mrd_sent, "%u");
1032 __HAL_AUX_ENTRY("ini_num_cpl_rcvd",
1033 hw_info.ini_num_cpl_rcvd, "%u");
1034 __HAL_AUX_ENTRY("ini_num_mwr_byte_sent",
1035 hw_info.ini_num_mwr_byte_sent, "%llu");
1036 __HAL_AUX_ENTRY("ini_num_cpl_byte_rcvd",
1037 hw_info.ini_num_cpl_byte_rcvd, "%llu");
1038 __HAL_AUX_ENTRY("wrcrdtarb_xoff",
1039 hw_info.wrcrdtarb_xoff, "%u");
1040 __HAL_AUX_ENTRY("rdcrdtarb_xoff",
1041 hw_info.rdcrdtarb_xoff, "%u");
1042 __HAL_AUX_ENTRY("vpath_genstats_count0",
1043 hw_info.vpath_genstats_count0, "%u");
1044 __HAL_AUX_ENTRY("vpath_genstats_count1",
1045 hw_info.vpath_genstats_count1, "%u");
1046 __HAL_AUX_ENTRY("vpath_genstats_count2",
1047 hw_info.vpath_genstats_count2, "%u");
1048 __HAL_AUX_ENTRY("vpath_genstats_count3",
1049 hw_info.vpath_genstats_count3, "%u");
1050 __HAL_AUX_ENTRY("vpath_genstats_count4",
1051 hw_info.vpath_genstats_count4, "%u");
1052 __HAL_AUX_ENTRY("vpath_genstats_count5",
1053 hw_info.vpath_genstats_count5, "%u");
1054 __HAL_AUX_ENTRY("tx_ttl_eth_frms",
1055 hw_info.tx_stats.tx_ttl_eth_frms, "%llu");
1056 __HAL_AUX_ENTRY("tx_ttl_eth_octets",
1057 hw_info.tx_stats.tx_ttl_eth_octets, "%llu");
1058 __HAL_AUX_ENTRY("tx_data_octets",
1059 hw_info.tx_stats.tx_data_octets, "%llu");
1060 __HAL_AUX_ENTRY("tx_mcast_frms",
1061 hw_info.tx_stats.tx_mcast_frms, "%llu");
1062 __HAL_AUX_ENTRY("tx_bcast_frms",
1063 hw_info.tx_stats.tx_bcast_frms, "%llu");
1064 __HAL_AUX_ENTRY("tx_ucast_frms",
1065 hw_info.tx_stats.tx_ucast_frms, "%llu");
1066 __HAL_AUX_ENTRY("tx_tagged_frms",
1067 hw_info.tx_stats.tx_tagged_frms, "%llu");
1068 __HAL_AUX_ENTRY("tx_vld_ip",
1069 hw_info.tx_stats.tx_vld_ip, "%llu");
1070 __HAL_AUX_ENTRY("tx_vld_ip_octets",
1071 hw_info.tx_stats.tx_vld_ip_octets, "%llu");
1072 __HAL_AUX_ENTRY("tx_icmp",
1073 hw_info.tx_stats.tx_icmp, "%llu");
1074 __HAL_AUX_ENTRY("tx_tcp",
1075 hw_info.tx_stats.tx_tcp, "%llu");
1076 __HAL_AUX_ENTRY("tx_rst_tcp",
1077 hw_info.tx_stats.tx_rst_tcp, "%llu");
1078 __HAL_AUX_ENTRY("tx_udp",
1079 hw_info.tx_stats.tx_udp, "%llu");
1080 __HAL_AUX_ENTRY("tx_unknown_protocol",
1081 hw_info.tx_stats.tx_unknown_protocol, "%u");
1082 __HAL_AUX_ENTRY("tx_lost_ip",
1083 hw_info.tx_stats.tx_lost_ip, "%u");
1084 __HAL_AUX_ENTRY("tx_parse_error",
1085 hw_info.tx_stats.tx_parse_error, "%u");
1086 __HAL_AUX_ENTRY("tx_tcp_offload",
1087 hw_info.tx_stats.tx_tcp_offload, "%llu");
1088 __HAL_AUX_ENTRY("tx_retx_tcp_offload",
1089 hw_info.tx_stats.tx_retx_tcp_offload, "%llu");
1090 __HAL_AUX_ENTRY("tx_lost_ip_offload",
1091 hw_info.tx_stats.tx_lost_ip_offload, "%llu");
1092 __HAL_AUX_ENTRY("rx_ttl_eth_frms",
1093 hw_info.rx_stats.rx_ttl_eth_frms, "%llu");
1094 __HAL_AUX_ENTRY("rx_vld_frms",
1095 hw_info.rx_stats.rx_vld_frms, "%llu");
1096 __HAL_AUX_ENTRY("rx_offload_frms",
1097 hw_info.rx_stats.rx_offload_frms, "%llu");
1098 __HAL_AUX_ENTRY("rx_ttl_eth_octets",
1099 hw_info.rx_stats.rx_ttl_eth_octets, "%llu");
1100 __HAL_AUX_ENTRY("rx_data_octets",
1101 hw_info.rx_stats.rx_data_octets, "%llu");
1102 __HAL_AUX_ENTRY("rx_offload_octets",
1103 hw_info.rx_stats.rx_offload_octets, "%llu");
1104 __HAL_AUX_ENTRY("rx_vld_mcast_frms",
1105 hw_info.rx_stats.rx_vld_mcast_frms, "%llu");
1106 __HAL_AUX_ENTRY("rx_vld_bcast_frms",
1107 hw_info.rx_stats.rx_vld_bcast_frms, "%llu");
1108 __HAL_AUX_ENTRY("rx_accepted_ucast_frms",
1109 hw_info.rx_stats.rx_accepted_ucast_frms, "%llu");
1110 __HAL_AUX_ENTRY("rx_accepted_nucast_frms",
1111 hw_info.rx_stats.rx_accepted_nucast_frms, "%llu");
1112 __HAL_AUX_ENTRY("rx_tagged_frms",
1113 hw_info.rx_stats.rx_tagged_frms, "%llu");
1114 __HAL_AUX_ENTRY("rx_long_frms",
1115 hw_info.rx_stats.rx_long_frms, "%llu");
1116 __HAL_AUX_ENTRY("rx_usized_frms",
1117 hw_info.rx_stats.rx_usized_frms, "%llu");
1118 __HAL_AUX_ENTRY("rx_osized_frms",
1119 hw_info.rx_stats.rx_osized_frms, "%llu");
1120 __HAL_AUX_ENTRY("rx_frag_frms",
1121 hw_info.rx_stats.rx_frag_frms, "%llu");
1122 __HAL_AUX_ENTRY("rx_jabber_frms",
1123 hw_info.rx_stats.rx_jabber_frms, "%llu");
1124 __HAL_AUX_ENTRY("rx_ttl_64_frms",
1125 hw_info.rx_stats.rx_ttl_64_frms, "%llu");
1126 __HAL_AUX_ENTRY("rx_ttl_65_127_frms",
1127 hw_info.rx_stats.rx_ttl_65_127_frms, "%llu");
1128 __HAL_AUX_ENTRY("rx_ttl_128_255_frms",
1129 hw_info.rx_stats.rx_ttl_128_255_frms, "%llu");
1130 __HAL_AUX_ENTRY("rx_ttl_256_511_frms",
1131 hw_info.rx_stats.rx_ttl_256_511_frms, "%llu");
1132 __HAL_AUX_ENTRY("rx_ttl_512_1023_frms",
1133 hw_info.rx_stats.rx_ttl_512_1023_frms, "%llu");
1134 __HAL_AUX_ENTRY("rx_ttl_1024_1518_frms",
1135 hw_info.rx_stats.rx_ttl_1024_1518_frms, "%llu");
1136 __HAL_AUX_ENTRY("rx_ttl_1519_4095_frms",
1137 hw_info.rx_stats.rx_ttl_1519_4095_frms, "%llu");
1138 __HAL_AUX_ENTRY("rx_ttl_4096_8191_frms",
1139 hw_info.rx_stats.rx_ttl_4096_8191_frms, "%llu");
1140 __HAL_AUX_ENTRY("rx_ttl_8192_max_frms",
1141 hw_info.rx_stats.rx_ttl_8192_max_frms, "%llu");
1142 __HAL_AUX_ENTRY("rx_ttl_gt_max_frms",
1143 hw_info.rx_stats.rx_ttl_gt_max_frms, "%llu");
1144 __HAL_AUX_ENTRY("rx_ip",
1145 hw_info.rx_stats.rx_ip, "%llu");
1146 __HAL_AUX_ENTRY("rx_accepted_ip",
1147 hw_info.rx_stats.rx_accepted_ip, "%llu");
1148 __HAL_AUX_ENTRY("rx_ip_octets",
1149 hw_info.rx_stats.rx_ip_octets, "%llu");
1150 __HAL_AUX_ENTRY("rx_err_ip",
1151 hw_info.rx_stats.rx_err_ip, "%llu");
1152 __HAL_AUX_ENTRY("rx_icmp",
1153 hw_info.rx_stats.rx_icmp, "%llu");
1154 __HAL_AUX_ENTRY("rx_tcp",
1155 hw_info.rx_stats.rx_tcp, "%llu");
1156 __HAL_AUX_ENTRY("rx_udp",
1157 hw_info.rx_stats.rx_udp, "%llu");
1158 __HAL_AUX_ENTRY("rx_err_tcp",
1159 hw_info.rx_stats.rx_err_tcp, "%llu");
1160 __HAL_AUX_ENTRY("rx_lost_frms",
1161 hw_info.rx_stats.rx_lost_frms, "%llu");
1162 __HAL_AUX_ENTRY("rx_lost_ip",
1163 hw_info.rx_stats.rx_lost_ip, "%llu");
1164 __HAL_AUX_ENTRY("rx_lost_ip_offload",
1165 hw_info.rx_stats.rx_lost_ip_offload, "%llu");
1166 __HAL_AUX_ENTRY("rx_various_discard",
1167 hw_info.rx_stats.rx_various_discard, "%u");
1168 __HAL_AUX_ENTRY("rx_sleep_discard",
1169 hw_info.rx_stats.rx_sleep_discard, "%u");
1170 __HAL_AUX_ENTRY("rx_red_discard",
1171 hw_info.rx_stats.rx_red_discard, "%u");
1172 __HAL_AUX_ENTRY("rx_queue_full_discard",
1173 hw_info.rx_stats.rx_queue_full_discard, "%u");
1174 __HAL_AUX_ENTRY("rx_mpa_ok_frms",
1175 hw_info.rx_stats.rx_mpa_ok_frms, "%llu");
1176 __HAL_AUX_ENTRY("prog_event_vnum1",
1177 hw_info.prog_event_vnum1, "%u");
1178 __HAL_AUX_ENTRY("prog_event_vnum0",
1179 hw_info.prog_event_vnum0, "%u");
1180 __HAL_AUX_ENTRY("prog_event_vnum3",
1181 hw_info.prog_event_vnum3, "%u");
1182 __HAL_AUX_ENTRY("prog_event_vnum2",
1183 hw_info.prog_event_vnum2, "%u");
1184 __HAL_AUX_ENTRY("rx_multi_cast_frame_discard",
1185 hw_info.rx_multi_cast_frame_discard, "%u");
1186 __HAL_AUX_ENTRY("rx_frm_transferred",
1187 hw_info.rx_frm_transferred, "%u");
1188 __HAL_AUX_ENTRY("rxd_returned",
1189 hw_info.rxd_returned, "%u");
1190 __HAL_AUX_ENTRY("rx_mpa_len_fail_frms",
1191 hw_info.rx_mpa_len_fail_frms, "%u");
1192 __HAL_AUX_ENTRY("rx_mpa_mrk_fail_frms",
1193 hw_info.rx_mpa_mrk_fail_frms, "%u");
1194 __HAL_AUX_ENTRY("rx_mpa_crc_fail_frms",
1195 hw_info.rx_mpa_crc_fail_frms, "%u");
1196 __HAL_AUX_ENTRY("rx_permitted_frms",
1197 hw_info.rx_permitted_frms, "%u");
1198 __HAL_AUX_ENTRY("rx_vp_reset_discarded_frms",
1199 hw_info.rx_vp_reset_discarded_frms, "%llu");
1200 __HAL_AUX_ENTRY("rx_wol_frms",
1201 hw_info.rx_wol_frms, "%llu");
1202 __HAL_AUX_ENTRY("tx_vp_reset_discarded_frms",
1203 hw_info.tx_vp_reset_discarded_frms, "%llu");
1204
1205 __HAL_AUX_ENTRY_END(bufsize, retsize);
1206
1207 return (VXGE_HAL_OK);
1208 }
1209
1210 /*
1211 * vxge_hal_aux_stats_device_hw_read - Read device hardware statistics.
1212 * @devh: HAL device handle.
1213 * @bufsize: Buffer size.
1214 * @retbuf: Buffer pointer.
1215 * @retsize: Size of the result. Cannot be greater than @bufsize.
1216 *
1217 * Read device hardware statistics. This is a subset of stats counters
1218 * from vxge_hal_device_stats_hw_info_t {}.
1219 *
1220 */
1221 vxge_hal_status_e
vxge_hal_aux_stats_device_hw_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1222 vxge_hal_aux_stats_device_hw_read(vxge_hal_device_h devh,
1223 int bufsize, char *retbuf, int *retsize)
1224 {
1225 u32 i;
1226 int rsize = 0;
1227 vxge_hal_status_e status;
1228 __hal_device_t *hldev = (__hal_device_t *) devh;
1229
1230 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1231
1232 vxge_assert(devh);
1233
1234 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
1235
1236 if (!(hldev->vpaths_deployed & mBIT(i)))
1237 continue;
1238
1239 __HAL_AUX_ENTRY("H/W stats for vpath id", i, "%u");
1240
1241 status = vxge_hal_aux_stats_vpath_hw_read(
1242 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]),
1243 leftsize, ptr, &rsize);
1244
1245 if (status != VXGE_HAL_OK)
1246 return (status);
1247
1248 ptr += rsize;
1249 leftsize -= rsize;
1250
1251 }
1252
1253 __HAL_AUX_ENTRY_END(bufsize, retsize);
1254
1255 return (VXGE_HAL_OK);
1256 }
1257
1258 #define __HAL_AUX_VPATH_SW_COMMON_INFO(prefix, common) {\
1259 __HAL_AUX_ENTRY(prefix"full_cnt", (common)->full_cnt, "%u");\
1260 __HAL_AUX_ENTRY(prefix"usage_cnt", (common)->usage_cnt, "%u");\
1261 __HAL_AUX_ENTRY(prefix"usage_max", (common)->usage_max, "%u");\
1262 __HAL_AUX_ENTRY(prefix"avg_compl_per_intr_cnt",\
1263 (common)->avg_compl_per_intr_cnt, "%u");\
1264 __HAL_AUX_ENTRY(prefix"total_compl_cnt",\
1265 (common)->total_compl_cnt, "%u");\
1266 }
1267
1268 /*
1269 * vxge_hal_aux_stats_vpath_sw_fifo_read - Read vpath fifo software statistics.
1270 * @vpath_handle: HAL Vpath handle.
1271 * @bufsize: Buffer size.
1272 * @retbuf: Buffer pointer.
1273 * @retsize: Size of the result. Cannot be greater than @bufsize.
1274 *
1275 * Read vpath fifo software statistics. This is a subset of stats counters
1276 * from vxge_hal_vpath_stats_sw_fifo_info_t {}.
1277 *
1278 */
1279 vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_fifo_read(vxge_hal_vpath_h vpath_handle,int bufsize,char * retbuf,int * retsize)1280 vxge_hal_aux_stats_vpath_sw_fifo_read(
1281 vxge_hal_vpath_h vpath_handle,
1282 int bufsize,
1283 char *retbuf,
1284 int *retsize)
1285 {
1286 u32 i;
1287 u8 strbuf[256];
1288 vxge_hal_status_e status;
1289 vxge_hal_vpath_stats_sw_fifo_info_t *fifo_info;
1290 vxge_hal_vpath_stats_sw_info_t sw_stats;
1291
1292 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1293
1294 vxge_assert(vpath_handle != NULL);
1295
1296 status = vxge_hal_vpath_sw_stats_get(vpath_handle, &sw_stats);
1297 if (status != VXGE_HAL_OK)
1298 return (status);
1299
1300 fifo_info = &sw_stats.fifo_stats;
1301
1302 __HAL_AUX_VPATH_SW_COMMON_INFO("fifo_",
1303 &fifo_info->common_stats);
1304
1305 __HAL_AUX_ENTRY("total_posts",
1306 fifo_info->total_posts, "%u");
1307 __HAL_AUX_ENTRY("total_buffers",
1308 fifo_info->total_buffers, "%u");
1309 __HAL_AUX_ENTRY("avg_buffers_per_post",
1310 fifo_info->avg_buffers_per_post, "%u");
1311 __HAL_AUX_ENTRY("copied_frags",
1312 fifo_info->copied_frags, "%u");
1313 __HAL_AUX_ENTRY("copied_buffers",
1314 fifo_info->copied_buffers, "%u");
1315 __HAL_AUX_ENTRY("avg_buffer_size",
1316 fifo_info->avg_buffer_size, "%u");
1317 __HAL_AUX_ENTRY("avg_post_size",
1318 fifo_info->avg_post_size, "%u");
1319 __HAL_AUX_ENTRY("total_frags",
1320 fifo_info->total_frags, "%u");
1321 __HAL_AUX_ENTRY("copied_frags",
1322 fifo_info->copied_frags, "%u");
1323 __HAL_AUX_ENTRY("total_posts_dang_dtrs",
1324 fifo_info->total_posts_dang_dtrs, "%u");
1325 __HAL_AUX_ENTRY("total_posts_dang_frags",
1326 fifo_info->total_posts_dang_frags, "%u");
1327
1328 for (i = 0; i < 16; i++) {
1329 (void) vxge_os_snprintf((char *) strbuf,
1330 sizeof(strbuf), "txd_t_code_err_cnt[%d]", i);
1331 __HAL_AUX_ENTRY(strbuf,
1332 fifo_info->txd_t_code_err_cnt[i], "%u");
1333 }
1334
1335 __HAL_AUX_ENTRY_END(bufsize, retsize);
1336
1337 return (VXGE_HAL_OK);
1338 }
1339
1340 /*
1341 * vxge_hal_aux_stats_vpath_sw_ring_read - Read vpath ring software statistics.
1342 * @vpath_handle: HAL Vpath handle.
1343 * @bufsize: Buffer size.
1344 * @retbuf: Buffer pointer.
1345 * @retsize: Size of the result. Cannot be greater than @bufsize.
1346 *
1347 * Read vpath ring software statistics. This is a subset of stats counters
1348 * from vxge_hal_vpath_stats_sw_ring_info_t {}.
1349 *
1350 */
1351 vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_ring_read(vxge_hal_vpath_h vpath_handle,int bufsize,char * retbuf,int * retsize)1352 vxge_hal_aux_stats_vpath_sw_ring_read(
1353 vxge_hal_vpath_h vpath_handle,
1354 int bufsize,
1355 char *retbuf,
1356 int *retsize)
1357 {
1358 u32 i;
1359 u8 strbuf[256];
1360 vxge_hal_status_e status;
1361 vxge_hal_vpath_stats_sw_ring_info_t *ring_info;
1362 vxge_hal_vpath_stats_sw_info_t sw_stats;
1363
1364 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1365
1366 vxge_assert(vpath_handle != NULL);
1367
1368 status = vxge_hal_vpath_sw_stats_get(vpath_handle, &sw_stats);
1369 if (status != VXGE_HAL_OK)
1370 return (status);
1371
1372 ring_info = &sw_stats.ring_stats;
1373
1374 __HAL_AUX_VPATH_SW_COMMON_INFO("ring_",
1375 &ring_info->common_stats);
1376
1377 for (i = 0; i < 16; i++) {
1378 (void) vxge_os_snprintf((char *) strbuf,
1379 sizeof(strbuf), "rxd_t_code_err_cnt[%d]", i);
1380 __HAL_AUX_ENTRY(strbuf,
1381 ring_info->rxd_t_code_err_cnt[i], "%u");
1382 }
1383
1384 __HAL_AUX_ENTRY_END(bufsize, retsize);
1385
1386 return (VXGE_HAL_OK);
1387 }
1388
1389
1390 /*
1391 * vxge_hal_aux_stats_vpath_sw_err_read - Read vpath err software statistics.
1392 * @vpath_handle: HAL Vpath handle.
1393 * @bufsize: Buffer size.
1394 * @retbuf: Buffer pointer.
1395 * @retsize: Size of the result. Cannot be greater than @bufsize.
1396 *
1397 * Read vpath err software statistics. This is a subset of stats counters
1398 * from vxge_hal_vpath_stats_sw_err_info_t {}.
1399 *
1400 */
1401 vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_err_read(vxge_hal_vpath_h vpath_handle,int bufsize,char * retbuf,int * retsize)1402 vxge_hal_aux_stats_vpath_sw_err_read(
1403 vxge_hal_vpath_h vpath_handle,
1404 int bufsize,
1405 char *retbuf,
1406 int *retsize)
1407 {
1408 vxge_hal_vpath_stats_sw_err_t *err_info;
1409 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
1410
1411 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1412
1413 vxge_assert(vpath_handle != NULL);
1414
1415 err_info = &vp->vpath->sw_stats->error_stats;
1416
1417 __HAL_AUX_ENTRY("unknown_alarms",
1418 err_info->unknown_alarms, "%u");
1419 __HAL_AUX_ENTRY("network_sustained_fault",
1420 err_info->network_sustained_fault, "%u");
1421 __HAL_AUX_ENTRY("network_sustained_ok",
1422 err_info->network_sustained_ok, "%u");
1423 __HAL_AUX_ENTRY("kdfcctl_fifo0_overwrite",
1424 err_info->kdfcctl_fifo0_overwrite, "%u");
1425 __HAL_AUX_ENTRY("kdfcctl_fifo0_poison",
1426 err_info->kdfcctl_fifo0_poison, "%u");
1427 __HAL_AUX_ENTRY("kdfcctl_fifo0_dma_error",
1428 err_info->kdfcctl_fifo0_dma_error, "%u");
1429 __HAL_AUX_ENTRY("kdfcctl_fifo1_overwrite",
1430 err_info->kdfcctl_fifo1_overwrite, "%u");
1431 __HAL_AUX_ENTRY("kdfcctl_fifo1_poison",
1432 err_info->kdfcctl_fifo1_poison, "%u");
1433 __HAL_AUX_ENTRY("kdfcctl_fifo1_dma_error",
1434 err_info->kdfcctl_fifo1_dma_error, "%u");
1435 __HAL_AUX_ENTRY("kdfcctl_fifo2_overwrite",
1436 err_info->kdfcctl_fifo2_overwrite, "%u");
1437 __HAL_AUX_ENTRY("kdfcctl_fifo2_poison",
1438 err_info->kdfcctl_fifo2_poison, "%u");
1439 __HAL_AUX_ENTRY("kdfcctl_fifo2_dma_error",
1440 err_info->kdfcctl_fifo2_dma_error, "%u");
1441 __HAL_AUX_ENTRY("dblgen_fifo0_overflow",
1442 err_info->dblgen_fifo0_overflow, "%u");
1443 __HAL_AUX_ENTRY("dblgen_fifo1_overflow",
1444 err_info->dblgen_fifo1_overflow, "%u");
1445 __HAL_AUX_ENTRY("dblgen_fifo2_overflow",
1446 err_info->dblgen_fifo2_overflow, "%u");
1447 __HAL_AUX_ENTRY("statsb_pif_chain_error",
1448 err_info->statsb_pif_chain_error, "%u");
1449 __HAL_AUX_ENTRY("statsb_drop_timeout",
1450 err_info->statsb_drop_timeout, "%u");
1451 __HAL_AUX_ENTRY("target_illegal_access",
1452 err_info->target_illegal_access, "%u");
1453 __HAL_AUX_ENTRY("ini_serr_det",
1454 err_info->ini_serr_det, "%u");
1455 __HAL_AUX_ENTRY("pci_config_status_err",
1456 err_info->pci_config_status_err, "%u");
1457 __HAL_AUX_ENTRY("pci_config_uncor_err",
1458 err_info->pci_config_uncor_err, "%u");
1459 __HAL_AUX_ENTRY("pci_config_cor_err",
1460 err_info->pci_config_cor_err, "%u");
1461 __HAL_AUX_ENTRY("mrpcim_to_vpath_alarms",
1462 err_info->mrpcim_to_vpath_alarms, "%u");
1463 __HAL_AUX_ENTRY("srpcim_to_vpath_alarms",
1464 err_info->srpcim_to_vpath_alarms, "%u");
1465 __HAL_AUX_ENTRY("srpcim_msg_to_vpath",
1466 err_info->srpcim_msg_to_vpath, "%u");
1467 __HAL_AUX_ENTRY("prc_ring_bumps",
1468 err_info->prc_ring_bumps, "%u");
1469 __HAL_AUX_ENTRY("prc_rxdcm_sc_err",
1470 err_info->prc_rxdcm_sc_err, "%u");
1471 __HAL_AUX_ENTRY("prc_rxdcm_sc_abort",
1472 err_info->prc_rxdcm_sc_abort, "%u");
1473 __HAL_AUX_ENTRY("prc_quanta_size_err",
1474 err_info->prc_quanta_size_err, "%u");
1475
1476 __HAL_AUX_ENTRY_END(bufsize, retsize);
1477
1478 return (VXGE_HAL_OK);
1479 }
1480
1481 /*
1482 * vxge_hal_aux_stats_vpath_sw_read - Read vpath soft statistics.
1483 * @vpath_handle: HAL Vpath handle.
1484 * @bufsize: Buffer size.
1485 * @retbuf: Buffer pointer.
1486 * @retsize: Size of the result. Cannot be greater than @bufsize.
1487 *
1488 * Read device hardware statistics. This is a subset of stats counters
1489 * from vxge_hal_vpath_stats_sw_info_t {}.
1490 *
1491 */
1492 vxge_hal_status_e
vxge_hal_aux_stats_vpath_sw_read(vxge_hal_vpath_h vpath_handle,int bufsize,char * retbuf,int * retsize)1493 vxge_hal_aux_stats_vpath_sw_read(
1494 vxge_hal_vpath_h vpath_handle,
1495 int bufsize,
1496 char *retbuf,
1497 int *retsize)
1498 {
1499 int rsize = 0;
1500 vxge_hal_status_e status;
1501 vxge_hal_vpath_stats_sw_info_t *sw_info;
1502 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
1503
1504 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1505
1506 vxge_assert(vpath_handle != NULL);
1507
1508 sw_info = vp->vpath->sw_stats;
1509
1510 __HAL_AUX_ENTRY("soft_reset_cnt", sw_info->soft_reset_cnt, "%u");
1511
1512
1513 status = vxge_hal_aux_stats_vpath_sw_err_read(vpath_handle,
1514 leftsize, ptr, &rsize);
1515 if (status != VXGE_HAL_OK)
1516 return (status);
1517
1518 ptr += rsize;
1519 leftsize -= rsize;
1520
1521 status = vxge_hal_aux_stats_vpath_sw_ring_read(vpath_handle,
1522 leftsize, ptr, &rsize);
1523 if (status != VXGE_HAL_OK)
1524 return (status);
1525
1526 ptr += rsize;
1527 leftsize -= rsize;
1528
1529 status = vxge_hal_aux_stats_vpath_sw_fifo_read(vpath_handle,
1530 leftsize, ptr, &rsize);
1531 if (status != VXGE_HAL_OK)
1532 return (status);
1533
1534
1535 leftsize -= rsize;
1536
1537 __HAL_AUX_ENTRY_END(bufsize, retsize);
1538
1539 return (VXGE_HAL_OK);
1540 }
1541
1542 /*
1543 * vxge_hal_aux_stats_device_sw_read - Read device software statistics.
1544 * @devh: HAL device handle.
1545 * @bufsize: Buffer size.
1546 * @retbuf: Buffer pointer.
1547 * @retsize: Size of the result. Cannot be greater than @bufsize.
1548 *
1549 * Read device software statistics. This is a subset of stats counters
1550 * from vxge_hal_device_stats_sw_info_t {}.
1551 *
1552 */
1553 vxge_hal_status_e
vxge_hal_aux_stats_device_sw_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1554 vxge_hal_aux_stats_device_sw_read(vxge_hal_device_h devh,
1555 int bufsize, char *retbuf, int *retsize)
1556 {
1557 u32 i;
1558 int rsize = 0;
1559 vxge_hal_status_e status;
1560 __hal_device_t *hldev = (__hal_device_t *) devh;
1561
1562 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1563
1564 vxge_assert(devh);
1565
1566 __HAL_AUX_ENTRY("not_traffic_intr_cnt",
1567 hldev->header.not_traffic_intr_cnt, "%u");
1568 __HAL_AUX_ENTRY("traffic_intr_cnt",
1569 hldev->header.traffic_intr_cnt, "%u");
1570 __HAL_AUX_ENTRY("total_intr_cnt",
1571 hldev->header.not_traffic_intr_cnt +
1572 hldev->header.traffic_intr_cnt, "%u");
1573 __HAL_AUX_ENTRY("soft_reset_cnt",
1574 hldev->stats.sw_dev_info_stats.soft_reset_cnt, "%u");
1575
1576 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
1577
1578 if (!(hldev->vpaths_deployed & mBIT(i)))
1579 continue;
1580
1581 __HAL_AUX_ENTRY("S/W stats for vpath id", i, "%u");
1582
1583 status = vxge_hal_aux_stats_vpath_sw_read(
1584 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]),
1585 leftsize, ptr, &rsize);
1586
1587 if (status != VXGE_HAL_OK)
1588 return (status);
1589
1590 ptr += rsize;
1591 leftsize -= rsize;
1592 }
1593
1594 __HAL_AUX_ENTRY_END(bufsize, retsize);
1595
1596 return (VXGE_HAL_OK);
1597 }
1598
1599 /*
1600 * vxge_hal_aux_stats_device_sw_err_read - Read device software error statistics
1601 * @devh: HAL device handle.
1602 * @bufsize: Buffer size.
1603 * @retbuf: Buffer pointer.
1604 * @retsize: Size of the result. Cannot be greater than @bufsize.
1605 *
1606 * Read device software error statistics. This is a subset of stats counters
1607 * from vxge_hal_device_stats_sw_info_t {}.
1608 *
1609 */
1610 vxge_hal_status_e
vxge_hal_aux_stats_device_sw_err_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1611 vxge_hal_aux_stats_device_sw_err_read(vxge_hal_device_h devh,
1612 int bufsize, char *retbuf, int *retsize)
1613 {
1614 vxge_hal_device_stats_sw_err_t *sw_err;
1615 __hal_device_t *hldev = (__hal_device_t *) devh;
1616
1617 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1618
1619 vxge_assert(devh);
1620
1621 sw_err = &hldev->stats.sw_dev_err_stats;
1622
1623 __HAL_AUX_ENTRY("mrpcim_alarms", sw_err->mrpcim_alarms, "%u");
1624 __HAL_AUX_ENTRY("srpcim_alarms", sw_err->srpcim_alarms, "%u");
1625 __HAL_AUX_ENTRY("vpath_alarms", sw_err->vpath_alarms, "%u");
1626
1627 __HAL_AUX_ENTRY_END(bufsize, retsize);
1628
1629 return (VXGE_HAL_OK);
1630 }
1631
1632 /*
1633 * vxge_hal_aux_stats_device_read - Read device statistics.
1634 * @devh: HAL device handle.
1635 * @bufsize: Buffer size.
1636 * @retbuf: Buffer pointer.
1637 * @retsize: Size of the result. Cannot be greater than @bufsize.
1638 *
1639 * Read device statistics. This is a subset of stats counters
1640 * from vxge_hal_device_stats_t {}.
1641 *
1642 */
1643 vxge_hal_status_e
vxge_hal_aux_stats_device_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1644 vxge_hal_aux_stats_device_read(vxge_hal_device_h devh,
1645 int bufsize, char *retbuf, int *retsize)
1646 {
1647 char *ptr = retbuf;
1648 int rsize = 0, leftsize = bufsize;
1649 vxge_hal_status_e status;
1650
1651 vxge_assert(devh);
1652
1653 status = vxge_hal_aux_stats_device_hw_read(devh,
1654 leftsize, ptr, &rsize);
1655 if (status != VXGE_HAL_OK)
1656 return (status);
1657
1658 ptr += rsize;
1659 leftsize -= rsize;
1660
1661 status = vxge_hal_aux_stats_device_sw_err_read(devh,
1662 leftsize, ptr, &rsize);
1663 if (status != VXGE_HAL_OK)
1664 return (status);
1665
1666 ptr += rsize;
1667 leftsize -= rsize;
1668
1669 status = vxge_hal_aux_stats_device_sw_read(devh,
1670 leftsize, ptr, &rsize);
1671 if (status != VXGE_HAL_OK)
1672 return (status);
1673
1674 leftsize -= rsize;
1675
1676 __HAL_AUX_ENTRY_END(bufsize, retsize);
1677
1678 return (VXGE_HAL_OK);
1679 }
1680
1681 /*
1682 * vxge_hal_aux_stats_xpak_read - Read device xpak statistics.
1683 * @devh: HAL device handle.
1684 * @bufsize: Buffer size.
1685 * @retbuf: Buffer pointer.
1686 * @retsize: Size of the result. Cannot be greater than @bufsize.
1687 *
1688 * Read device xpak statistics. This is valid for function 0 device only
1689 *
1690 */
1691 vxge_hal_status_e
vxge_hal_aux_stats_xpak_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1692 vxge_hal_aux_stats_xpak_read(vxge_hal_device_h devh,
1693 int bufsize, char *retbuf, int *retsize)
1694 {
1695 u32 i;
1696 vxge_hal_mrpcim_xpak_stats_t *xpak_stats;
1697 __hal_device_t *hldev = (__hal_device_t *) devh;
1698
1699 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1700
1701 vxge_assert(devh);
1702
1703 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM))
1704 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
1705
1706 for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
1707
1708 xpak_stats = &hldev->mrpcim->xpak_stats[i];
1709
1710 __HAL_AUX_ENTRY("Wire Port Id : ", i, "%u");
1711 __HAL_AUX_ENTRY("alarm_transceiver_temp_high",
1712 xpak_stats->excess_bias_current, "%u");
1713 __HAL_AUX_ENTRY("alarm_transceiver_temp_high",
1714 xpak_stats->excess_laser_output, "%u");
1715 __HAL_AUX_ENTRY("alarm_transceiver_temp_high",
1716 xpak_stats->excess_temp, "%u");
1717 __HAL_AUX_ENTRY("alarm_transceiver_temp_high",
1718 xpak_stats->alarm_transceiver_temp_high, "%u");
1719 __HAL_AUX_ENTRY("alarm_transceiver_temp_low",
1720 xpak_stats->alarm_transceiver_temp_low, "%u");
1721 __HAL_AUX_ENTRY("alarm_laser_bias_current_high",
1722 xpak_stats->alarm_laser_bias_current_high, "%u");
1723 __HAL_AUX_ENTRY("alarm_laser_bias_current_low",
1724 xpak_stats->alarm_laser_bias_current_low, "%u");
1725 __HAL_AUX_ENTRY("alarm_laser_output_power_high",
1726 xpak_stats->alarm_laser_output_power_high, "%u");
1727 __HAL_AUX_ENTRY("alarm_laser_output_power_low",
1728 xpak_stats->alarm_laser_output_power_low, "%u");
1729 __HAL_AUX_ENTRY("warn_transceiver_temp_high",
1730 xpak_stats->warn_transceiver_temp_high, "%u");
1731 __HAL_AUX_ENTRY("warn_transceiver_temp_low",
1732 xpak_stats->warn_transceiver_temp_low, "%u");
1733 __HAL_AUX_ENTRY("warn_laser_bias_current_high",
1734 xpak_stats->warn_laser_bias_current_high, "%u");
1735 __HAL_AUX_ENTRY("warn_laser_bias_current_low",
1736 xpak_stats->warn_laser_bias_current_low, "%u");
1737 __HAL_AUX_ENTRY("warn_laser_output_power_high",
1738 xpak_stats->warn_laser_output_power_high, "%u");
1739 __HAL_AUX_ENTRY("warn_laser_output_power_low",
1740 xpak_stats->warn_laser_output_power_low, "%u");
1741
1742 }
1743
1744 __HAL_AUX_ENTRY_END(bufsize, retsize);
1745
1746 return (VXGE_HAL_OK);
1747 }
1748 /*
1749 * vxge_hal_aux_stats_mrpcim_read - Read device mrpcim statistics.
1750 * @devh: HAL device handle.
1751 * @bufsize: Buffer size.
1752 * @retbuf: Buffer pointer.
1753 * @retsize: Size of the result. Cannot be greater than @bufsize.
1754 *
1755 * Read device mrpcim statistics. This is valid for function 0 device only
1756 *
1757 */
1758 vxge_hal_status_e
vxge_hal_aux_stats_mrpcim_read(vxge_hal_device_h devh,int bufsize,char * retbuf,int * retsize)1759 vxge_hal_aux_stats_mrpcim_read(vxge_hal_device_h devh,
1760 int bufsize, char *retbuf, int *retsize)
1761 {
1762 vxge_hal_status_e status;
1763 vxge_hal_mrpcim_stats_hw_info_t mrpcim_info;
1764 __hal_device_t *hldev = (__hal_device_t *) devh;
1765
1766 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
1767
1768 vxge_assert(devh);
1769
1770 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM))
1771 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
1772
1773 status = vxge_hal_mrpcim_stats_enable(devh);
1774 if (status != VXGE_HAL_OK)
1775 return (status);
1776
1777 status = vxge_hal_mrpcim_stats_get(devh, &mrpcim_info);
1778 if (status != VXGE_HAL_OK)
1779 return (status);
1780
1781 __HAL_AUX_ENTRY("pic_ini_rd_drop", mrpcim_info.pic_ini_rd_drop, "%u");
1782 __HAL_AUX_ENTRY("pic_ini_wr_drop", mrpcim_info.pic_ini_wr_drop, "%u");
1783
1784 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane0",
1785 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[0].
1786 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1787 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane1",
1788 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[1].
1789 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1790 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane2",
1791 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[2].
1792 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1793 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane3",
1794 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[3].
1795 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1796 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane4",
1797 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[4].
1798 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1799 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane5",
1800 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[5].
1801 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1802 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane6",
1803 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[6].
1804 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1805 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane7",
1806 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[7].
1807 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1808 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane8",
1809 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[8].
1810 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1811 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane9",
1812 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[9].
1813 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1814 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane10",
1815 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[10].
1816 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1817 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane11",
1818 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[11].
1819 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1820 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane12",
1821 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[12].
1822 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1823 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane13",
1824 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[13].
1825 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1826 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane14",
1827 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[14].
1828 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1829 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane15",
1830 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[15].
1831 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1832 __HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane16",
1833 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[16].
1834 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1835
1836 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane0",
1837 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[0].
1838 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1839 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane1",
1840 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[1].
1841 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1842 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane2",
1843 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[2].
1844 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1845 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane3",
1846 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[3].
1847 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1848 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane4",
1849 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[4].
1850 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1851 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane5",
1852 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[5].
1853 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1854 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane6",
1855 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[6].
1856 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1857 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane7",
1858 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[7].
1859 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1860 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane8",
1861 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[8].
1862 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1863 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane9",
1864 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[9].
1865 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1866 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane10",
1867 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[10].
1868 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1869 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane11",
1870 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[11].
1871 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1872 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane12",
1873 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[12].
1874 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1875 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane13",
1876 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[13].
1877 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1878 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane14",
1879 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[14].
1880 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1881 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane15",
1882 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[15].
1883 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1884 __HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane16",
1885 mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[16].
1886 pic_wrcrdtarb_pd_crdt_depleted, "%u");
1887
1888 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane0",
1889 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[0].
1890 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1891 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane1",
1892 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[1].
1893 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1894 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane2",
1895 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[2].
1896 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1897 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane3",
1898 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[3].
1899 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1900 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane4",
1901 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[4].
1902 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1903 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane5",
1904 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[5].
1905 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1906 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane6",
1907 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[6].
1908 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1909 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane7",
1910 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[7].
1911 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1912 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane8",
1913 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[8].
1914 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1915 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane9",
1916 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[9].
1917 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1918 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane10",
1919 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[10].
1920 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1921 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane11",
1922 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[11].
1923 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1924 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane12",
1925 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[12].
1926 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1927 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane13",
1928 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[13].
1929 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1930 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane14",
1931 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[14].
1932 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1933 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane15",
1934 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[15].
1935 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1936 __HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane16",
1937 mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[16].
1938 pic_rdcrdtarb_nph_crdt_depleted, "%u");
1939
1940 __HAL_AUX_ENTRY("pic_ini_rd_vpin_drop",
1941 mrpcim_info.pic_ini_rd_vpin_drop, "%u");
1942 __HAL_AUX_ENTRY("pic_ini_wr_vpin_drop",
1943 mrpcim_info.pic_ini_wr_vpin_drop, "%u");
1944 __HAL_AUX_ENTRY("pic_genstats_count0",
1945 mrpcim_info.pic_genstats_count0, "%u");
1946 __HAL_AUX_ENTRY("pic_genstats_count1",
1947 mrpcim_info.pic_genstats_count1, "%u");
1948 __HAL_AUX_ENTRY("pic_genstats_count2",
1949 mrpcim_info.pic_genstats_count2, "%u");
1950 __HAL_AUX_ENTRY("pic_genstats_count3",
1951 mrpcim_info.pic_genstats_count3, "%u");
1952 __HAL_AUX_ENTRY("pic_genstats_count4",
1953 mrpcim_info.pic_genstats_count4, "%u");
1954 __HAL_AUX_ENTRY("pic_genstats_count5",
1955 mrpcim_info.pic_genstats_count5, "%u");
1956 __HAL_AUX_ENTRY("pci_rstdrop_cpl",
1957 mrpcim_info.pci_rstdrop_cpl, "%u");
1958 __HAL_AUX_ENTRY("pci_rstdrop_msg",
1959 mrpcim_info.pci_rstdrop_msg, "%u");
1960 __HAL_AUX_ENTRY("pci_rstdrop_client1",
1961 mrpcim_info.pci_rstdrop_client1, "%u");
1962 __HAL_AUX_ENTRY("pci_rstdrop_client0",
1963 mrpcim_info.pci_rstdrop_client0, "%u");
1964 __HAL_AUX_ENTRY("pci_rstdrop_client2",
1965 mrpcim_info.pci_rstdrop_client2, "%u");
1966
1967 __HAL_AUX_ENTRY("pci_depl_cplh_vplane0",
1968 mrpcim_info.pci_depl_h_vplane[0].pci_depl_cplh, "%u");
1969 __HAL_AUX_ENTRY("pci_depl_nph_vplane0",
1970 mrpcim_info.pci_depl_h_vplane[0].pci_depl_nph, "%u");
1971 __HAL_AUX_ENTRY("pci_depl_ph_vplane0",
1972 mrpcim_info.pci_depl_h_vplane[0].pci_depl_ph, "%u");
1973 __HAL_AUX_ENTRY("pci_depl_cplh_vplane1",
1974 mrpcim_info.pci_depl_h_vplane[1].pci_depl_cplh, "%u");
1975 __HAL_AUX_ENTRY("pci_depl_nph_vplane1",
1976 mrpcim_info.pci_depl_h_vplane[1].pci_depl_nph, "%u");
1977 __HAL_AUX_ENTRY("pci_depl_ph_vplane1",
1978 mrpcim_info.pci_depl_h_vplane[1].pci_depl_ph, "%u");
1979 __HAL_AUX_ENTRY("pci_depl_cplh_vplane2",
1980 mrpcim_info.pci_depl_h_vplane[2].pci_depl_cplh, "%u");
1981 __HAL_AUX_ENTRY("pci_depl_nph_vplane2",
1982 mrpcim_info.pci_depl_h_vplane[2].pci_depl_nph, "%u");
1983 __HAL_AUX_ENTRY("pci_depl_ph_vplane2",
1984 mrpcim_info.pci_depl_h_vplane[2].pci_depl_ph, "%u");
1985 __HAL_AUX_ENTRY("pci_depl_cplh_vplane3",
1986 mrpcim_info.pci_depl_h_vplane[3].pci_depl_cplh, "%u");
1987 __HAL_AUX_ENTRY("pci_depl_nph_vplane3",
1988 mrpcim_info.pci_depl_h_vplane[3].pci_depl_nph, "%u");
1989 __HAL_AUX_ENTRY("pci_depl_ph_vplane3",
1990 mrpcim_info.pci_depl_h_vplane[3].pci_depl_ph, "%u");
1991 __HAL_AUX_ENTRY("pci_depl_cplh_vplane4",
1992 mrpcim_info.pci_depl_h_vplane[4].pci_depl_cplh, "%u");
1993 __HAL_AUX_ENTRY("pci_depl_nph_vplane4",
1994 mrpcim_info.pci_depl_h_vplane[4].pci_depl_nph, "%u");
1995 __HAL_AUX_ENTRY("pci_depl_ph_vplane4",
1996 mrpcim_info.pci_depl_h_vplane[4].pci_depl_ph, "%u");
1997 __HAL_AUX_ENTRY("pci_depl_cplh_vplane5",
1998 mrpcim_info.pci_depl_h_vplane[5].pci_depl_cplh, "%u");
1999 __HAL_AUX_ENTRY("pci_depl_nph_vplane5",
2000 mrpcim_info.pci_depl_h_vplane[5].pci_depl_nph, "%u");
2001 __HAL_AUX_ENTRY("pci_depl_ph_vplane5",
2002 mrpcim_info.pci_depl_h_vplane[5].pci_depl_ph, "%u");
2003 __HAL_AUX_ENTRY("pci_depl_cplh_vplane6",
2004 mrpcim_info.pci_depl_h_vplane[6].pci_depl_cplh, "%u");
2005 __HAL_AUX_ENTRY("pci_depl_nph_vplane6",
2006 mrpcim_info.pci_depl_h_vplane[6].pci_depl_nph, "%u");
2007 __HAL_AUX_ENTRY("pci_depl_ph_vplane6",
2008 mrpcim_info.pci_depl_h_vplane[6].pci_depl_ph, "%u");
2009 __HAL_AUX_ENTRY("pci_depl_cplh_vplane7",
2010 mrpcim_info.pci_depl_h_vplane[7].pci_depl_cplh, "%u");
2011 __HAL_AUX_ENTRY("pci_depl_nph_vplane7",
2012 mrpcim_info.pci_depl_h_vplane[7].pci_depl_nph, "%u");
2013 __HAL_AUX_ENTRY("pci_depl_ph_vplane7",
2014 mrpcim_info.pci_depl_h_vplane[7].pci_depl_ph, "%u");
2015 __HAL_AUX_ENTRY("pci_depl_cplh_vplane8",
2016 mrpcim_info.pci_depl_h_vplane[8].pci_depl_cplh, "%u");
2017 __HAL_AUX_ENTRY("pci_depl_nph_vplane8",
2018 mrpcim_info.pci_depl_h_vplane[8].pci_depl_nph, "%u");
2019 __HAL_AUX_ENTRY("pci_depl_ph_vplane8",
2020 mrpcim_info.pci_depl_h_vplane[8].pci_depl_ph, "%u");
2021 __HAL_AUX_ENTRY("pci_depl_cplh_vplane9",
2022 mrpcim_info.pci_depl_h_vplane[9].pci_depl_cplh, "%u");
2023 __HAL_AUX_ENTRY("pci_depl_nph_vplane9",
2024 mrpcim_info.pci_depl_h_vplane[9].pci_depl_nph, "%u");
2025 __HAL_AUX_ENTRY("pci_depl_ph_vplane9",
2026 mrpcim_info.pci_depl_h_vplane[9].pci_depl_ph, "%u");
2027 __HAL_AUX_ENTRY("pci_depl_cplh_vplane10",
2028 mrpcim_info.pci_depl_h_vplane[10].pci_depl_cplh, "%u");
2029 __HAL_AUX_ENTRY("pci_depl_nph_vplane10",
2030 mrpcim_info.pci_depl_h_vplane[10].pci_depl_nph, "%u");
2031 __HAL_AUX_ENTRY("pci_depl_ph_vplane10",
2032 mrpcim_info.pci_depl_h_vplane[10].pci_depl_ph, "%u");
2033 __HAL_AUX_ENTRY("pci_depl_cplh_vplane11",
2034 mrpcim_info.pci_depl_h_vplane[11].pci_depl_cplh, "%u");
2035 __HAL_AUX_ENTRY("pci_depl_nph_vplane11",
2036 mrpcim_info.pci_depl_h_vplane[11].pci_depl_nph, "%u");
2037 __HAL_AUX_ENTRY("pci_depl_ph_vplane11",
2038 mrpcim_info.pci_depl_h_vplane[11].pci_depl_ph, "%u");
2039 __HAL_AUX_ENTRY("pci_depl_cplh_vplane12",
2040 mrpcim_info.pci_depl_h_vplane[12].pci_depl_cplh, "%u");
2041 __HAL_AUX_ENTRY("pci_depl_nph_vplane12",
2042 mrpcim_info.pci_depl_h_vplane[12].pci_depl_nph, "%u");
2043 __HAL_AUX_ENTRY("pci_depl_ph_vplane12",
2044 mrpcim_info.pci_depl_h_vplane[12].pci_depl_ph, "%u");
2045 __HAL_AUX_ENTRY("pci_depl_cplh_vplane13",
2046 mrpcim_info.pci_depl_h_vplane[13].pci_depl_cplh, "%u");
2047 __HAL_AUX_ENTRY("pci_depl_nph_vplane13",
2048 mrpcim_info.pci_depl_h_vplane[13].pci_depl_nph, "%u");
2049 __HAL_AUX_ENTRY("pci_depl_ph_vplane13",
2050 mrpcim_info.pci_depl_h_vplane[13].pci_depl_ph, "%u");
2051 __HAL_AUX_ENTRY("pci_depl_cplh_vplane14",
2052 mrpcim_info.pci_depl_h_vplane[14].pci_depl_cplh, "%u");
2053 __HAL_AUX_ENTRY("pci_depl_nph_vplane14",
2054 mrpcim_info.pci_depl_h_vplane[14].pci_depl_nph, "%u");
2055 __HAL_AUX_ENTRY("pci_depl_ph_vplane14",
2056 mrpcim_info.pci_depl_h_vplane[14].pci_depl_ph, "%u");
2057 __HAL_AUX_ENTRY("pci_depl_cplh_vplane15",
2058 mrpcim_info.pci_depl_h_vplane[15].pci_depl_cplh, "%u");
2059 __HAL_AUX_ENTRY("pci_depl_nph_vplane15",
2060 mrpcim_info.pci_depl_h_vplane[15].pci_depl_nph, "%u");
2061 __HAL_AUX_ENTRY("pci_depl_ph_vplane15",
2062 mrpcim_info.pci_depl_h_vplane[15].pci_depl_ph, "%u");
2063 __HAL_AUX_ENTRY("pci_depl_cplh_vplane16",
2064 mrpcim_info.pci_depl_h_vplane[16].pci_depl_cplh, "%u");
2065 __HAL_AUX_ENTRY("pci_depl_nph_vplane16",
2066 mrpcim_info.pci_depl_h_vplane[16].pci_depl_nph, "%u");
2067 __HAL_AUX_ENTRY("pci_depl_ph_vplane16",
2068 mrpcim_info.pci_depl_h_vplane[16].pci_depl_ph, "%u");
2069
2070 __HAL_AUX_ENTRY("pci_depl_cpld_vplane0",
2071 mrpcim_info.pci_depl_d_vplane[0].pci_depl_cpld, "%u");
2072 __HAL_AUX_ENTRY("pci_depl_npd_vplane0",
2073 mrpcim_info.pci_depl_d_vplane[0].pci_depl_npd, "%u");
2074 __HAL_AUX_ENTRY("pci_depl_pd_vplane0",
2075 mrpcim_info.pci_depl_d_vplane[0].pci_depl_pd, "%u");
2076 __HAL_AUX_ENTRY("pci_depl_cpld_vplane1",
2077 mrpcim_info.pci_depl_d_vplane[1].pci_depl_cpld, "%u");
2078 __HAL_AUX_ENTRY("pci_depl_npd_vplane1",
2079 mrpcim_info.pci_depl_d_vplane[1].pci_depl_npd, "%u");
2080 __HAL_AUX_ENTRY("pci_depl_pd_vplane1",
2081 mrpcim_info.pci_depl_d_vplane[1].pci_depl_pd, "%u");
2082 __HAL_AUX_ENTRY("pci_depl_cpld_vplane2",
2083 mrpcim_info.pci_depl_d_vplane[2].pci_depl_cpld, "%u");
2084 __HAL_AUX_ENTRY("pci_depl_npd_vplane2",
2085 mrpcim_info.pci_depl_d_vplane[2].pci_depl_npd, "%u");
2086 __HAL_AUX_ENTRY("pci_depl_pd_vplane2",
2087 mrpcim_info.pci_depl_d_vplane[2].pci_depl_pd, "%u");
2088 __HAL_AUX_ENTRY("pci_depl_cpld_vplane3",
2089 mrpcim_info.pci_depl_d_vplane[3].pci_depl_cpld, "%u");
2090 __HAL_AUX_ENTRY("pci_depl_npd_vplane3",
2091 mrpcim_info.pci_depl_d_vplane[3].pci_depl_npd, "%u");
2092 __HAL_AUX_ENTRY("pci_depl_pd_vplane3",
2093 mrpcim_info.pci_depl_d_vplane[3].pci_depl_pd, "%u");
2094 __HAL_AUX_ENTRY("pci_depl_cpld_vplane4",
2095 mrpcim_info.pci_depl_d_vplane[4].pci_depl_cpld, "%u");
2096 __HAL_AUX_ENTRY("pci_depl_npd_vplane4",
2097 mrpcim_info.pci_depl_d_vplane[4].pci_depl_npd, "%u");
2098 __HAL_AUX_ENTRY("pci_depl_pd_vplane4",
2099 mrpcim_info.pci_depl_d_vplane[4].pci_depl_pd, "%u");
2100 __HAL_AUX_ENTRY("pci_depl_cpld_vplane5",
2101 mrpcim_info.pci_depl_d_vplane[5].pci_depl_cpld, "%u");
2102 __HAL_AUX_ENTRY("pci_depl_npd_vplane5",
2103 mrpcim_info.pci_depl_d_vplane[5].pci_depl_npd, "%u");
2104 __HAL_AUX_ENTRY("pci_depl_pd_vplane5",
2105 mrpcim_info.pci_depl_d_vplane[5].pci_depl_pd, "%u");
2106 __HAL_AUX_ENTRY("pci_depl_cpld_vplane6",
2107 mrpcim_info.pci_depl_d_vplane[6].pci_depl_cpld, "%u");
2108 __HAL_AUX_ENTRY("pci_depl_npd_vplane6",
2109 mrpcim_info.pci_depl_d_vplane[6].pci_depl_npd, "%u");
2110 __HAL_AUX_ENTRY("pci_depl_pd_vplane6",
2111 mrpcim_info.pci_depl_d_vplane[6].pci_depl_pd, "%u");
2112 __HAL_AUX_ENTRY("pci_depl_cpld_vplane7",
2113 mrpcim_info.pci_depl_d_vplane[7].pci_depl_cpld, "%u");
2114 __HAL_AUX_ENTRY("pci_depl_npd_vplane7",
2115 mrpcim_info.pci_depl_d_vplane[7].pci_depl_npd, "%u");
2116 __HAL_AUX_ENTRY("pci_depl_pd_vplane7",
2117 mrpcim_info.pci_depl_d_vplane[7].pci_depl_pd, "%u");
2118 __HAL_AUX_ENTRY("pci_depl_cpld_vplane8",
2119 mrpcim_info.pci_depl_d_vplane[8].pci_depl_cpld, "%u");
2120 __HAL_AUX_ENTRY("pci_depl_npd_vplane8",
2121 mrpcim_info.pci_depl_d_vplane[8].pci_depl_npd, "%u");
2122 __HAL_AUX_ENTRY("pci_depl_pd_vplane8",
2123 mrpcim_info.pci_depl_d_vplane[8].pci_depl_pd, "%u");
2124 __HAL_AUX_ENTRY("pci_depl_cpld_vplane9",
2125 mrpcim_info.pci_depl_d_vplane[9].pci_depl_cpld, "%u");
2126 __HAL_AUX_ENTRY("pci_depl_npd_vplane9",
2127 mrpcim_info.pci_depl_d_vplane[9].pci_depl_npd, "%u");
2128 __HAL_AUX_ENTRY("pci_depl_pd_vplane9",
2129 mrpcim_info.pci_depl_d_vplane[9].pci_depl_pd, "%u");
2130 __HAL_AUX_ENTRY("pci_depl_cpld_vplane10",
2131 mrpcim_info.pci_depl_d_vplane[10].pci_depl_cpld, "%u");
2132 __HAL_AUX_ENTRY("pci_depl_npd_vplane10",
2133 mrpcim_info.pci_depl_d_vplane[10].pci_depl_npd, "%u");
2134 __HAL_AUX_ENTRY("pci_depl_pd_vplane10",
2135 mrpcim_info.pci_depl_d_vplane[10].pci_depl_pd, "%u");
2136 __HAL_AUX_ENTRY("pci_depl_cpld_vplane11",
2137 mrpcim_info.pci_depl_d_vplane[11].pci_depl_cpld, "%u");
2138 __HAL_AUX_ENTRY("pci_depl_npd_vplane11",
2139 mrpcim_info.pci_depl_d_vplane[11].pci_depl_npd, "%u");
2140 __HAL_AUX_ENTRY("pci_depl_pd_vplane11",
2141 mrpcim_info.pci_depl_d_vplane[11].pci_depl_pd, "%u");
2142 __HAL_AUX_ENTRY("pci_depl_cpld_vplane12",
2143 mrpcim_info.pci_depl_d_vplane[12].pci_depl_cpld, "%u");
2144 __HAL_AUX_ENTRY("pci_depl_npd_vplane12",
2145 mrpcim_info.pci_depl_d_vplane[12].pci_depl_npd, "%u");
2146 __HAL_AUX_ENTRY("pci_depl_pd_vplane12",
2147 mrpcim_info.pci_depl_d_vplane[12].pci_depl_pd, "%u");
2148 __HAL_AUX_ENTRY("pci_depl_cpld_vplane13",
2149 mrpcim_info.pci_depl_d_vplane[13].pci_depl_cpld, "%u");
2150 __HAL_AUX_ENTRY("pci_depl_npd_vplane13",
2151 mrpcim_info.pci_depl_d_vplane[13].pci_depl_npd, "%u");
2152 __HAL_AUX_ENTRY("pci_depl_pd_vplane13",
2153 mrpcim_info.pci_depl_d_vplane[13].pci_depl_pd, "%u");
2154 __HAL_AUX_ENTRY("pci_depl_cpld_vplane14",
2155 mrpcim_info.pci_depl_d_vplane[14].pci_depl_cpld, "%u");
2156 __HAL_AUX_ENTRY("pci_depl_npd_vplane14",
2157 mrpcim_info.pci_depl_d_vplane[14].pci_depl_npd, "%u");
2158 __HAL_AUX_ENTRY("pci_depl_pd_vplane14",
2159 mrpcim_info.pci_depl_d_vplane[14].pci_depl_pd, "%u");
2160 __HAL_AUX_ENTRY("pci_depl_cpld_vplane15",
2161 mrpcim_info.pci_depl_d_vplane[15].pci_depl_cpld, "%u");
2162 __HAL_AUX_ENTRY("pci_depl_npd_vplane15",
2163 mrpcim_info.pci_depl_d_vplane[15].pci_depl_npd, "%u");
2164 __HAL_AUX_ENTRY("pci_depl_pd_vplane15",
2165 mrpcim_info.pci_depl_d_vplane[15].pci_depl_pd, "%u");
2166 __HAL_AUX_ENTRY("pci_depl_cpld_vplane16",
2167 mrpcim_info.pci_depl_d_vplane[16].pci_depl_cpld, "%u");
2168 __HAL_AUX_ENTRY("pci_depl_npd_vplane16",
2169 mrpcim_info.pci_depl_d_vplane[16].pci_depl_npd, "%u");
2170 __HAL_AUX_ENTRY("pci_depl_pd_vplane16",
2171 mrpcim_info.pci_depl_d_vplane[16].pci_depl_pd, "%u");
2172
2173 __HAL_AUX_ENTRY("tx_ttl_frms_PORT0",
2174 mrpcim_info.xgmac_port[0].tx_ttl_frms, "%llu");
2175 __HAL_AUX_ENTRY("tx_ttl_octets_PORT0",
2176 mrpcim_info.xgmac_port[0].tx_ttl_octets, "%llu");
2177 __HAL_AUX_ENTRY("tx_data_octets_PORT0",
2178 mrpcim_info.xgmac_port[0].tx_data_octets, "%llu");
2179 __HAL_AUX_ENTRY("tx_mcast_frms_PORT0",
2180 mrpcim_info.xgmac_port[0].tx_mcast_frms, "%llu");
2181 __HAL_AUX_ENTRY("tx_bcast_frms_PORT0",
2182 mrpcim_info.xgmac_port[0].tx_bcast_frms, "%llu");
2183 __HAL_AUX_ENTRY("tx_ucast_frms_PORT0",
2184 mrpcim_info.xgmac_port[0].tx_ucast_frms, "%llu");
2185 __HAL_AUX_ENTRY("tx_tagged_frms_PORT0",
2186 mrpcim_info.xgmac_port[0].tx_tagged_frms, "%llu");
2187 __HAL_AUX_ENTRY("tx_vld_ip_PORT0",
2188 mrpcim_info.xgmac_port[0].tx_vld_ip, "%llu");
2189 __HAL_AUX_ENTRY("tx_vld_ip_octets_PORT0",
2190 mrpcim_info.xgmac_port[0].tx_vld_ip_octets, "%llu");
2191 __HAL_AUX_ENTRY("tx_icmp_PORT0",
2192 mrpcim_info.xgmac_port[0].tx_icmp, "%llu");
2193 __HAL_AUX_ENTRY("tx_tcp_PORT0",
2194 mrpcim_info.xgmac_port[0].tx_tcp, "%llu");
2195 __HAL_AUX_ENTRY("tx_rst_tcp_PORT0",
2196 mrpcim_info.xgmac_port[0].tx_rst_tcp, "%llu");
2197 __HAL_AUX_ENTRY("tx_udp_PORT0",
2198 mrpcim_info.xgmac_port[0].tx_udp, "%llu");
2199 __HAL_AUX_ENTRY("tx_parse_error_PORT0",
2200 mrpcim_info.xgmac_port[0].tx_parse_error, "%u");
2201 __HAL_AUX_ENTRY("tx_unknown_protocol_PORT0",
2202 mrpcim_info.xgmac_port[0].tx_unknown_protocol, "%u");
2203 __HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT0",
2204 mrpcim_info.xgmac_port[0].tx_pause_ctrl_frms, "%llu");
2205 __HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT0",
2206 mrpcim_info.xgmac_port[0].tx_marker_pdu_frms, "%u");
2207 __HAL_AUX_ENTRY("tx_lacpdu_frms_PORT0",
2208 mrpcim_info.xgmac_port[0].tx_lacpdu_frms, "%u");
2209 __HAL_AUX_ENTRY("tx_drop_ip_PORT0",
2210 mrpcim_info.xgmac_port[0].tx_drop_ip, "%u");
2211 __HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT0",
2212 mrpcim_info.xgmac_port[0].tx_marker_resp_pdu_frms, "%u");
2213 __HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT0",
2214 mrpcim_info.xgmac_port[0].tx_xgmii_char2_match, "%u");
2215 __HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT0",
2216 mrpcim_info.xgmac_port[0].tx_xgmii_char1_match, "%u");
2217 __HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT0",
2218 mrpcim_info.xgmac_port[0].tx_xgmii_column2_match, "%u");
2219 __HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT0",
2220 mrpcim_info.xgmac_port[0].tx_xgmii_column1_match, "%u");
2221 __HAL_AUX_ENTRY("tx_any_err_frms_PORT0",
2222 mrpcim_info.xgmac_port[0].tx_any_err_frms, "%u");
2223 __HAL_AUX_ENTRY("tx_drop_frms_PORT0",
2224 mrpcim_info.xgmac_port[0].tx_drop_frms, "%u");
2225 __HAL_AUX_ENTRY("rx_ttl_frms_PORT0",
2226 mrpcim_info.xgmac_port[0].rx_ttl_frms, "%llu");
2227 __HAL_AUX_ENTRY("rx_vld_frms_PORT0",
2228 mrpcim_info.xgmac_port[0].rx_vld_frms, "%llu");
2229 __HAL_AUX_ENTRY("rx_offload_frms_PORT0",
2230 mrpcim_info.xgmac_port[0].rx_offload_frms, "%llu");
2231 __HAL_AUX_ENTRY("rx_ttl_octets_PORT0",
2232 mrpcim_info.xgmac_port[0].rx_ttl_octets, "%llu");
2233 __HAL_AUX_ENTRY("rx_data_octets_PORT0",
2234 mrpcim_info.xgmac_port[0].rx_data_octets, "%llu");
2235 __HAL_AUX_ENTRY("rx_offload_octets_PORT0",
2236 mrpcim_info.xgmac_port[0].rx_offload_octets, "%llu");
2237 __HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT0",
2238 mrpcim_info.xgmac_port[0].rx_vld_mcast_frms, "%llu");
2239 __HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT0",
2240 mrpcim_info.xgmac_port[0].rx_vld_bcast_frms, "%llu");
2241 __HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT0",
2242 mrpcim_info.xgmac_port[0].rx_accepted_ucast_frms, "%llu");
2243 __HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT0",
2244 mrpcim_info.xgmac_port[0].rx_accepted_nucast_frms, "%llu");
2245 __HAL_AUX_ENTRY("rx_tagged_frms_PORT0",
2246 mrpcim_info.xgmac_port[0].rx_tagged_frms, "%llu");
2247 __HAL_AUX_ENTRY("rx_long_frms_PORT0",
2248 mrpcim_info.xgmac_port[0].rx_long_frms, "%llu");
2249 __HAL_AUX_ENTRY("rx_usized_frms_PORT0",
2250 mrpcim_info.xgmac_port[0].rx_usized_frms, "%llu");
2251 __HAL_AUX_ENTRY("rx_osized_frms_PORT0",
2252 mrpcim_info.xgmac_port[0].rx_osized_frms, "%llu");
2253 __HAL_AUX_ENTRY("rx_frag_frms_PORT0",
2254 mrpcim_info.xgmac_port[0].rx_frag_frms, "%llu");
2255 __HAL_AUX_ENTRY("rx_jabber_frms_PORT0",
2256 mrpcim_info.xgmac_port[0].rx_jabber_frms, "%llu");
2257 __HAL_AUX_ENTRY("rx_ttl_64_frms_PORT0",
2258 mrpcim_info.xgmac_port[0].rx_ttl_64_frms, "%llu");
2259 __HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT0",
2260 mrpcim_info.xgmac_port[0].rx_ttl_65_127_frms, "%llu");
2261 __HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT0",
2262 mrpcim_info.xgmac_port[0].rx_ttl_128_255_frms, "%llu");
2263 __HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT0",
2264 mrpcim_info.xgmac_port[0].rx_ttl_256_511_frms, "%llu");
2265 __HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT0",
2266 mrpcim_info.xgmac_port[0].rx_ttl_512_1023_frms, "%llu");
2267 __HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT0",
2268 mrpcim_info.xgmac_port[0].rx_ttl_1024_1518_frms, "%llu");
2269 __HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT0",
2270 mrpcim_info.xgmac_port[0].rx_ttl_1519_4095_frms, "%llu");
2271 __HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT0",
2272 mrpcim_info.xgmac_port[0].rx_ttl_4096_8191_frms, "%llu");
2273 __HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT0",
2274 mrpcim_info.xgmac_port[0].rx_ttl_8192_max_frms, "%llu");
2275 __HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT0",
2276 mrpcim_info.xgmac_port[0].rx_ttl_gt_max_frms, "%llu");
2277 __HAL_AUX_ENTRY("rx_ip_PORT0",
2278 mrpcim_info.xgmac_port[0].rx_ip, "%llu");
2279 __HAL_AUX_ENTRY("rx_accepted_ip_PORT0",
2280 mrpcim_info.xgmac_port[0].rx_accepted_ip, "%llu");
2281 __HAL_AUX_ENTRY("rx_ip_octets_PORT0",
2282 mrpcim_info.xgmac_port[0].rx_ip_octets, "%llu");
2283 __HAL_AUX_ENTRY("rx_err_ip_PORT0",
2284 mrpcim_info.xgmac_port[0].rx_err_ip, "%llu");
2285 __HAL_AUX_ENTRY("rx_icmp_PORT0",
2286 mrpcim_info.xgmac_port[0].rx_icmp, "%llu");
2287 __HAL_AUX_ENTRY("rx_tcp_PORT0",
2288 mrpcim_info.xgmac_port[0].rx_tcp, "%llu");
2289 __HAL_AUX_ENTRY("rx_udp_PORT0",
2290 mrpcim_info.xgmac_port[0].rx_udp, "%llu");
2291 __HAL_AUX_ENTRY("rx_err_tcp_PORT0",
2292 mrpcim_info.xgmac_port[0].rx_err_tcp, "%llu");
2293 __HAL_AUX_ENTRY("rx_pause_cnt_PORT0",
2294 mrpcim_info.xgmac_port[0].rx_pause_count, "%llu");
2295 __HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT0",
2296 mrpcim_info.xgmac_port[0].rx_pause_ctrl_frms, "%llu");
2297 __HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT0",
2298 mrpcim_info.xgmac_port[0].rx_unsup_ctrl_frms, "%llu");
2299 __HAL_AUX_ENTRY("rx_fcs_err_frms_PORT0",
2300 mrpcim_info.xgmac_port[0].rx_fcs_err_frms, "%llu");
2301 __HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT0",
2302 mrpcim_info.xgmac_port[0].rx_in_rng_len_err_frms, "%llu");
2303 __HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT0",
2304 mrpcim_info.xgmac_port[0].rx_out_rng_len_err_frms, "%llu");
2305 __HAL_AUX_ENTRY("rx_drop_frms_PORT0",
2306 mrpcim_info.xgmac_port[0].rx_drop_frms, "%llu");
2307 __HAL_AUX_ENTRY("rx_discarded_frms_PORT0",
2308 mrpcim_info.xgmac_port[0].rx_discarded_frms, "%llu");
2309 __HAL_AUX_ENTRY("rx_drop_ip_PORT0",
2310 mrpcim_info.xgmac_port[0].rx_drop_ip, "%llu");
2311 __HAL_AUX_ENTRY("rx_drp_udp_PORT0",
2312 mrpcim_info.xgmac_port[0].rx_drop_udp, "%llu");
2313 __HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT0",
2314 mrpcim_info.xgmac_port[0].rx_marker_pdu_frms, "%u");
2315 __HAL_AUX_ENTRY("rx_lacpdu_frms_PORT0",
2316 mrpcim_info.xgmac_port[0].rx_lacpdu_frms, "%u");
2317 __HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT0",
2318 mrpcim_info.xgmac_port[0].rx_unknown_pdu_frms, "%u");
2319 __HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT0",
2320 mrpcim_info.xgmac_port[0].rx_marker_resp_pdu_frms, "%u");
2321 __HAL_AUX_ENTRY("rx_fcs_discard_PORT0",
2322 mrpcim_info.xgmac_port[0].rx_fcs_discard, "%u");
2323 __HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT0",
2324 mrpcim_info.xgmac_port[0].rx_illegal_pdu_frms, "%u");
2325 __HAL_AUX_ENTRY("rx_switch_discard_PORT0",
2326 mrpcim_info.xgmac_port[0].rx_switch_discard, "%u");
2327 __HAL_AUX_ENTRY("rx_len_discard_PORT0",
2328 mrpcim_info.xgmac_port[0].rx_len_discard, "%u");
2329 __HAL_AUX_ENTRY("rx_rpa_discard_PORT0",
2330 mrpcim_info.xgmac_port[0].rx_rpa_discard, "%u");
2331 __HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT0",
2332 mrpcim_info.xgmac_port[0].rx_l2_mgmt_discard, "%u");
2333 __HAL_AUX_ENTRY("rx_rts_discard_PORT0",
2334 mrpcim_info.xgmac_port[0].rx_rts_discard, "%u");
2335 __HAL_AUX_ENTRY("rx_trash_discard_PORT0",
2336 mrpcim_info.xgmac_port[0].rx_trash_discard, "%u");
2337 __HAL_AUX_ENTRY("rx_buff_full_discard_PORT0",
2338 mrpcim_info.xgmac_port[0].rx_buff_full_discard, "%u");
2339 __HAL_AUX_ENTRY("rx_red_discard_PORT0",
2340 mrpcim_info.xgmac_port[0].rx_red_discard, "%u");
2341 __HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT0",
2342 mrpcim_info.xgmac_port[0].rx_xgmii_ctrl_err_cnt, "%u");
2343 __HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT0",
2344 mrpcim_info.xgmac_port[0].rx_xgmii_data_err_cnt, "%u");
2345 __HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT0",
2346 mrpcim_info.xgmac_port[0].rx_xgmii_char1_match, "%u");
2347 __HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT0",
2348 mrpcim_info.xgmac_port[0].rx_xgmii_err_sym, "%u");
2349 __HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT0",
2350 mrpcim_info.xgmac_port[0].rx_xgmii_column1_match, "%u");
2351 __HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT0",
2352 mrpcim_info.xgmac_port[0].rx_xgmii_char2_match, "%u");
2353 __HAL_AUX_ENTRY("rx_local_fault_PORT0",
2354 mrpcim_info.xgmac_port[0].rx_local_fault, "%u");
2355 __HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT0",
2356 mrpcim_info.xgmac_port[0].rx_xgmii_column2_match, "%u");
2357 __HAL_AUX_ENTRY("rx_jettison_PORT0",
2358 mrpcim_info.xgmac_port[0].rx_jettison, "%u");
2359 __HAL_AUX_ENTRY("rx_remote_fault_PORT0",
2360 mrpcim_info.xgmac_port[0].rx_remote_fault, "%u");
2361
2362 __HAL_AUX_ENTRY("tx_ttl_frms_PORT1",
2363 mrpcim_info.xgmac_port[1].tx_ttl_frms, "%llu");
2364 __HAL_AUX_ENTRY("tx_ttl_octets_PORT1",
2365 mrpcim_info.xgmac_port[1].tx_ttl_octets, "%llu");
2366 __HAL_AUX_ENTRY("tx_data_octets_PORT1",
2367 mrpcim_info.xgmac_port[1].tx_data_octets, "%llu");
2368 __HAL_AUX_ENTRY("tx_mcast_frms_PORT1",
2369 mrpcim_info.xgmac_port[1].tx_mcast_frms, "%llu");
2370 __HAL_AUX_ENTRY("tx_bcast_frms_PORT1",
2371 mrpcim_info.xgmac_port[1].tx_bcast_frms, "%llu");
2372 __HAL_AUX_ENTRY("tx_ucast_frms_PORT1",
2373 mrpcim_info.xgmac_port[1].tx_ucast_frms, "%llu");
2374 __HAL_AUX_ENTRY("tx_tagged_frms_PORT1",
2375 mrpcim_info.xgmac_port[1].tx_tagged_frms, "%llu");
2376 __HAL_AUX_ENTRY("tx_vld_ip_PORT1",
2377 mrpcim_info.xgmac_port[1].tx_vld_ip, "%llu");
2378 __HAL_AUX_ENTRY("tx_vld_ip_octets_PORT1",
2379 mrpcim_info.xgmac_port[1].tx_vld_ip_octets, "%llu");
2380 __HAL_AUX_ENTRY("tx_icmp_PORT1",
2381 mrpcim_info.xgmac_port[1].tx_icmp, "%llu");
2382 __HAL_AUX_ENTRY("tx_tcp_PORT1",
2383 mrpcim_info.xgmac_port[1].tx_tcp, "%llu");
2384 __HAL_AUX_ENTRY("tx_rst_tcp_PORT1",
2385 mrpcim_info.xgmac_port[1].tx_rst_tcp, "%llu");
2386 __HAL_AUX_ENTRY("tx_udp_PORT1",
2387 mrpcim_info.xgmac_port[1].tx_udp, "%llu");
2388 __HAL_AUX_ENTRY("tx_parse_error_PORT1",
2389 mrpcim_info.xgmac_port[1].tx_parse_error, "%u");
2390 __HAL_AUX_ENTRY("tx_unknown_protocol_PORT1",
2391 mrpcim_info.xgmac_port[1].tx_unknown_protocol, "%u");
2392 __HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT1",
2393 mrpcim_info.xgmac_port[1].tx_pause_ctrl_frms, "%llu");
2394 __HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT1",
2395 mrpcim_info.xgmac_port[1].tx_marker_pdu_frms, "%u");
2396 __HAL_AUX_ENTRY("tx_lacpdu_frms_PORT1",
2397 mrpcim_info.xgmac_port[1].tx_lacpdu_frms, "%u");
2398 __HAL_AUX_ENTRY("tx_drop_ip_PORT1",
2399 mrpcim_info.xgmac_port[1].tx_drop_ip, "%u");
2400 __HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT1",
2401 mrpcim_info.xgmac_port[1].tx_marker_resp_pdu_frms, "%u");
2402 __HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT1",
2403 mrpcim_info.xgmac_port[1].tx_xgmii_char2_match, "%u");
2404 __HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT1",
2405 mrpcim_info.xgmac_port[1].tx_xgmii_char1_match, "%u");
2406 __HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT1",
2407 mrpcim_info.xgmac_port[1].tx_xgmii_column2_match, "%u");
2408 __HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT1",
2409 mrpcim_info.xgmac_port[1].tx_xgmii_column1_match, "%u");
2410 __HAL_AUX_ENTRY("tx_any_err_frms_PORT1",
2411 mrpcim_info.xgmac_port[1].tx_any_err_frms, "%u");
2412 __HAL_AUX_ENTRY("tx_drop_frms_PORT1",
2413 mrpcim_info.xgmac_port[1].tx_drop_frms, "%u");
2414 __HAL_AUX_ENTRY("rx_ttl_frms_PORT1",
2415 mrpcim_info.xgmac_port[1].rx_ttl_frms, "%llu");
2416 __HAL_AUX_ENTRY("rx_vld_frms_PORT1",
2417 mrpcim_info.xgmac_port[1].rx_vld_frms, "%llu");
2418 __HAL_AUX_ENTRY("rx_offload_frms_PORT1",
2419 mrpcim_info.xgmac_port[1].rx_offload_frms, "%llu");
2420 __HAL_AUX_ENTRY("rx_ttl_octets_PORT1",
2421 mrpcim_info.xgmac_port[1].rx_ttl_octets, "%llu");
2422 __HAL_AUX_ENTRY("rx_data_octets_PORT1",
2423 mrpcim_info.xgmac_port[1].rx_data_octets, "%llu");
2424 __HAL_AUX_ENTRY("rx_offload_octets_PORT1",
2425 mrpcim_info.xgmac_port[1].rx_offload_octets, "%llu");
2426 __HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT1",
2427 mrpcim_info.xgmac_port[1].rx_vld_mcast_frms, "%llu");
2428 __HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT1",
2429 mrpcim_info.xgmac_port[1].rx_vld_bcast_frms, "%llu");
2430 __HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT1",
2431 mrpcim_info.xgmac_port[1].rx_accepted_ucast_frms, "%llu");
2432 __HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT1",
2433 mrpcim_info.xgmac_port[1].rx_accepted_nucast_frms, "%llu");
2434 __HAL_AUX_ENTRY("rx_tagged_frms_PORT1",
2435 mrpcim_info.xgmac_port[1].rx_tagged_frms, "%llu");
2436 __HAL_AUX_ENTRY("rx_long_frms_PORT1",
2437 mrpcim_info.xgmac_port[1].rx_long_frms, "%llu");
2438 __HAL_AUX_ENTRY("rx_usized_frms_PORT1",
2439 mrpcim_info.xgmac_port[1].rx_usized_frms, "%llu");
2440 __HAL_AUX_ENTRY("rx_osized_frms_PORT1",
2441 mrpcim_info.xgmac_port[1].rx_osized_frms, "%llu");
2442 __HAL_AUX_ENTRY("rx_frag_frms_PORT1",
2443 mrpcim_info.xgmac_port[1].rx_frag_frms, "%llu");
2444 __HAL_AUX_ENTRY("rx_jabber_frms_PORT1",
2445 mrpcim_info.xgmac_port[1].rx_jabber_frms, "%llu");
2446 __HAL_AUX_ENTRY("rx_ttl_64_frms_PORT1",
2447 mrpcim_info.xgmac_port[1].rx_ttl_64_frms, "%llu");
2448 __HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT1",
2449 mrpcim_info.xgmac_port[1].rx_ttl_65_127_frms, "%llu");
2450 __HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT1",
2451 mrpcim_info.xgmac_port[1].rx_ttl_128_255_frms, "%llu");
2452 __HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT1",
2453 mrpcim_info.xgmac_port[1].rx_ttl_256_511_frms, "%llu");
2454 __HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT1",
2455 mrpcim_info.xgmac_port[1].rx_ttl_512_1023_frms, "%llu");
2456 __HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT1",
2457 mrpcim_info.xgmac_port[1].rx_ttl_1024_1518_frms, "%llu");
2458 __HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT1",
2459 mrpcim_info.xgmac_port[1].rx_ttl_1519_4095_frms, "%llu");
2460 __HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT1",
2461 mrpcim_info.xgmac_port[1].rx_ttl_4096_8191_frms, "%llu");
2462 __HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT1",
2463 mrpcim_info.xgmac_port[1].rx_ttl_8192_max_frms, "%llu");
2464 __HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT1",
2465 mrpcim_info.xgmac_port[1].rx_ttl_gt_max_frms, "%llu");
2466 __HAL_AUX_ENTRY("rx_ip_PORT1",
2467 mrpcim_info.xgmac_port[1].rx_ip, "%llu");
2468 __HAL_AUX_ENTRY("rx_accepted_ip_PORT1",
2469 mrpcim_info.xgmac_port[1].rx_accepted_ip, "%llu");
2470 __HAL_AUX_ENTRY("rx_ip_octets_PORT1",
2471 mrpcim_info.xgmac_port[1].rx_ip_octets, "%llu");
2472 __HAL_AUX_ENTRY("rx_err_ip_PORT1",
2473 mrpcim_info.xgmac_port[1].rx_err_ip, "%llu");
2474 __HAL_AUX_ENTRY("rx_icmp_PORT1",
2475 mrpcim_info.xgmac_port[1].rx_icmp, "%llu");
2476 __HAL_AUX_ENTRY("rx_tcp_PORT1",
2477 mrpcim_info.xgmac_port[1].rx_tcp, "%llu");
2478 __HAL_AUX_ENTRY("rx_udp_PORT1",
2479 mrpcim_info.xgmac_port[1].rx_udp, "%llu");
2480 __HAL_AUX_ENTRY("rx_err_tcp_PORT1",
2481 mrpcim_info.xgmac_port[1].rx_err_tcp, "%llu");
2482 __HAL_AUX_ENTRY("rx_pause_count_PORT1",
2483 mrpcim_info.xgmac_port[1].rx_pause_count, "%llu");
2484 __HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT1",
2485 mrpcim_info.xgmac_port[1].rx_pause_ctrl_frms, "%llu");
2486 __HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT1",
2487 mrpcim_info.xgmac_port[1].rx_unsup_ctrl_frms, "%llu");
2488 __HAL_AUX_ENTRY("rx_fcs_err_frms_PORT1",
2489 mrpcim_info.xgmac_port[1].rx_fcs_err_frms, "%llu");
2490 __HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT1",
2491 mrpcim_info.xgmac_port[1].rx_in_rng_len_err_frms, "%llu");
2492 __HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT1",
2493 mrpcim_info.xgmac_port[1].rx_out_rng_len_err_frms, "%llu");
2494 __HAL_AUX_ENTRY("rx_drop_frms_PORT1",
2495 mrpcim_info.xgmac_port[1].rx_drop_frms, "%llu");
2496 __HAL_AUX_ENTRY("rx_discarded_frms_PORT1",
2497 mrpcim_info.xgmac_port[1].rx_discarded_frms, "%llu");
2498 __HAL_AUX_ENTRY("rx_drop_ip_PORT1",
2499 mrpcim_info.xgmac_port[1].rx_drop_ip, "%llu");
2500 __HAL_AUX_ENTRY("rx_drop_udp_PORT1",
2501 mrpcim_info.xgmac_port[1].rx_drop_udp, "%llu");
2502 __HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT1",
2503 mrpcim_info.xgmac_port[1].rx_marker_pdu_frms, "%u");
2504 __HAL_AUX_ENTRY("rx_lacpdu_frms_PORT1",
2505 mrpcim_info.xgmac_port[1].rx_lacpdu_frms, "%u");
2506 __HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT1",
2507 mrpcim_info.xgmac_port[1].rx_unknown_pdu_frms, "%u");
2508 __HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT1",
2509 mrpcim_info.xgmac_port[1].rx_marker_resp_pdu_frms, "%u");
2510 __HAL_AUX_ENTRY("rx_fcs_discard_PORT1",
2511 mrpcim_info.xgmac_port[1].rx_fcs_discard, "%u");
2512 __HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT1",
2513 mrpcim_info.xgmac_port[1].rx_illegal_pdu_frms, "%u");
2514 __HAL_AUX_ENTRY("rx_switch_discard_PORT1",
2515 mrpcim_info.xgmac_port[1].rx_switch_discard, "%u");
2516 __HAL_AUX_ENTRY("rx_len_discard_PORT1",
2517 mrpcim_info.xgmac_port[1].rx_len_discard, "%u");
2518 __HAL_AUX_ENTRY("rx_rpa_discard_PORT1",
2519 mrpcim_info.xgmac_port[1].rx_rpa_discard, "%u");
2520 __HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT1",
2521 mrpcim_info.xgmac_port[1].rx_l2_mgmt_discard, "%u");
2522 __HAL_AUX_ENTRY("rx_rts_discard_PORT1",
2523 mrpcim_info.xgmac_port[1].rx_rts_discard, "%u");
2524 __HAL_AUX_ENTRY("rx_trash_discard_PORT1",
2525 mrpcim_info.xgmac_port[1].rx_trash_discard, "%u");
2526 __HAL_AUX_ENTRY("rx_buff_full_discard_PORT1",
2527 mrpcim_info.xgmac_port[1].rx_buff_full_discard, "%u");
2528 __HAL_AUX_ENTRY("rx_red_discard_PORT1",
2529 mrpcim_info.xgmac_port[1].rx_red_discard, "%u");
2530 __HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT1",
2531 mrpcim_info.xgmac_port[1].rx_xgmii_ctrl_err_cnt, "%u");
2532 __HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT1",
2533 mrpcim_info.xgmac_port[1].rx_xgmii_data_err_cnt, "%u");
2534 __HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT1",
2535 mrpcim_info.xgmac_port[1].rx_xgmii_char1_match, "%u");
2536 __HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT1",
2537 mrpcim_info.xgmac_port[1].rx_xgmii_err_sym, "%u");
2538 __HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT1",
2539 mrpcim_info.xgmac_port[1].rx_xgmii_column1_match, "%u");
2540 __HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT1",
2541 mrpcim_info.xgmac_port[1].rx_xgmii_char2_match, "%u");
2542 __HAL_AUX_ENTRY("rx_local_fault_PORT1",
2543 mrpcim_info.xgmac_port[1].rx_local_fault, "%u");
2544 __HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT1",
2545 mrpcim_info.xgmac_port[1].rx_xgmii_column2_match, "%u");
2546 __HAL_AUX_ENTRY("rx_jettison_PORT1",
2547 mrpcim_info.xgmac_port[1].rx_jettison, "%u");
2548 __HAL_AUX_ENTRY("rx_remote_fault_PORT1",
2549 mrpcim_info.xgmac_port[1].rx_remote_fault, "%u");
2550
2551 __HAL_AUX_ENTRY("tx_ttl_frms_PORT2",
2552 mrpcim_info.xgmac_port[2].tx_ttl_frms, "%llu");
2553 __HAL_AUX_ENTRY("tx_ttl_octets_PORT2",
2554 mrpcim_info.xgmac_port[2].tx_ttl_octets, "%llu");
2555 __HAL_AUX_ENTRY("tx_data_octets_PORT2",
2556 mrpcim_info.xgmac_port[2].tx_data_octets, "%llu");
2557 __HAL_AUX_ENTRY("tx_mcast_frms_PORT2",
2558 mrpcim_info.xgmac_port[2].tx_mcast_frms, "%llu");
2559 __HAL_AUX_ENTRY("tx_bcast_frms_PORT2",
2560 mrpcim_info.xgmac_port[2].tx_bcast_frms, "%llu");
2561 __HAL_AUX_ENTRY("tx_ucast_frms_PORT2",
2562 mrpcim_info.xgmac_port[2].tx_ucast_frms, "%llu");
2563 __HAL_AUX_ENTRY("tx_tagged_frms_PORT2",
2564 mrpcim_info.xgmac_port[2].tx_tagged_frms, "%llu");
2565 __HAL_AUX_ENTRY("tx_vld_ip_PORT2",
2566 mrpcim_info.xgmac_port[2].tx_vld_ip, "%llu");
2567 __HAL_AUX_ENTRY("tx_vld_ip_octets_PORT2",
2568 mrpcim_info.xgmac_port[2].tx_vld_ip_octets, "%llu");
2569 __HAL_AUX_ENTRY("tx_icmp_PORT2",
2570 mrpcim_info.xgmac_port[2].tx_icmp, "%llu");
2571 __HAL_AUX_ENTRY("tx_tcp_PORT2",
2572 mrpcim_info.xgmac_port[2].tx_tcp, "%llu");
2573 __HAL_AUX_ENTRY("tx_rst_tcp_PORT2",
2574 mrpcim_info.xgmac_port[2].tx_rst_tcp, "%llu");
2575 __HAL_AUX_ENTRY("tx_udp_PORT2",
2576 mrpcim_info.xgmac_port[2].tx_udp, "%llu");
2577 __HAL_AUX_ENTRY("tx_parse_error_PORT2",
2578 mrpcim_info.xgmac_port[2].tx_parse_error, "%u");
2579 __HAL_AUX_ENTRY("tx_unknown_protocol_PORT2",
2580 mrpcim_info.xgmac_port[2].tx_unknown_protocol, "%u");
2581 __HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT2",
2582 mrpcim_info.xgmac_port[2].tx_pause_ctrl_frms, "%llu");
2583 __HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT2",
2584 mrpcim_info.xgmac_port[2].tx_marker_pdu_frms, "%u");
2585 __HAL_AUX_ENTRY("tx_lacpdu_frms_PORT2",
2586 mrpcim_info.xgmac_port[2].tx_lacpdu_frms, "%u");
2587 __HAL_AUX_ENTRY("tx_drop_ip_PORT2",
2588 mrpcim_info.xgmac_port[2].tx_drop_ip, "%u");
2589 __HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT2",
2590 mrpcim_info.xgmac_port[2].tx_marker_resp_pdu_frms, "%u");
2591 __HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT2",
2592 mrpcim_info.xgmac_port[2].tx_xgmii_char2_match, "%u");
2593 __HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT2",
2594 mrpcim_info.xgmac_port[2].tx_xgmii_char1_match, "%u");
2595 __HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT2",
2596 mrpcim_info.xgmac_port[2].tx_xgmii_column2_match, "%u");
2597 __HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT2",
2598 mrpcim_info.xgmac_port[2].tx_xgmii_column1_match, "%u");
2599 __HAL_AUX_ENTRY("tx_any_err_frms_PORT2",
2600 mrpcim_info.xgmac_port[2].tx_any_err_frms, "%u");
2601 __HAL_AUX_ENTRY("tx_drop_frms_PORT2",
2602 mrpcim_info.xgmac_port[2].tx_drop_frms, "%u");
2603 __HAL_AUX_ENTRY("rx_ttl_frms_PORT2",
2604 mrpcim_info.xgmac_port[2].rx_ttl_frms, "%llu");
2605 __HAL_AUX_ENTRY("rx_vld_frms_PORT2",
2606 mrpcim_info.xgmac_port[2].rx_vld_frms, "%llu");
2607 __HAL_AUX_ENTRY("rx_offload_frms_PORT2",
2608 mrpcim_info.xgmac_port[2].rx_offload_frms, "%llu");
2609 __HAL_AUX_ENTRY("rx_ttl_octets_PORT2",
2610 mrpcim_info.xgmac_port[2].rx_ttl_octets, "%llu");
2611 __HAL_AUX_ENTRY("rx_data_octets_PORT2",
2612 mrpcim_info.xgmac_port[2].rx_data_octets, "%llu");
2613 __HAL_AUX_ENTRY("rx_offload_octets_PORT2",
2614 mrpcim_info.xgmac_port[2].rx_offload_octets, "%llu");
2615 __HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT2",
2616 mrpcim_info.xgmac_port[2].rx_vld_mcast_frms, "%llu");
2617 __HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT2",
2618 mrpcim_info.xgmac_port[2].rx_vld_bcast_frms, "%llu");
2619 __HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT2",
2620 mrpcim_info.xgmac_port[2].rx_accepted_ucast_frms, "%llu");
2621 __HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT2",
2622 mrpcim_info.xgmac_port[2].rx_accepted_nucast_frms, "%llu");
2623 __HAL_AUX_ENTRY("rx_tagged_frms_PORT2",
2624 mrpcim_info.xgmac_port[2].rx_tagged_frms, "%llu");
2625 __HAL_AUX_ENTRY("rx_long_frms_PORT2",
2626 mrpcim_info.xgmac_port[2].rx_long_frms, "%llu");
2627 __HAL_AUX_ENTRY("rx_usized_frms_PORT2",
2628 mrpcim_info.xgmac_port[2].rx_usized_frms, "%llu");
2629 __HAL_AUX_ENTRY("rx_osized_frms_PORT2",
2630 mrpcim_info.xgmac_port[2].rx_osized_frms, "%llu");
2631 __HAL_AUX_ENTRY("rx_frag_frms_PORT2",
2632 mrpcim_info.xgmac_port[2].rx_frag_frms, "%llu");
2633 __HAL_AUX_ENTRY("rx_jabber_frms_PORT2",
2634 mrpcim_info.xgmac_port[2].rx_jabber_frms, "%llu");
2635 __HAL_AUX_ENTRY("rx_ttl_64_frms_PORT2",
2636 mrpcim_info.xgmac_port[2].rx_ttl_64_frms, "%llu");
2637 __HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT2",
2638 mrpcim_info.xgmac_port[2].rx_ttl_65_127_frms, "%llu");
2639 __HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT2",
2640 mrpcim_info.xgmac_port[2].rx_ttl_128_255_frms, "%llu");
2641 __HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT2",
2642 mrpcim_info.xgmac_port[2].rx_ttl_256_511_frms, "%llu");
2643 __HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT2",
2644 mrpcim_info.xgmac_port[2].rx_ttl_512_1023_frms, "%llu");
2645 __HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT2",
2646 mrpcim_info.xgmac_port[2].rx_ttl_1024_1518_frms, "%llu");
2647 __HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT2",
2648 mrpcim_info.xgmac_port[2].rx_ttl_1519_4095_frms, "%llu");
2649 __HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT2",
2650 mrpcim_info.xgmac_port[2].rx_ttl_4096_8191_frms, "%llu");
2651 __HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT2",
2652 mrpcim_info.xgmac_port[2].rx_ttl_8192_max_frms, "%llu");
2653 __HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT2",
2654 mrpcim_info.xgmac_port[2].rx_ttl_gt_max_frms, "%llu");
2655 __HAL_AUX_ENTRY("rx_ip_PORT2",
2656 mrpcim_info.xgmac_port[2].rx_ip, "%llu");
2657 __HAL_AUX_ENTRY("rx_accepted_ip_PORT2",
2658 mrpcim_info.xgmac_port[2].rx_accepted_ip, "%llu");
2659 __HAL_AUX_ENTRY("rx_ip_octets_PORT2",
2660 mrpcim_info.xgmac_port[2].rx_ip_octets, "%llu");
2661 __HAL_AUX_ENTRY("rx_err_ip_PORT2",
2662 mrpcim_info.xgmac_port[2].rx_err_ip, "%llu");
2663 __HAL_AUX_ENTRY("rx_icmp_PORT2",
2664 mrpcim_info.xgmac_port[2].rx_icmp, "%llu");
2665 __HAL_AUX_ENTRY("rx_tcp_PORT2",
2666 mrpcim_info.xgmac_port[2].rx_tcp, "%llu");
2667 __HAL_AUX_ENTRY("rx_udp_PORT2",
2668 mrpcim_info.xgmac_port[2].rx_udp, "%llu");
2669 __HAL_AUX_ENTRY("rx_err_tcp_PORT2",
2670 mrpcim_info.xgmac_port[2].rx_err_tcp, "%llu");
2671 __HAL_AUX_ENTRY("rx_pause_count_PORT2",
2672 mrpcim_info.xgmac_port[2].rx_pause_count, "%llu");
2673 __HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT2",
2674 mrpcim_info.xgmac_port[2].rx_pause_ctrl_frms, "%llu");
2675 __HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT2",
2676 mrpcim_info.xgmac_port[2].rx_unsup_ctrl_frms, "%llu");
2677 __HAL_AUX_ENTRY("rx_fcs_err_frms_PORT2",
2678 mrpcim_info.xgmac_port[2].rx_fcs_err_frms, "%llu");
2679 __HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT2",
2680 mrpcim_info.xgmac_port[2].rx_in_rng_len_err_frms, "%llu");
2681 __HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT2",
2682 mrpcim_info.xgmac_port[2].rx_out_rng_len_err_frms, "%llu");
2683 __HAL_AUX_ENTRY("rx_drop_frms_PORT2",
2684 mrpcim_info.xgmac_port[2].rx_drop_frms, "%llu");
2685 __HAL_AUX_ENTRY("rx_discarded_frms_PORT2",
2686 mrpcim_info.xgmac_port[2].rx_discarded_frms, "%llu");
2687 __HAL_AUX_ENTRY("rx_drop_ip_PORT2",
2688 mrpcim_info.xgmac_port[2].rx_drop_ip, "%llu");
2689 __HAL_AUX_ENTRY("rx_drop_udp_PORT2",
2690 mrpcim_info.xgmac_port[2].rx_drop_udp, "%llu");
2691 __HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT2",
2692 mrpcim_info.xgmac_port[2].rx_marker_pdu_frms, "%u");
2693 __HAL_AUX_ENTRY("rx_lacpdu_frms_PORT2",
2694 mrpcim_info.xgmac_port[2].rx_lacpdu_frms, "%u");
2695 __HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT2",
2696 mrpcim_info.xgmac_port[2].rx_unknown_pdu_frms, "%u");
2697 __HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT2",
2698 mrpcim_info.xgmac_port[2].rx_marker_resp_pdu_frms, "%u");
2699 __HAL_AUX_ENTRY("rx_fcs_discard_PORT2",
2700 mrpcim_info.xgmac_port[2].rx_fcs_discard, "%u");
2701 __HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT2",
2702 mrpcim_info.xgmac_port[2].rx_illegal_pdu_frms, "%u");
2703 __HAL_AUX_ENTRY("rx_switch_discard_PORT2",
2704 mrpcim_info.xgmac_port[2].rx_switch_discard, "%u");
2705 __HAL_AUX_ENTRY("rx_len_discard_PORT2",
2706 mrpcim_info.xgmac_port[2].rx_len_discard, "%u");
2707 __HAL_AUX_ENTRY("rx_rpa_discard_PORT2",
2708 mrpcim_info.xgmac_port[2].rx_rpa_discard, "%u");
2709 __HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT2",
2710 mrpcim_info.xgmac_port[2].rx_l2_mgmt_discard, "%u");
2711 __HAL_AUX_ENTRY("rx_rts_discard_PORT2",
2712 mrpcim_info.xgmac_port[2].rx_rts_discard, "%u");
2713 __HAL_AUX_ENTRY("rx_trash_discard_PORT2",
2714 mrpcim_info.xgmac_port[2].rx_trash_discard, "%u");
2715 __HAL_AUX_ENTRY("rx_buff_full_discard_PORT2",
2716 mrpcim_info.xgmac_port[2].rx_buff_full_discard, "%u");
2717 __HAL_AUX_ENTRY("rx_red_discard_PORT2",
2718 mrpcim_info.xgmac_port[2].rx_red_discard, "%u");
2719 __HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT2",
2720 mrpcim_info.xgmac_port[2].rx_xgmii_ctrl_err_cnt, "%u");
2721 __HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT2",
2722 mrpcim_info.xgmac_port[2].rx_xgmii_data_err_cnt, "%u");
2723 __HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT2",
2724 mrpcim_info.xgmac_port[2].rx_xgmii_char1_match, "%u");
2725 __HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT2",
2726 mrpcim_info.xgmac_port[2].rx_xgmii_err_sym, "%u");
2727 __HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT2",
2728 mrpcim_info.xgmac_port[2].rx_xgmii_column1_match, "%u");
2729 __HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT2",
2730 mrpcim_info.xgmac_port[2].rx_xgmii_char2_match, "%u");
2731 __HAL_AUX_ENTRY("rx_local_fault_PORT2",
2732 mrpcim_info.xgmac_port[2].rx_local_fault, "%u");
2733 __HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT2",
2734 mrpcim_info.xgmac_port[2].rx_xgmii_column2_match, "%u");
2735 __HAL_AUX_ENTRY("rx_jettison_PORT2",
2736 mrpcim_info.xgmac_port[2].rx_jettison, "%u");
2737 __HAL_AUX_ENTRY("rx_remote_fault_PORT2",
2738 mrpcim_info.xgmac_port[2].rx_remote_fault, "%u");
2739
2740 __HAL_AUX_ENTRY("tx_frms_AGGR0",
2741 mrpcim_info.xgmac_aggr[0].tx_frms, "%llu");
2742 __HAL_AUX_ENTRY("tx_data_octets_AGGR0",
2743 mrpcim_info.xgmac_aggr[0].tx_data_octets, "%llu");
2744 __HAL_AUX_ENTRY("tx_mcast_frms_AGGR0",
2745 mrpcim_info.xgmac_aggr[0].tx_mcast_frms, "%llu");
2746 __HAL_AUX_ENTRY("tx_bcast_frms_AGGR0",
2747 mrpcim_info.xgmac_aggr[0].tx_bcast_frms, "%llu");
2748 __HAL_AUX_ENTRY("tx_discarded_frms_AGGR0",
2749 mrpcim_info.xgmac_aggr[0].tx_discarded_frms, "%llu");
2750 __HAL_AUX_ENTRY("tx_errored_frms_AGGR0",
2751 mrpcim_info.xgmac_aggr[0].tx_errored_frms, "%llu");
2752 __HAL_AUX_ENTRY("rx_frms_AGGR0",
2753 mrpcim_info.xgmac_aggr[0].rx_frms, "%llu");
2754 __HAL_AUX_ENTRY("rx_data_octets_AGGR0",
2755 mrpcim_info.xgmac_aggr[0].rx_data_octets, "%llu");
2756 __HAL_AUX_ENTRY("rx_mcast_frms_AGGR0",
2757 mrpcim_info.xgmac_aggr[0].rx_mcast_frms, "%llu");
2758 __HAL_AUX_ENTRY("rx_bcast_frms_AGGR0",
2759 mrpcim_info.xgmac_aggr[0].rx_bcast_frms, "%llu");
2760 __HAL_AUX_ENTRY("rx_discarded_frms_AGGR0",
2761 mrpcim_info.xgmac_aggr[0].rx_discarded_frms, "%llu");
2762 __HAL_AUX_ENTRY("rx_errored_frms_AGGR0",
2763 mrpcim_info.xgmac_aggr[0].rx_errored_frms, "%llu");
2764 __HAL_AUX_ENTRY("rx_unknown_slow_proto_frms_AGGR0",
2765 mrpcim_info.xgmac_aggr[0].rx_unknown_slow_proto_frms, "%llu");
2766
2767 __HAL_AUX_ENTRY("tx_frms_AGGR1",
2768 mrpcim_info.xgmac_aggr[1].tx_frms, "%llu");
2769 __HAL_AUX_ENTRY("tx_data_octets_AGGR1",
2770 mrpcim_info.xgmac_aggr[1].tx_data_octets, "%llu");
2771 __HAL_AUX_ENTRY("tx_mcast_frms_AGGR1",
2772 mrpcim_info.xgmac_aggr[1].tx_mcast_frms, "%llu");
2773 __HAL_AUX_ENTRY("tx_bcast_frms_AGGR1",
2774 mrpcim_info.xgmac_aggr[1].tx_bcast_frms, "%llu");
2775 __HAL_AUX_ENTRY("tx_discarded_frms_AGGR1",
2776 mrpcim_info.xgmac_aggr[1].tx_discarded_frms, "%llu");
2777 __HAL_AUX_ENTRY("tx_errored_frms_AGGR1",
2778 mrpcim_info.xgmac_aggr[1].tx_errored_frms, "%llu");
2779 __HAL_AUX_ENTRY("rx_frms_AGGR1",
2780 mrpcim_info.xgmac_aggr[1].rx_frms, "%llu");
2781 __HAL_AUX_ENTRY("rx_data_octets_AGGR1",
2782 mrpcim_info.xgmac_aggr[1].rx_data_octets, "%llu");
2783 __HAL_AUX_ENTRY("rx_mcast_frms_AGGR1",
2784 mrpcim_info.xgmac_aggr[1].rx_mcast_frms, "%llu");
2785 __HAL_AUX_ENTRY("rx_bcast_frms_AGGR1",
2786 mrpcim_info.xgmac_aggr[1].rx_bcast_frms, "%llu");
2787 __HAL_AUX_ENTRY("rx_discarded_frms_AGGR1",
2788 mrpcim_info.xgmac_aggr[1].rx_discarded_frms, "%llu");
2789 __HAL_AUX_ENTRY("rx_errored_frms_AGGR1",
2790 mrpcim_info.xgmac_aggr[1].rx_errored_frms, "%llu");
2791 __HAL_AUX_ENTRY("rx_unknown_slow_proto_frms_AGGR1",
2792 mrpcim_info.xgmac_aggr[1].rx_unknown_slow_proto_frms, "%llu");
2793
2794 __HAL_AUX_ENTRY("xgmac_global_prog_event_gnum0",
2795 mrpcim_info.xgmac_global_prog_event_gnum0, "%llu");
2796 __HAL_AUX_ENTRY("xgmac_global_prog_event_gnum1",
2797 mrpcim_info.xgmac_global_prog_event_gnum1, "%llu");
2798
2799 __HAL_AUX_ENTRY("xgmac_orp_lro_events",
2800 mrpcim_info.xgmac_orp_lro_events, "%llu");
2801
2802 __HAL_AUX_ENTRY("xgmac_orp_bs_events",
2803 mrpcim_info.xgmac_orp_bs_events, "%llu");
2804
2805 __HAL_AUX_ENTRY("xgmac_orp_iwarp_events",
2806 mrpcim_info.xgmac_orp_iwarp_events, "%llu");
2807
2808 __HAL_AUX_ENTRY("xgmac_tx_permitted_frms",
2809 mrpcim_info.xgmac_tx_permitted_frms, "%u");
2810
2811 __HAL_AUX_ENTRY("xgmac_port2_tx_any_frms",
2812 mrpcim_info.xgmac_port2_tx_any_frms, "%u");
2813 __HAL_AUX_ENTRY("xgmac_port1_tx_any_frms",
2814 mrpcim_info.xgmac_port1_tx_any_frms, "%u");
2815 __HAL_AUX_ENTRY("xgmac_port0_tx_any_frms",
2816 mrpcim_info.xgmac_port0_tx_any_frms, "%u");
2817
2818 __HAL_AUX_ENTRY("xgmac_port2_rx_any_frms",
2819 mrpcim_info.xgmac_port2_rx_any_frms, "%u");
2820 __HAL_AUX_ENTRY("xgmac_port1_rx_any_frms",
2821 mrpcim_info.xgmac_port1_rx_any_frms, "%u");
2822 __HAL_AUX_ENTRY("xgmac_port0_rx_any_frms",
2823 mrpcim_info.xgmac_port0_rx_any_frms, "%u");
2824
2825 __HAL_AUX_ENTRY_END(bufsize, retsize);
2826
2827 return (VXGE_HAL_OK);
2828 }
2829
2830 /*
2831 * vxge_hal_aux_vpath_ring_dump - Dump vpath ring.
2832 * @vpath_handle: Vpath handle.
2833 *
2834 * Dump vpath ring.
2835 */
2836 vxge_hal_status_e
vxge_hal_aux_vpath_ring_dump(vxge_hal_vpath_h vpath_handle)2837 vxge_hal_aux_vpath_ring_dump(vxge_hal_vpath_h vpath_handle)
2838 {
2839 u32 i;
2840 char buffer[4096];
2841 __hal_ring_t *ring;
2842 vxge_hal_rxd_h rxdh;
2843 __hal_virtualpath_t *vpath;
2844 vxge_hal_ring_rxd_1_t *rxd1;
2845 vxge_hal_ring_rxd_3_t *rxd3;
2846 vxge_hal_ring_rxd_5_t *rxd5;
2847
2848 vxge_assert(vpath_handle != NULL);
2849
2850 vpath = (__hal_virtualpath_t *)
2851 ((__hal_vpath_handle_t *) vpath_handle)->vpath;
2852
2853 ring = (__hal_ring_t *) vpath->ringh;
2854
2855 vxge_os_println("********* vxge RING DUMP BEGIN **********");
2856
2857 vxge_os_println("********* vxge RING RXD LIST **********");
2858
2859 __hal_channel_for_each_dtr(&ring->channel, rxdh, i) {
2860
2861 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2862 "%d : 0x"VXGE_OS_STXFMT, i, (ptr_t) rxdh);
2863
2864 vxge_os_println(buffer);
2865
2866 switch (ring->buffer_mode) {
2867 case 1:
2868 rxd1 = (vxge_hal_ring_rxd_1_t *) rxdh;
2869 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2870 "\thost_control = 0x"VXGE_OS_LLXFMT", "
2871 "control_0 = 0x"VXGE_OS_LLXFMT", "
2872 "control_1 = 0x"VXGE_OS_LLXFMT", "
2873 "buffer0_ptr = 0x"VXGE_OS_LLXFMT,
2874 rxd1->host_control, rxd1->control_0,
2875 rxd1->control_1, rxd1->buffer0_ptr);
2876 break;
2877 case 3:
2878 rxd3 = (vxge_hal_ring_rxd_3_t *) rxdh;
2879 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2880 "\thost_control = 0x"VXGE_OS_LLXFMT", "
2881 "control_0 = 0x"VXGE_OS_LLXFMT", "
2882 "control_1 = 0x"VXGE_OS_LLXFMT", "
2883 "buffer0_ptr = 0x"VXGE_OS_LLXFMT", "
2884 "buffer1_ptr = 0x"VXGE_OS_LLXFMT", "
2885 "buffer2_ptr = 0x"VXGE_OS_LLXFMT,
2886 rxd3->host_control, rxd3->control_0,
2887 rxd3->control_1, rxd3->buffer0_ptr,
2888 rxd3->buffer1_ptr, rxd3->buffer2_ptr);
2889 break;
2890 case 5:
2891 rxd5 = (vxge_hal_ring_rxd_5_t *) rxdh;
2892 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2893 "\thost_control = 0x%x, "
2894 "control_0 = 0x"VXGE_OS_LLXFMT", "
2895 "control_1 = 0x"VXGE_OS_LLXFMT", "
2896 "control_2 = 0x%x, "
2897 "buffer0_ptr = 0x"VXGE_OS_LLXFMT", "
2898 "buffer1_ptr = 0x"VXGE_OS_LLXFMT", "
2899 "buffer2_ptr = 0x"VXGE_OS_LLXFMT", "
2900 "buffer3_ptr = 0x"VXGE_OS_LLXFMT", "
2901 "buffer4_ptr = 0x"VXGE_OS_LLXFMT,
2902 rxd5->host_control, rxd5->control_0,
2903 rxd5->control_1, rxd5->control_2,
2904 rxd5->buffer0_ptr, rxd5->buffer1_ptr,
2905 rxd5->buffer2_ptr, rxd5->buffer3_ptr,
2906 rxd5->buffer4_ptr);
2907 break;
2908 default:
2909 continue;
2910 }
2911
2912 vxge_os_println(buffer);
2913 }
2914
2915 vxge_os_println("******* vxge RING RXD LIST END **********");
2916
2917 vxge_os_println("********* vxge RING DUMP END **********");
2918
2919 return (VXGE_HAL_OK);
2920 }
2921
2922 /*
2923 * vxge_hal_aux_vpath_fifo_dump - Dump vpath fifo.
2924 * @vpath_handle: Vpath handle.
2925 *
2926 * Dump vpath fifo.
2927 */
2928 vxge_hal_status_e
vxge_hal_aux_vpath_fifo_dump(vxge_hal_vpath_h vpath_handle)2929 vxge_hal_aux_vpath_fifo_dump(vxge_hal_vpath_h vpath_handle)
2930 {
2931 u32 i, j;
2932 char buffer[4096];
2933 __hal_fifo_t *fifo;
2934 vxge_hal_txdl_h txdlh;
2935 __hal_virtualpath_t *vpath;
2936 vxge_hal_fifo_txd_t *txd;
2937 __hal_fifo_txdl_priv_t *txdl_priv;
2938
2939 vxge_assert(vpath_handle != NULL);
2940
2941 vpath = (__hal_virtualpath_t *)
2942 ((__hal_vpath_handle_t *) vpath_handle)->vpath;
2943
2944 fifo = (__hal_fifo_t *) vpath->fifoh;
2945
2946 vxge_os_println("********* vxge FIFO DUMP BEGIN **********");
2947
2948 vxge_os_println("********* vxge FIFO TXDL LIST **********");
2949
2950 __hal_channel_for_each_dtr(&fifo->channel, txdlh, j) {
2951
2952 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2953 "TXDL %d : 0x"VXGE_OS_STXFMT, j, (ptr_t) txdlh);
2954
2955 vxge_os_println(buffer);
2956
2957 txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
2958
2959 for (i = 0, txd = (vxge_hal_fifo_txd_t *) txdlh;
2960 i < txdl_priv->frags; i++, txd++) {
2961
2962 (void) vxge_os_snprintf(buffer, sizeof(buffer),
2963 "\tcontrol_0 = 0x"VXGE_OS_LLXFMT", "
2964 "control_1 = 0x"VXGE_OS_LLXFMT", "
2965 "buffer_ptr = 0x"VXGE_OS_LLXFMT", "
2966 "host_control = 0x"VXGE_OS_LLXFMT,
2967 txd->control_0, txd->control_1,
2968 txd->buffer_pointer, txd->host_control);
2969
2970 vxge_os_println(buffer);
2971 }
2972
2973 }
2974
2975 vxge_os_println("******* vxge FIFO TXDL LIST END **********");
2976
2977 vxge_os_println("********* vxge FIFO DUMP END **********");
2978
2979 return (VXGE_HAL_OK);
2980 }
2981
2982 /*
2983 * vxge_hal_aux_device_dump - Dump driver "about" info and device state.
2984 * @devh: HAL device handle.
2985 *
2986 * Dump driver & device "about" info and device state,
2987 * including all BAR0 registers, hardware and software statistics, PCI
2988 * configuration space.
2989 */
2990 vxge_hal_status_e
vxge_hal_aux_device_dump(vxge_hal_device_h devh)2991 vxge_hal_aux_device_dump(vxge_hal_device_h devh)
2992 {
2993 vxge_hal_status_e status = VXGE_HAL_OK;
2994 __hal_device_t *hldev = (__hal_device_t *) devh;
2995 int retsize;
2996 u32 offset, i;
2997 u64 retval;
2998
2999 vxge_assert(hldev->dump_buf != NULL);
3000
3001 vxge_os_println("********* vxge DEVICE DUMP BEGIN **********");
3002
3003 status = vxge_hal_aux_about_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
3004 hldev->dump_buf, &retsize);
3005 if (status != VXGE_HAL_OK)
3006 goto error;
3007
3008 vxge_os_println(hldev->dump_buf);
3009
3010 vxge_os_println("******* PCI Config Reg **********");
3011
3012 status = vxge_hal_aux_pci_config_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
3013 hldev->dump_buf, &retsize);
3014 if (status != VXGE_HAL_OK)
3015 goto error;
3016
3017 vxge_os_println(hldev->dump_buf);
3018
3019 vxge_os_println("******* Legacy Reg **********");
3020
3021 for (offset = 0; offset < sizeof(vxge_hal_legacy_reg_t); offset += 8) {
3022 status = vxge_hal_mgmt_reg_read(devh,
3023 vxge_hal_mgmt_reg_type_legacy, 0, offset, &retval);
3024
3025 if (status != VXGE_HAL_OK)
3026 goto error;
3027
3028 if (!retval)
3029 continue;
3030
3031 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3032 (u32) (retval >> 32), (u32) retval);
3033 }
3034 vxge_os_println("\n");
3035
3036 vxge_os_println("******* TOC Reg *********");
3037
3038 for (offset = 0; offset < sizeof(vxge_hal_toc_reg_t); offset += 8) {
3039 status = vxge_hal_mgmt_reg_read(devh,
3040 vxge_hal_mgmt_reg_type_toc, 0, offset, &retval);
3041 if (status != VXGE_HAL_OK)
3042 goto error;
3043
3044 if (!retval)
3045 continue;
3046
3047 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3048 (u32) (retval >> 32), (u32) retval);
3049 }
3050 vxge_os_println("\n");
3051
3052 vxge_os_println("******* Common Reg **********");
3053
3054 for (offset = 0; offset < sizeof(vxge_hal_common_reg_t); offset += 8) {
3055 status = vxge_hal_mgmt_reg_read(devh,
3056 vxge_hal_mgmt_reg_type_common, 0, offset, &retval);
3057 if (status != VXGE_HAL_OK)
3058 goto error;
3059
3060 if (!retval)
3061 continue;
3062
3063 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3064 (u32) (retval >> 32), (u32) retval);
3065 }
3066 vxge_os_println("\n");
3067
3068 for (i = 0; i < VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES; i++) {
3069 vxge_os_printf("****** PCI Config Mgmt Reg : %d ********\n", i);
3070
3071 for (offset = 0; offset < sizeof(vxge_hal_pcicfgmgmt_reg_t);
3072 offset += 8) {
3073 status = vxge_hal_mgmt_reg_read(devh,
3074 vxge_hal_mgmt_reg_type_pcicfgmgmt,
3075 i, offset, &retval);
3076 if (status != VXGE_HAL_OK)
3077 continue;
3078
3079 if (!retval)
3080 continue;
3081
3082 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3083 (u32) (retval >> 32), (u32) retval);
3084 }
3085 }
3086 vxge_os_println("\n");
3087
3088 vxge_os_println("******* MRPCIM Reg **********");
3089
3090 for (offset = 0; offset < sizeof(vxge_hal_mrpcim_reg_t);
3091 offset += 8) {
3092 status = vxge_hal_mgmt_reg_read(devh,
3093 vxge_hal_mgmt_reg_type_mrpcim, 0, offset, &retval);
3094 if (status != VXGE_HAL_OK)
3095 continue;
3096
3097 if (!retval)
3098 continue;
3099
3100 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3101 (u32) (retval >> 32), (u32) retval);
3102 }
3103 vxge_os_println("\n");
3104
3105 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
3106 vxge_os_printf("******* SRPCIM Reg : %d **********\n", i);
3107
3108 for (offset = 0; offset < sizeof(vxge_hal_srpcim_reg_t);
3109 offset += 8) {
3110 status = vxge_hal_mgmt_reg_read(devh,
3111 vxge_hal_mgmt_reg_type_srpcim, i, offset, &retval);
3112 if (status != VXGE_HAL_OK)
3113 continue;
3114
3115 if (!retval)
3116 continue;
3117
3118 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3119 (u32) (retval >> 32), (u32) retval);
3120 }
3121 }
3122 vxge_os_println("\n");
3123
3124 for (i = 0; i < VXGE_HAL_TITAN_VPMGMT_REG_SPACES; i++) {
3125 vxge_os_printf("******* VPATH MGMT Reg : %d **********\n", i);
3126
3127 for (offset = 0; offset < sizeof(vxge_hal_vpmgmt_reg_t);
3128 offset += 8) {
3129 status = vxge_hal_mgmt_reg_read(devh,
3130 vxge_hal_mgmt_reg_type_vpmgmt, i, offset, &retval);
3131 if (status != VXGE_HAL_OK)
3132 continue;
3133
3134 if (!retval)
3135 continue;
3136
3137 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3138 (u32) (retval >> 32), (u32) retval);
3139 }
3140 }
3141 vxge_os_println("\n");
3142
3143 for (i = 0; i < VXGE_HAL_TITAN_VPATH_REG_SPACES; i++) {
3144 vxge_os_printf("******* VPATH Reg : %d **********\n", i);
3145
3146 for (offset = 0; offset < sizeof(vxge_hal_vpath_reg_t);
3147 offset += 8) {
3148 status = vxge_hal_mgmt_reg_read(devh,
3149 vxge_hal_mgmt_reg_type_vpath, i, offset, &retval);
3150 if (status != VXGE_HAL_OK)
3151 continue;
3152
3153 if (!retval)
3154 continue;
3155
3156 vxge_os_printf("0x%04x 0x%08x%08x", offset,
3157 (u32) (retval >> 32), (u32) retval);
3158 }
3159 }
3160
3161 vxge_os_println("\n");
3162
3163 status = vxge_hal_aux_stats_mrpcim_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
3164 hldev->dump_buf,
3165 &retsize);
3166 if (status == VXGE_HAL_OK) {
3167 vxge_os_println("******* MRPCIM Stats **********");
3168 vxge_os_println(hldev->dump_buf);
3169 }
3170
3171 vxge_os_println("******* Device Stats **********");
3172
3173 status = vxge_hal_aux_stats_device_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
3174 hldev->dump_buf, &retsize);
3175 if (status != VXGE_HAL_OK)
3176 goto error;
3177
3178 vxge_os_println(hldev->dump_buf);
3179
3180 vxge_os_println("********* DEVICE DUMP END **********");
3181
3182 error:
3183 return (status);
3184 }
3185