1 /* $FreeBSD$ */
2 /*-
3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
4 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
5 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
6 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
32 *
33 * The EHCI 0.96 spec can be found at
34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
35 * The EHCI 1.0 spec can be found at
36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
37 * and the USB 2.0 spec at
38 * http://www.usb.org/developers/docs/usb_20.zip
39 *
40 */
41
42 /*
43 * TODO:
44 * 1) command failures are not recovered correctly
45 */
46
47 #ifdef USB_GLOBAL_INCLUDE_FILE
48 #include USB_GLOBAL_INCLUDE_FILE
49 #else
50 #include <sys/stdint.h>
51 #include <sys/stddef.h>
52 #include <sys/param.h>
53 #include <sys/queue.h>
54 #include <sys/types.h>
55 #include <sys/systm.h>
56 #include <sys/kernel.h>
57 #include <sys/bus.h>
58 #include <sys/module.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/condvar.h>
62 #include <sys/sysctl.h>
63 #include <sys/sx.h>
64 #include <sys/unistd.h>
65 #include <sys/callout.h>
66 #include <sys/malloc.h>
67 #include <sys/priv.h>
68
69 #include <dev/usb/usb.h>
70 #include <dev/usb/usbdi.h>
71
72 #define USB_DEBUG_VAR ehcidebug
73
74 #include <dev/usb/usb_core.h>
75 #include <dev/usb/usb_debug.h>
76 #include <dev/usb/usb_busdma.h>
77 #include <dev/usb/usb_process.h>
78 #include <dev/usb/usb_transfer.h>
79 #include <dev/usb/usb_device.h>
80 #include <dev/usb/usb_hub.h>
81 #include <dev/usb/usb_util.h>
82
83 #include <dev/usb/usb_controller.h>
84 #include <dev/usb/usb_bus.h>
85 #endif /* USB_GLOBAL_INCLUDE_FILE */
86
87 #include <dev/usb/controller/ehci.h>
88 #include <dev/usb/controller/ehcireg.h>
89
90 #define EHCI_BUS2SC(bus) \
91 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
92 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
93
94 #ifdef USB_DEBUG
95 static int ehcidebug = 0;
96 static int ehcinohighspeed = 0;
97 static int ehciiaadbug = 0;
98 static int ehcilostintrbug = 0;
99
100 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
102 &ehcidebug, 0, "Debug level");
103 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW | CTLFLAG_TUN,
105 &ehcinohighspeed, 0, "Disable High Speed USB");
106 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW | CTLFLAG_TUN,
108 &ehciiaadbug, 0, "Enable doorbell bug workaround");
109 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
110 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW | CTLFLAG_TUN,
111 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
112 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
113
114
115 static void ehci_dump_regs(ehci_softc_t *sc);
116 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
117
118 #endif
119
120 #define EHCI_INTR_ENDPT 1
121
122 extern struct usb_bus_methods ehci_bus_methods;
123 extern struct usb_pipe_methods ehci_device_bulk_methods;
124 extern struct usb_pipe_methods ehci_device_ctrl_methods;
125 extern struct usb_pipe_methods ehci_device_intr_methods;
126 extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
127 extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
128
129 static void ehci_do_poll(struct usb_bus *);
130 static void ehci_device_done(struct usb_xfer *, usb_error_t);
131 static uint8_t ehci_check_transfer(struct usb_xfer *);
132 static void ehci_timeout(void *);
133 static void ehci_poll_timeout(void *);
134
135 static void ehci_root_intr(ehci_softc_t *sc);
136
137 struct ehci_std_temp {
138 ehci_softc_t *sc;
139 struct usb_page_cache *pc;
140 ehci_qtd_t *td;
141 ehci_qtd_t *td_next;
142 uint32_t average;
143 uint32_t qtd_status;
144 uint32_t len;
145 uint16_t max_frame_size;
146 uint8_t shortpkt;
147 uint8_t auto_data_toggle;
148 uint8_t setup_alt_next;
149 uint8_t last_frame;
150 };
151
152 void
ehci_iterate_hw_softc(struct usb_bus * bus,usb_bus_mem_sub_cb_t * cb)153 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
154 {
155 ehci_softc_t *sc = EHCI_BUS2SC(bus);
156 uint32_t i;
157
158 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
159 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
160
161 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
162 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
163
164 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
165 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
166
167 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
168 cb(bus, sc->sc_hw.intr_start_pc + i,
169 sc->sc_hw.intr_start_pg + i,
170 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
171 }
172
173 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
174 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
175 sc->sc_hw.isoc_hs_start_pg + i,
176 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
177 }
178
179 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
180 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
181 sc->sc_hw.isoc_fs_start_pg + i,
182 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
183 }
184 }
185
186 usb_error_t
ehci_reset(ehci_softc_t * sc)187 ehci_reset(ehci_softc_t *sc)
188 {
189 uint32_t hcr;
190 int i;
191
192 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
193 for (i = 0; i < 100; i++) {
194 usb_pause_mtx(NULL, hz / 128);
195 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
196 if (!hcr) {
197 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
198 /*
199 * Force USBMODE as requested. Controllers
200 * may have multiple operating modes.
201 */
202 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
203 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
204 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
205 device_printf(sc->sc_bus.bdev,
206 "set host controller mode\n");
207 }
208 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
209 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
210 device_printf(sc->sc_bus.bdev,
211 "set big-endian mode\n");
212 }
213 EOWRITE4(sc, EHCI_USBMODE, usbmode);
214 }
215 return (0);
216 }
217 }
218 device_printf(sc->sc_bus.bdev, "reset timeout\n");
219 return (USB_ERR_IOERROR);
220 }
221
222 static usb_error_t
ehci_hcreset(ehci_softc_t * sc)223 ehci_hcreset(ehci_softc_t *sc)
224 {
225 uint32_t hcr;
226 int i;
227
228 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
229 for (i = 0; i < 100; i++) {
230 usb_pause_mtx(NULL, hz / 128);
231 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
232 if (hcr)
233 break;
234 }
235 if (!hcr)
236 /*
237 * Fall through and try reset anyway even though
238 * Table 2-9 in the EHCI spec says this will result
239 * in undefined behavior.
240 */
241 device_printf(sc->sc_bus.bdev, "stop timeout\n");
242
243 return (ehci_reset(sc));
244 }
245
246 static int
ehci_init_sub(struct ehci_softc * sc)247 ehci_init_sub(struct ehci_softc *sc)
248 {
249 struct usb_page_search buf_res;
250 uint32_t cparams;
251 uint32_t hcr;
252 uint8_t i;
253
254 cparams = EREAD4(sc, EHCI_HCCPARAMS);
255
256 DPRINTF("cparams=0x%x\n", cparams);
257
258 if (EHCI_HCC_64BIT(cparams)) {
259 DPRINTF("HCC uses 64-bit structures\n");
260
261 /* MUST clear segment register if 64 bit capable */
262 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
263 }
264
265 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
266 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
267
268 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
269 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
270
271 /* enable interrupts */
272 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
273
274 /* turn on controller */
275 EOWRITE4(sc, EHCI_USBCMD,
276 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
277 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
278 EHCI_CMD_ASE |
279 EHCI_CMD_PSE |
280 EHCI_CMD_RS);
281
282 /* Take over port ownership */
283 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
284
285 for (i = 0; i < 100; i++) {
286 usb_pause_mtx(NULL, hz / 128);
287 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
288 if (!hcr) {
289 break;
290 }
291 }
292 if (hcr) {
293 device_printf(sc->sc_bus.bdev, "run timeout\n");
294 return (USB_ERR_IOERROR);
295 }
296 return (USB_ERR_NORMAL_COMPLETION);
297 }
298
299 usb_error_t
ehci_init(ehci_softc_t * sc)300 ehci_init(ehci_softc_t *sc)
301 {
302 struct usb_page_search buf_res;
303 uint32_t version;
304 uint32_t sparams;
305 uint16_t i;
306 uint16_t x;
307 uint16_t y;
308 uint16_t bit;
309 usb_error_t err = 0;
310
311 DPRINTF("start\n");
312
313 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
314 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
315
316 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
317
318 #ifdef USB_DEBUG
319 if (ehciiaadbug)
320 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
321 if (ehcilostintrbug)
322 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
323 if (ehcidebug > 2) {
324 ehci_dump_regs(sc);
325 }
326 #endif
327
328 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
329 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
330 version >> 8, version & 0xff);
331
332 sparams = EREAD4(sc, EHCI_HCSPARAMS);
333 DPRINTF("sparams=0x%x\n", sparams);
334
335 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
336 sc->sc_bus.usbrev = USB_REV_2_0;
337
338 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
339 /* Reset the controller */
340 DPRINTF("%s: resetting\n",
341 device_get_nameunit(sc->sc_bus.bdev));
342
343 err = ehci_hcreset(sc);
344 if (err) {
345 device_printf(sc->sc_bus.bdev, "reset timeout\n");
346 return (err);
347 }
348 }
349
350 /*
351 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
352 * bytes 2: 256*4 bytes 3: unknown
353 */
354 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
355 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
356 return (USB_ERR_IOERROR);
357 }
358 /* set up the bus struct */
359 sc->sc_bus.methods = &ehci_bus_methods;
360
361 sc->sc_eintrs = EHCI_NORMAL_INTRS;
362
363 if (1) {
364 struct ehci_qh_sub *qh;
365
366 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
367
368 qh = buf_res.buffer;
369
370 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
371
372 /* init terminate TD */
373 qh->qtd_next =
374 htohc32(sc, EHCI_LINK_TERMINATE);
375 qh->qtd_altnext =
376 htohc32(sc, EHCI_LINK_TERMINATE);
377 qh->qtd_status =
378 htohc32(sc, EHCI_QTD_HALTED);
379 }
380
381 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
382 ehci_qh_t *qh;
383
384 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
385
386 qh = buf_res.buffer;
387
388 /* initialize page cache pointer */
389
390 qh->page_cache = sc->sc_hw.intr_start_pc + i;
391
392 /* store a pointer to queue head */
393
394 sc->sc_intr_p_last[i] = qh;
395
396 qh->qh_self =
397 htohc32(sc, buf_res.physaddr) |
398 htohc32(sc, EHCI_LINK_QH);
399
400 qh->qh_endp =
401 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
402 qh->qh_endphub =
403 htohc32(sc, EHCI_QH_SET_MULT(1));
404 qh->qh_curqtd = 0;
405
406 qh->qh_qtd.qtd_next =
407 htohc32(sc, EHCI_LINK_TERMINATE);
408 qh->qh_qtd.qtd_altnext =
409 htohc32(sc, EHCI_LINK_TERMINATE);
410 qh->qh_qtd.qtd_status =
411 htohc32(sc, EHCI_QTD_HALTED);
412 }
413
414 /*
415 * the QHs are arranged to give poll intervals that are
416 * powers of 2 times 1ms
417 */
418 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
419 while (bit) {
420 x = bit;
421 while (x & bit) {
422 ehci_qh_t *qh_x;
423 ehci_qh_t *qh_y;
424
425 y = (x ^ bit) | (bit / 2);
426
427 qh_x = sc->sc_intr_p_last[x];
428 qh_y = sc->sc_intr_p_last[y];
429
430 /*
431 * the next QH has half the poll interval
432 */
433 qh_x->qh_link = qh_y->qh_self;
434
435 x++;
436 }
437 bit >>= 1;
438 }
439
440 if (1) {
441 ehci_qh_t *qh;
442
443 qh = sc->sc_intr_p_last[0];
444
445 /* the last (1ms) QH terminates */
446 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
447 }
448 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
449 ehci_sitd_t *sitd;
450 ehci_itd_t *itd;
451
452 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
453
454 sitd = buf_res.buffer;
455
456 /* initialize page cache pointer */
457
458 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
459
460 /* store a pointer to the transfer descriptor */
461
462 sc->sc_isoc_fs_p_last[i] = sitd;
463
464 /* initialize full speed isochronous */
465
466 sitd->sitd_self =
467 htohc32(sc, buf_res.physaddr) |
468 htohc32(sc, EHCI_LINK_SITD);
469
470 sitd->sitd_back =
471 htohc32(sc, EHCI_LINK_TERMINATE);
472
473 sitd->sitd_next =
474 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
475
476
477 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
478
479 itd = buf_res.buffer;
480
481 /* initialize page cache pointer */
482
483 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
484
485 /* store a pointer to the transfer descriptor */
486
487 sc->sc_isoc_hs_p_last[i] = itd;
488
489 /* initialize high speed isochronous */
490
491 itd->itd_self =
492 htohc32(sc, buf_res.physaddr) |
493 htohc32(sc, EHCI_LINK_ITD);
494
495 itd->itd_next =
496 sitd->sitd_self;
497 }
498
499 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
500
501 if (1) {
502 uint32_t *pframes;
503
504 pframes = buf_res.buffer;
505
506 /*
507 * execution order:
508 * pframes -> high speed isochronous ->
509 * full speed isochronous -> interrupt QH's
510 */
511 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
512 pframes[i] = sc->sc_isoc_hs_p_last
513 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
514 }
515 }
516 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
517
518 if (1) {
519
520 ehci_qh_t *qh;
521
522 qh = buf_res.buffer;
523
524 /* initialize page cache pointer */
525
526 qh->page_cache = &sc->sc_hw.async_start_pc;
527
528 /* store a pointer to the queue head */
529
530 sc->sc_async_p_last = qh;
531
532 /* init dummy QH that starts the async list */
533
534 qh->qh_self =
535 htohc32(sc, buf_res.physaddr) |
536 htohc32(sc, EHCI_LINK_QH);
537
538 /* fill the QH */
539 qh->qh_endp =
540 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
541 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
542 qh->qh_link = qh->qh_self;
543 qh->qh_curqtd = 0;
544
545 /* fill the overlay qTD */
546 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
547 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
548 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
549 }
550 /* flush all cache into memory */
551
552 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
553
554 #ifdef USB_DEBUG
555 if (ehcidebug) {
556 ehci_dump_sqh(sc, sc->sc_async_p_last);
557 }
558 #endif
559
560 /* finial setup */
561 err = ehci_init_sub(sc);
562
563 if (!err) {
564 /* catch any lost interrupts */
565 ehci_do_poll(&sc->sc_bus);
566 }
567 return (err);
568 }
569
570 /*
571 * shut down the controller when the system is going down
572 */
573 void
ehci_detach(ehci_softc_t * sc)574 ehci_detach(ehci_softc_t *sc)
575 {
576 USB_BUS_LOCK(&sc->sc_bus);
577
578 usb_callout_stop(&sc->sc_tmo_pcd);
579 usb_callout_stop(&sc->sc_tmo_poll);
580
581 EOWRITE4(sc, EHCI_USBINTR, 0);
582 USB_BUS_UNLOCK(&sc->sc_bus);
583
584 if (ehci_hcreset(sc)) {
585 DPRINTF("reset failed!\n");
586 }
587
588 /* XXX let stray task complete */
589 usb_pause_mtx(NULL, hz / 20);
590
591 usb_callout_drain(&sc->sc_tmo_pcd);
592 usb_callout_drain(&sc->sc_tmo_poll);
593 }
594
595 static void
ehci_suspend(ehci_softc_t * sc)596 ehci_suspend(ehci_softc_t *sc)
597 {
598 DPRINTF("stopping the HC\n");
599
600 /* reset HC */
601 ehci_hcreset(sc);
602 }
603
604 static void
ehci_resume(ehci_softc_t * sc)605 ehci_resume(ehci_softc_t *sc)
606 {
607 /* reset HC */
608 ehci_hcreset(sc);
609
610 /* setup HC */
611 ehci_init_sub(sc);
612
613 /* catch any lost interrupts */
614 ehci_do_poll(&sc->sc_bus);
615 }
616
617 #ifdef USB_DEBUG
618 static void
ehci_dump_regs(ehci_softc_t * sc)619 ehci_dump_regs(ehci_softc_t *sc)
620 {
621 uint32_t i;
622
623 i = EOREAD4(sc, EHCI_USBCMD);
624 printf("cmd=0x%08x\n", i);
625
626 if (i & EHCI_CMD_ITC_1)
627 printf(" EHCI_CMD_ITC_1\n");
628 if (i & EHCI_CMD_ITC_2)
629 printf(" EHCI_CMD_ITC_2\n");
630 if (i & EHCI_CMD_ITC_4)
631 printf(" EHCI_CMD_ITC_4\n");
632 if (i & EHCI_CMD_ITC_8)
633 printf(" EHCI_CMD_ITC_8\n");
634 if (i & EHCI_CMD_ITC_16)
635 printf(" EHCI_CMD_ITC_16\n");
636 if (i & EHCI_CMD_ITC_32)
637 printf(" EHCI_CMD_ITC_32\n");
638 if (i & EHCI_CMD_ITC_64)
639 printf(" EHCI_CMD_ITC_64\n");
640 if (i & EHCI_CMD_ASPME)
641 printf(" EHCI_CMD_ASPME\n");
642 if (i & EHCI_CMD_ASPMC)
643 printf(" EHCI_CMD_ASPMC\n");
644 if (i & EHCI_CMD_LHCR)
645 printf(" EHCI_CMD_LHCR\n");
646 if (i & EHCI_CMD_IAAD)
647 printf(" EHCI_CMD_IAAD\n");
648 if (i & EHCI_CMD_ASE)
649 printf(" EHCI_CMD_ASE\n");
650 if (i & EHCI_CMD_PSE)
651 printf(" EHCI_CMD_PSE\n");
652 if (i & EHCI_CMD_FLS_M)
653 printf(" EHCI_CMD_FLS_M\n");
654 if (i & EHCI_CMD_HCRESET)
655 printf(" EHCI_CMD_HCRESET\n");
656 if (i & EHCI_CMD_RS)
657 printf(" EHCI_CMD_RS\n");
658
659 i = EOREAD4(sc, EHCI_USBSTS);
660
661 printf("sts=0x%08x\n", i);
662
663 if (i & EHCI_STS_ASS)
664 printf(" EHCI_STS_ASS\n");
665 if (i & EHCI_STS_PSS)
666 printf(" EHCI_STS_PSS\n");
667 if (i & EHCI_STS_REC)
668 printf(" EHCI_STS_REC\n");
669 if (i & EHCI_STS_HCH)
670 printf(" EHCI_STS_HCH\n");
671 if (i & EHCI_STS_IAA)
672 printf(" EHCI_STS_IAA\n");
673 if (i & EHCI_STS_HSE)
674 printf(" EHCI_STS_HSE\n");
675 if (i & EHCI_STS_FLR)
676 printf(" EHCI_STS_FLR\n");
677 if (i & EHCI_STS_PCD)
678 printf(" EHCI_STS_PCD\n");
679 if (i & EHCI_STS_ERRINT)
680 printf(" EHCI_STS_ERRINT\n");
681 if (i & EHCI_STS_INT)
682 printf(" EHCI_STS_INT\n");
683
684 printf("ien=0x%08x\n",
685 EOREAD4(sc, EHCI_USBINTR));
686 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
687 EOREAD4(sc, EHCI_FRINDEX),
688 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
689 EOREAD4(sc, EHCI_PERIODICLISTBASE),
690 EOREAD4(sc, EHCI_ASYNCLISTADDR));
691 for (i = 1; i <= sc->sc_noport; i++) {
692 printf("port %d status=0x%08x\n", i,
693 EOREAD4(sc, EHCI_PORTSC(i)));
694 }
695 }
696
697 static void
ehci_dump_link(ehci_softc_t * sc,uint32_t link,int type)698 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
699 {
700 link = hc32toh(sc, link);
701 printf("0x%08x", link);
702 if (link & EHCI_LINK_TERMINATE)
703 printf("<T>");
704 else {
705 printf("<");
706 if (type) {
707 switch (EHCI_LINK_TYPE(link)) {
708 case EHCI_LINK_ITD:
709 printf("ITD");
710 break;
711 case EHCI_LINK_QH:
712 printf("QH");
713 break;
714 case EHCI_LINK_SITD:
715 printf("SITD");
716 break;
717 case EHCI_LINK_FSTN:
718 printf("FSTN");
719 break;
720 }
721 }
722 printf(">");
723 }
724 }
725
726 static void
ehci_dump_qtd(ehci_softc_t * sc,ehci_qtd_t * qtd)727 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
728 {
729 uint32_t s;
730
731 printf(" next=");
732 ehci_dump_link(sc, qtd->qtd_next, 0);
733 printf(" altnext=");
734 ehci_dump_link(sc, qtd->qtd_altnext, 0);
735 printf("\n");
736 s = hc32toh(sc, qtd->qtd_status);
737 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
738 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
739 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
740 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
741 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
742 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
743 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
744 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
745 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
746 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
747 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
748 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
749 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
750
751 for (s = 0; s < 5; s++) {
752 printf(" buffer[%d]=0x%08x\n", s,
753 hc32toh(sc, qtd->qtd_buffer[s]));
754 }
755 for (s = 0; s < 5; s++) {
756 printf(" buffer_hi[%d]=0x%08x\n", s,
757 hc32toh(sc, qtd->qtd_buffer_hi[s]));
758 }
759 }
760
761 static uint8_t
ehci_dump_sqtd(ehci_softc_t * sc,ehci_qtd_t * sqtd)762 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
763 {
764 uint8_t temp;
765
766 usb_pc_cpu_invalidate(sqtd->page_cache);
767 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
768 ehci_dump_qtd(sc, sqtd);
769 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
770 return (temp);
771 }
772
773 static void
ehci_dump_sqtds(ehci_softc_t * sc,ehci_qtd_t * sqtd)774 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
775 {
776 uint16_t i;
777 uint8_t stop;
778
779 stop = 0;
780 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
781 stop = ehci_dump_sqtd(sc, sqtd);
782 }
783 if (sqtd) {
784 printf("dump aborted, too many TDs\n");
785 }
786 }
787
788 static void
ehci_dump_sqh(ehci_softc_t * sc,ehci_qh_t * qh)789 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
790 {
791 uint32_t endp;
792 uint32_t endphub;
793
794 usb_pc_cpu_invalidate(qh->page_cache);
795 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
796 printf(" link=");
797 ehci_dump_link(sc, qh->qh_link, 1);
798 printf("\n");
799 endp = hc32toh(sc, qh->qh_endp);
800 printf(" endp=0x%08x\n", endp);
801 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
802 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
803 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
804 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
805 printf(" mpl=0x%x ctl=%d nrl=%d\n",
806 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
807 EHCI_QH_GET_NRL(endp));
808 endphub = hc32toh(sc, qh->qh_endphub);
809 printf(" endphub=0x%08x\n", endphub);
810 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
811 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
812 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
813 EHCI_QH_GET_MULT(endphub));
814 printf(" curqtd=");
815 ehci_dump_link(sc, qh->qh_curqtd, 0);
816 printf("\n");
817 printf("Overlay qTD:\n");
818 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
819 }
820
821 static void
ehci_dump_sitd(ehci_softc_t * sc,ehci_sitd_t * sitd)822 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
823 {
824 usb_pc_cpu_invalidate(sitd->page_cache);
825 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
826 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
827 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
828 hc32toh(sc, sitd->sitd_portaddr),
829 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
830 ? "in" : "out",
831 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
832 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
833 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
834 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
835 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
836 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
837 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
838 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
839 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
840 hc32toh(sc, sitd->sitd_back),
841 hc32toh(sc, sitd->sitd_bp[0]),
842 hc32toh(sc, sitd->sitd_bp[1]),
843 hc32toh(sc, sitd->sitd_bp_hi[0]),
844 hc32toh(sc, sitd->sitd_bp_hi[1]));
845 }
846
847 static void
ehci_dump_itd(ehci_softc_t * sc,ehci_itd_t * itd)848 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
849 {
850 usb_pc_cpu_invalidate(itd->page_cache);
851 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
852 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
853 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
854 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
855 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
856 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
857 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
858 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
859 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
860 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
861 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
862 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
863 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
864 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
865 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
866 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
867 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
868 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
869 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
870 printf(" addr=0x%02x; endpt=0x%01x\n",
871 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
872 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
873 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
874 printf(" dir=%s; mpl=0x%02x\n",
875 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
876 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
877 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
878 hc32toh(sc, itd->itd_bp[2]),
879 hc32toh(sc, itd->itd_bp[3]),
880 hc32toh(sc, itd->itd_bp[4]),
881 hc32toh(sc, itd->itd_bp[5]),
882 hc32toh(sc, itd->itd_bp[6]));
883 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
884 " 0x%08x,0x%08x,0x%08x\n",
885 hc32toh(sc, itd->itd_bp_hi[0]),
886 hc32toh(sc, itd->itd_bp_hi[1]),
887 hc32toh(sc, itd->itd_bp_hi[2]),
888 hc32toh(sc, itd->itd_bp_hi[3]),
889 hc32toh(sc, itd->itd_bp_hi[4]),
890 hc32toh(sc, itd->itd_bp_hi[5]),
891 hc32toh(sc, itd->itd_bp_hi[6]));
892 }
893
894 static void
ehci_dump_isoc(ehci_softc_t * sc)895 ehci_dump_isoc(ehci_softc_t *sc)
896 {
897 ehci_itd_t *itd;
898 ehci_sitd_t *sitd;
899 uint16_t max = 1000;
900 uint16_t pos;
901
902 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
903 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
904
905 printf("%s: isochronous dump from frame 0x%03x:\n",
906 __FUNCTION__, pos);
907
908 itd = sc->sc_isoc_hs_p_last[pos];
909 sitd = sc->sc_isoc_fs_p_last[pos];
910
911 while (itd && max && max--) {
912 ehci_dump_itd(sc, itd);
913 itd = itd->prev;
914 }
915
916 while (sitd && max && max--) {
917 ehci_dump_sitd(sc, sitd);
918 sitd = sitd->prev;
919 }
920 }
921
922 #endif
923
924 static void
ehci_transfer_intr_enqueue(struct usb_xfer * xfer)925 ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
926 {
927 /* check for early completion */
928 if (ehci_check_transfer(xfer)) {
929 return;
930 }
931 /* put transfer on interrupt queue */
932 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
933
934 /* start timeout, if any */
935 if (xfer->timeout != 0) {
936 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
937 }
938 }
939
940 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
941 static ehci_sitd_t *
_ehci_append_fs_td(ehci_sitd_t * std,ehci_sitd_t * last)942 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
943 {
944 DPRINTFN(11, "%p to %p\n", std, last);
945
946 /* (sc->sc_bus.mtx) must be locked */
947
948 std->next = last->next;
949 std->sitd_next = last->sitd_next;
950
951 std->prev = last;
952
953 usb_pc_cpu_flush(std->page_cache);
954
955 /*
956 * the last->next->prev is never followed: std->next->prev = std;
957 */
958 last->next = std;
959 last->sitd_next = std->sitd_self;
960
961 usb_pc_cpu_flush(last->page_cache);
962
963 return (std);
964 }
965
966 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
967 static ehci_itd_t *
_ehci_append_hs_td(ehci_itd_t * std,ehci_itd_t * last)968 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
969 {
970 DPRINTFN(11, "%p to %p\n", std, last);
971
972 /* (sc->sc_bus.mtx) must be locked */
973
974 std->next = last->next;
975 std->itd_next = last->itd_next;
976
977 std->prev = last;
978
979 usb_pc_cpu_flush(std->page_cache);
980
981 /*
982 * the last->next->prev is never followed: std->next->prev = std;
983 */
984 last->next = std;
985 last->itd_next = std->itd_self;
986
987 usb_pc_cpu_flush(last->page_cache);
988
989 return (std);
990 }
991
992 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
993 static ehci_qh_t *
_ehci_append_qh(ehci_qh_t * sqh,ehci_qh_t * last)994 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
995 {
996 DPRINTFN(11, "%p to %p\n", sqh, last);
997
998 if (sqh->prev != NULL) {
999 /* should not happen */
1000 DPRINTFN(0, "QH already linked!\n");
1001 return (last);
1002 }
1003 /* (sc->sc_bus.mtx) must be locked */
1004
1005 sqh->next = last->next;
1006 sqh->qh_link = last->qh_link;
1007
1008 sqh->prev = last;
1009
1010 usb_pc_cpu_flush(sqh->page_cache);
1011
1012 /*
1013 * the last->next->prev is never followed: sqh->next->prev = sqh;
1014 */
1015
1016 last->next = sqh;
1017 last->qh_link = sqh->qh_self;
1018
1019 usb_pc_cpu_flush(last->page_cache);
1020
1021 return (sqh);
1022 }
1023
1024 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1025 static ehci_sitd_t *
_ehci_remove_fs_td(ehci_sitd_t * std,ehci_sitd_t * last)1026 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1027 {
1028 DPRINTFN(11, "%p from %p\n", std, last);
1029
1030 /* (sc->sc_bus.mtx) must be locked */
1031
1032 std->prev->next = std->next;
1033 std->prev->sitd_next = std->sitd_next;
1034
1035 usb_pc_cpu_flush(std->prev->page_cache);
1036
1037 if (std->next) {
1038 std->next->prev = std->prev;
1039 usb_pc_cpu_flush(std->next->page_cache);
1040 }
1041 return ((last == std) ? std->prev : last);
1042 }
1043
1044 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1045 static ehci_itd_t *
_ehci_remove_hs_td(ehci_itd_t * std,ehci_itd_t * last)1046 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1047 {
1048 DPRINTFN(11, "%p from %p\n", std, last);
1049
1050 /* (sc->sc_bus.mtx) must be locked */
1051
1052 std->prev->next = std->next;
1053 std->prev->itd_next = std->itd_next;
1054
1055 usb_pc_cpu_flush(std->prev->page_cache);
1056
1057 if (std->next) {
1058 std->next->prev = std->prev;
1059 usb_pc_cpu_flush(std->next->page_cache);
1060 }
1061 return ((last == std) ? std->prev : last);
1062 }
1063
1064 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1065 static ehci_qh_t *
_ehci_remove_qh(ehci_qh_t * sqh,ehci_qh_t * last)1066 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1067 {
1068 DPRINTFN(11, "%p from %p\n", sqh, last);
1069
1070 /* (sc->sc_bus.mtx) must be locked */
1071
1072 /* only remove if not removed from a queue */
1073 if (sqh->prev) {
1074
1075 sqh->prev->next = sqh->next;
1076 sqh->prev->qh_link = sqh->qh_link;
1077
1078 usb_pc_cpu_flush(sqh->prev->page_cache);
1079
1080 if (sqh->next) {
1081 sqh->next->prev = sqh->prev;
1082 usb_pc_cpu_flush(sqh->next->page_cache);
1083 }
1084 last = ((last == sqh) ? sqh->prev : last);
1085
1086 sqh->prev = 0;
1087
1088 usb_pc_cpu_flush(sqh->page_cache);
1089 }
1090 return (last);
1091 }
1092
1093 static void
ehci_data_toggle_update(struct usb_xfer * xfer,uint16_t actlen,uint16_t xlen)1094 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1095 {
1096 uint16_t rem;
1097 uint8_t dt;
1098
1099 /* count number of full packets */
1100 dt = (actlen / xfer->max_packet_size) & 1;
1101
1102 /* compute remainder */
1103 rem = actlen % xfer->max_packet_size;
1104
1105 if (rem > 0)
1106 dt ^= 1; /* short packet at the end */
1107 else if (actlen != xlen)
1108 dt ^= 1; /* zero length packet at the end */
1109 else if (xlen == 0)
1110 dt ^= 1; /* zero length transfer */
1111
1112 xfer->endpoint->toggle_next ^= dt;
1113 }
1114
1115 static usb_error_t
ehci_non_isoc_done_sub(struct usb_xfer * xfer)1116 ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1117 {
1118 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1119 ehci_qtd_t *td;
1120 ehci_qtd_t *td_alt_next;
1121 uint32_t status;
1122 uint16_t len;
1123
1124 td = xfer->td_transfer_cache;
1125 td_alt_next = td->alt_next;
1126
1127 if (xfer->aframes != xfer->nframes) {
1128 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1129 }
1130 while (1) {
1131
1132 usb_pc_cpu_invalidate(td->page_cache);
1133 status = hc32toh(sc, td->qtd_status);
1134
1135 len = EHCI_QTD_GET_BYTES(status);
1136
1137 /*
1138 * Verify the status length and
1139 * add the length to "frlengths[]":
1140 */
1141 if (len > td->len) {
1142 /* should not happen */
1143 DPRINTF("Invalid status length, "
1144 "0x%04x/0x%04x bytes\n", len, td->len);
1145 status |= EHCI_QTD_HALTED;
1146 } else if (xfer->aframes != xfer->nframes) {
1147 xfer->frlengths[xfer->aframes] += td->len - len;
1148 /* manually update data toggle */
1149 ehci_data_toggle_update(xfer, td->len - len, td->len);
1150 }
1151
1152 /* Check for last transfer */
1153 if (((void *)td) == xfer->td_transfer_last) {
1154 td = NULL;
1155 break;
1156 }
1157 /* Check for transfer error */
1158 if (status & EHCI_QTD_HALTED) {
1159 /* the transfer is finished */
1160 td = NULL;
1161 break;
1162 }
1163 /* Check for short transfer */
1164 if (len > 0) {
1165 if (xfer->flags_int.short_frames_ok) {
1166 /* follow alt next */
1167 td = td->alt_next;
1168 } else {
1169 /* the transfer is finished */
1170 td = NULL;
1171 }
1172 break;
1173 }
1174 td = td->obj_next;
1175
1176 if (td->alt_next != td_alt_next) {
1177 /* this USB frame is complete */
1178 break;
1179 }
1180 }
1181
1182 /* update transfer cache */
1183
1184 xfer->td_transfer_cache = td;
1185
1186 #ifdef USB_DEBUG
1187 if (status & EHCI_QTD_STATERRS) {
1188 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1189 "status=%s%s%s%s%s%s%s%s\n",
1190 xfer->address, xfer->endpointno, xfer->aframes,
1191 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1192 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1193 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1194 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1195 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1196 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1197 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1198 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1199 }
1200 #endif
1201 if (status & EHCI_QTD_HALTED) {
1202 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1203 (xfer->xroot->udev->address != 0)) {
1204 /* try to separate I/O errors from STALL */
1205 if (EHCI_QTD_GET_CERR(status) == 0)
1206 return (USB_ERR_IOERROR);
1207 }
1208 return (USB_ERR_STALLED);
1209 }
1210 return (USB_ERR_NORMAL_COMPLETION);
1211 }
1212
1213 static void
ehci_non_isoc_done(struct usb_xfer * xfer)1214 ehci_non_isoc_done(struct usb_xfer *xfer)
1215 {
1216 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1217 ehci_qh_t *qh;
1218 uint32_t status;
1219 usb_error_t err = 0;
1220
1221 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1222 xfer, xfer->endpoint);
1223
1224 #ifdef USB_DEBUG
1225 if (ehcidebug > 10) {
1226 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1227
1228 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1229 }
1230 #endif
1231
1232 /* extract data toggle directly from the QH's overlay area */
1233
1234 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1235
1236 usb_pc_cpu_invalidate(qh->page_cache);
1237
1238 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1239
1240 /* reset scanner */
1241
1242 xfer->td_transfer_cache = xfer->td_transfer_first;
1243
1244 if (xfer->flags_int.control_xfr) {
1245
1246 if (xfer->flags_int.control_hdr) {
1247
1248 err = ehci_non_isoc_done_sub(xfer);
1249 }
1250 xfer->aframes = 1;
1251
1252 if (xfer->td_transfer_cache == NULL) {
1253 goto done;
1254 }
1255 }
1256 while (xfer->aframes != xfer->nframes) {
1257
1258 err = ehci_non_isoc_done_sub(xfer);
1259 xfer->aframes++;
1260
1261 if (xfer->td_transfer_cache == NULL) {
1262 goto done;
1263 }
1264 }
1265
1266 if (xfer->flags_int.control_xfr &&
1267 !xfer->flags_int.control_act) {
1268
1269 err = ehci_non_isoc_done_sub(xfer);
1270 }
1271 done:
1272 ehci_device_done(xfer, err);
1273 }
1274
1275 /*------------------------------------------------------------------------*
1276 * ehci_check_transfer
1277 *
1278 * Return values:
1279 * 0: USB transfer is not finished
1280 * Else: USB transfer is finished
1281 *------------------------------------------------------------------------*/
1282 static uint8_t
ehci_check_transfer(struct usb_xfer * xfer)1283 ehci_check_transfer(struct usb_xfer *xfer)
1284 {
1285 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1286 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1287
1288 uint32_t status;
1289
1290 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1291
1292 if (methods == &ehci_device_isoc_fs_methods) {
1293 ehci_sitd_t *td;
1294
1295 /* isochronous full speed transfer */
1296
1297 td = xfer->td_transfer_last;
1298 usb_pc_cpu_invalidate(td->page_cache);
1299 status = hc32toh(sc, td->sitd_status);
1300
1301 /* also check if first is complete */
1302
1303 td = xfer->td_transfer_first;
1304 usb_pc_cpu_invalidate(td->page_cache);
1305 status |= hc32toh(sc, td->sitd_status);
1306
1307 if (!(status & EHCI_SITD_ACTIVE)) {
1308 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1309 goto transferred;
1310 }
1311 } else if (methods == &ehci_device_isoc_hs_methods) {
1312 ehci_itd_t *td;
1313
1314 /* isochronous high speed transfer */
1315
1316 /* check last transfer */
1317 td = xfer->td_transfer_last;
1318 usb_pc_cpu_invalidate(td->page_cache);
1319 status = td->itd_status[0];
1320 status |= td->itd_status[1];
1321 status |= td->itd_status[2];
1322 status |= td->itd_status[3];
1323 status |= td->itd_status[4];
1324 status |= td->itd_status[5];
1325 status |= td->itd_status[6];
1326 status |= td->itd_status[7];
1327
1328 /* also check first transfer */
1329 td = xfer->td_transfer_first;
1330 usb_pc_cpu_invalidate(td->page_cache);
1331 status |= td->itd_status[0];
1332 status |= td->itd_status[1];
1333 status |= td->itd_status[2];
1334 status |= td->itd_status[3];
1335 status |= td->itd_status[4];
1336 status |= td->itd_status[5];
1337 status |= td->itd_status[6];
1338 status |= td->itd_status[7];
1339
1340 /* if no transactions are active we continue */
1341 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1342 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1343 goto transferred;
1344 }
1345 } else {
1346 ehci_qtd_t *td;
1347 ehci_qh_t *qh;
1348
1349 /* non-isochronous transfer */
1350
1351 /*
1352 * check whether there is an error somewhere in the middle,
1353 * or whether there was a short packet (SPD and not ACTIVE)
1354 */
1355 td = xfer->td_transfer_cache;
1356
1357 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1358
1359 usb_pc_cpu_invalidate(qh->page_cache);
1360
1361 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1362 if (status & EHCI_QTD_ACTIVE) {
1363 /* transfer is pending */
1364 goto done;
1365 }
1366
1367 while (1) {
1368 usb_pc_cpu_invalidate(td->page_cache);
1369 status = hc32toh(sc, td->qtd_status);
1370
1371 /*
1372 * Check if there is an active TD which
1373 * indicates that the transfer isn't done.
1374 */
1375 if (status & EHCI_QTD_ACTIVE) {
1376 /* update cache */
1377 xfer->td_transfer_cache = td;
1378 goto done;
1379 }
1380 /*
1381 * last transfer descriptor makes the transfer done
1382 */
1383 if (((void *)td) == xfer->td_transfer_last) {
1384 break;
1385 }
1386 /*
1387 * any kind of error makes the transfer done
1388 */
1389 if (status & EHCI_QTD_HALTED) {
1390 break;
1391 }
1392 /*
1393 * if there is no alternate next transfer, a short
1394 * packet also makes the transfer done
1395 */
1396 if (EHCI_QTD_GET_BYTES(status)) {
1397 if (xfer->flags_int.short_frames_ok) {
1398 /* follow alt next */
1399 if (td->alt_next) {
1400 td = td->alt_next;
1401 continue;
1402 }
1403 }
1404 /* transfer is done */
1405 break;
1406 }
1407 td = td->obj_next;
1408 }
1409 ehci_non_isoc_done(xfer);
1410 goto transferred;
1411 }
1412
1413 done:
1414 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1415 return (0);
1416
1417 transferred:
1418 return (1);
1419 }
1420
1421 static void
ehci_pcd_enable(ehci_softc_t * sc)1422 ehci_pcd_enable(ehci_softc_t *sc)
1423 {
1424 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1425
1426 sc->sc_eintrs |= EHCI_STS_PCD;
1427 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1428
1429 /* acknowledge any PCD interrupt */
1430 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1431
1432 ehci_root_intr(sc);
1433 }
1434
1435 static void
ehci_interrupt_poll(ehci_softc_t * sc)1436 ehci_interrupt_poll(ehci_softc_t *sc)
1437 {
1438 struct usb_xfer *xfer;
1439
1440 repeat:
1441 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1442 /*
1443 * check if transfer is transferred
1444 */
1445 if (ehci_check_transfer(xfer)) {
1446 /* queue has been modified */
1447 goto repeat;
1448 }
1449 }
1450 }
1451
1452 /*
1453 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1454 * writing back the qTD status, or miss signalling occasionally under
1455 * heavy load. If the host machine is too fast, we can miss
1456 * transaction completion - when we scan the active list the
1457 * transaction still seems to be active. This generally exhibits
1458 * itself as a umass stall that never recovers.
1459 *
1460 * We work around this behaviour by setting up this callback after any
1461 * softintr that completes with transactions still pending, giving us
1462 * another chance to check for completion after the writeback has
1463 * taken place.
1464 */
1465 static void
ehci_poll_timeout(void * arg)1466 ehci_poll_timeout(void *arg)
1467 {
1468 ehci_softc_t *sc = arg;
1469
1470 DPRINTFN(3, "\n");
1471 ehci_interrupt_poll(sc);
1472 }
1473
1474 /*------------------------------------------------------------------------*
1475 * ehci_interrupt - EHCI interrupt handler
1476 *
1477 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1478 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1479 * is present !
1480 *------------------------------------------------------------------------*/
1481 void
ehci_interrupt(ehci_softc_t * sc)1482 ehci_interrupt(ehci_softc_t *sc)
1483 {
1484 uint32_t status;
1485
1486 USB_BUS_LOCK(&sc->sc_bus);
1487
1488 DPRINTFN(16, "real interrupt\n");
1489
1490 #ifdef USB_DEBUG
1491 if (ehcidebug > 15) {
1492 ehci_dump_regs(sc);
1493 }
1494 #endif
1495
1496 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1497 if (status == 0) {
1498 /* the interrupt was not for us */
1499 goto done;
1500 }
1501 if (!(status & sc->sc_eintrs)) {
1502 goto done;
1503 }
1504 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1505
1506 status &= sc->sc_eintrs;
1507
1508 if (status & EHCI_STS_HSE) {
1509 printf("%s: unrecoverable error, "
1510 "controller halted\n", __FUNCTION__);
1511 #ifdef USB_DEBUG
1512 ehci_dump_regs(sc);
1513 ehci_dump_isoc(sc);
1514 #endif
1515 }
1516 if (status & EHCI_STS_PCD) {
1517 /*
1518 * Disable PCD interrupt for now, because it will be
1519 * on until the port has been reset.
1520 */
1521 sc->sc_eintrs &= ~EHCI_STS_PCD;
1522 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1523
1524 ehci_root_intr(sc);
1525
1526 /* do not allow RHSC interrupts > 1 per second */
1527 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1528 (void *)&ehci_pcd_enable, sc);
1529 }
1530 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1531
1532 if (status != 0) {
1533 /* block unprocessed interrupts */
1534 sc->sc_eintrs &= ~status;
1535 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1536 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1537 }
1538 /* poll all the USB transfers */
1539 ehci_interrupt_poll(sc);
1540
1541 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1542 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1543 (void *)&ehci_poll_timeout, sc);
1544 }
1545
1546 done:
1547 USB_BUS_UNLOCK(&sc->sc_bus);
1548 }
1549
1550 /*
1551 * called when a request does not complete
1552 */
1553 static void
ehci_timeout(void * arg)1554 ehci_timeout(void *arg)
1555 {
1556 struct usb_xfer *xfer = arg;
1557
1558 DPRINTF("xfer=%p\n", xfer);
1559
1560 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1561
1562 /* transfer is transferred */
1563 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1564 }
1565
1566 static void
ehci_do_poll(struct usb_bus * bus)1567 ehci_do_poll(struct usb_bus *bus)
1568 {
1569 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1570
1571 USB_BUS_LOCK(&sc->sc_bus);
1572 ehci_interrupt_poll(sc);
1573 USB_BUS_UNLOCK(&sc->sc_bus);
1574 }
1575
1576 static void
ehci_setup_standard_chain_sub(struct ehci_std_temp * temp)1577 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1578 {
1579 struct usb_page_search buf_res;
1580 ehci_qtd_t *td;
1581 ehci_qtd_t *td_next;
1582 ehci_qtd_t *td_alt_next;
1583 uint32_t buf_offset;
1584 uint32_t average;
1585 uint32_t len_old;
1586 uint32_t terminate;
1587 uint32_t qtd_altnext;
1588 uint8_t shortpkt_old;
1589 uint8_t precompute;
1590
1591 terminate = temp->sc->sc_terminate_self;
1592 qtd_altnext = temp->sc->sc_terminate_self;
1593 td_alt_next = NULL;
1594 buf_offset = 0;
1595 shortpkt_old = temp->shortpkt;
1596 len_old = temp->len;
1597 precompute = 1;
1598
1599 restart:
1600
1601 td = temp->td;
1602 td_next = temp->td_next;
1603
1604 while (1) {
1605
1606 if (temp->len == 0) {
1607
1608 if (temp->shortpkt) {
1609 break;
1610 }
1611 /* send a Zero Length Packet, ZLP, last */
1612
1613 temp->shortpkt = 1;
1614 average = 0;
1615
1616 } else {
1617
1618 average = temp->average;
1619
1620 if (temp->len < average) {
1621 if (temp->len % temp->max_frame_size) {
1622 temp->shortpkt = 1;
1623 }
1624 average = temp->len;
1625 }
1626 }
1627
1628 if (td_next == NULL) {
1629 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1630 }
1631 /* get next TD */
1632
1633 td = td_next;
1634 td_next = td->obj_next;
1635
1636 /* check if we are pre-computing */
1637
1638 if (precompute) {
1639
1640 /* update remaining length */
1641
1642 temp->len -= average;
1643
1644 continue;
1645 }
1646 /* fill out current TD */
1647
1648 td->qtd_status =
1649 temp->qtd_status |
1650 htohc32(temp->sc, EHCI_QTD_IOC |
1651 EHCI_QTD_SET_BYTES(average));
1652
1653 if (average == 0) {
1654
1655 if (temp->auto_data_toggle == 0) {
1656
1657 /* update data toggle, ZLP case */
1658
1659 temp->qtd_status ^=
1660 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1661 }
1662 td->len = 0;
1663
1664 /* properly reset reserved fields */
1665 td->qtd_buffer[0] = 0;
1666 td->qtd_buffer[1] = 0;
1667 td->qtd_buffer[2] = 0;
1668 td->qtd_buffer[3] = 0;
1669 td->qtd_buffer[4] = 0;
1670 td->qtd_buffer_hi[0] = 0;
1671 td->qtd_buffer_hi[1] = 0;
1672 td->qtd_buffer_hi[2] = 0;
1673 td->qtd_buffer_hi[3] = 0;
1674 td->qtd_buffer_hi[4] = 0;
1675 } else {
1676
1677 uint8_t x;
1678
1679 if (temp->auto_data_toggle == 0) {
1680
1681 /* update data toggle */
1682
1683 if (((average + temp->max_frame_size - 1) /
1684 temp->max_frame_size) & 1) {
1685 temp->qtd_status ^=
1686 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1687 }
1688 }
1689 td->len = average;
1690
1691 /* update remaining length */
1692
1693 temp->len -= average;
1694
1695 /* fill out buffer pointers */
1696
1697 usbd_get_page(temp->pc, buf_offset, &buf_res);
1698 td->qtd_buffer[0] =
1699 htohc32(temp->sc, buf_res.physaddr);
1700 td->qtd_buffer_hi[0] = 0;
1701
1702 x = 1;
1703
1704 while (average > EHCI_PAGE_SIZE) {
1705 average -= EHCI_PAGE_SIZE;
1706 buf_offset += EHCI_PAGE_SIZE;
1707 usbd_get_page(temp->pc, buf_offset, &buf_res);
1708 td->qtd_buffer[x] =
1709 htohc32(temp->sc,
1710 buf_res.physaddr & (~0xFFF));
1711 td->qtd_buffer_hi[x] = 0;
1712 x++;
1713 }
1714
1715 /*
1716 * NOTE: The "average" variable is never zero after
1717 * exiting the loop above !
1718 *
1719 * NOTE: We have to subtract one from the offset to
1720 * ensure that we are computing the physical address
1721 * of a valid page !
1722 */
1723 buf_offset += average;
1724 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1725 td->qtd_buffer[x] =
1726 htohc32(temp->sc,
1727 buf_res.physaddr & (~0xFFF));
1728 td->qtd_buffer_hi[x] = 0;
1729
1730 /* properly reset reserved fields */
1731 while (++x < EHCI_QTD_NBUFFERS) {
1732 td->qtd_buffer[x] = 0;
1733 td->qtd_buffer_hi[x] = 0;
1734 }
1735 }
1736
1737 if (td_next) {
1738 /* link the current TD with the next one */
1739 td->qtd_next = td_next->qtd_self;
1740 }
1741 td->qtd_altnext = qtd_altnext;
1742 td->alt_next = td_alt_next;
1743
1744 usb_pc_cpu_flush(td->page_cache);
1745 }
1746
1747 if (precompute) {
1748 precompute = 0;
1749
1750 /* setup alt next pointer, if any */
1751 if (temp->last_frame) {
1752 td_alt_next = NULL;
1753 qtd_altnext = terminate;
1754 } else {
1755 /* we use this field internally */
1756 td_alt_next = td_next;
1757 if (temp->setup_alt_next) {
1758 qtd_altnext = td_next->qtd_self;
1759 } else {
1760 qtd_altnext = terminate;
1761 }
1762 }
1763
1764 /* restore */
1765 temp->shortpkt = shortpkt_old;
1766 temp->len = len_old;
1767 goto restart;
1768 }
1769 temp->td = td;
1770 temp->td_next = td_next;
1771 }
1772
1773 static void
ehci_setup_standard_chain(struct usb_xfer * xfer,ehci_qh_t ** qh_last)1774 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1775 {
1776 struct ehci_std_temp temp;
1777 struct usb_pipe_methods *methods;
1778 ehci_qh_t *qh;
1779 ehci_qtd_t *td;
1780 uint32_t qh_endp;
1781 uint32_t qh_endphub;
1782 uint32_t x;
1783
1784 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1785 xfer->address, UE_GET_ADDR(xfer->endpointno),
1786 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1787
1788 temp.average = xfer->max_hc_frame_size;
1789 temp.max_frame_size = xfer->max_frame_size;
1790 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1791
1792 /* toggle the DMA set we are using */
1793 xfer->flags_int.curr_dma_set ^= 1;
1794
1795 /* get next DMA set */
1796 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1797
1798 xfer->td_transfer_first = td;
1799 xfer->td_transfer_cache = td;
1800
1801 temp.td = NULL;
1802 temp.td_next = td;
1803 temp.qtd_status = 0;
1804 temp.last_frame = 0;
1805 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1806
1807 if (xfer->flags_int.control_xfr) {
1808 if (xfer->endpoint->toggle_next) {
1809 /* DATA1 is next */
1810 temp.qtd_status |=
1811 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1812 }
1813 temp.auto_data_toggle = 0;
1814 } else {
1815 temp.auto_data_toggle = 1;
1816 }
1817
1818 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1819 (xfer->xroot->udev->address != 0)) {
1820 /* max 3 retries */
1821 temp.qtd_status |=
1822 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1823 }
1824 /* check if we should prepend a setup message */
1825
1826 if (xfer->flags_int.control_xfr) {
1827 if (xfer->flags_int.control_hdr) {
1828
1829 xfer->endpoint->toggle_next = 0;
1830
1831 temp.qtd_status &=
1832 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1833 temp.qtd_status |= htohc32(temp.sc,
1834 EHCI_QTD_ACTIVE |
1835 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1836 EHCI_QTD_SET_TOGGLE(0));
1837
1838 temp.len = xfer->frlengths[0];
1839 temp.pc = xfer->frbuffers + 0;
1840 temp.shortpkt = temp.len ? 1 : 0;
1841 /* check for last frame */
1842 if (xfer->nframes == 1) {
1843 /* no STATUS stage yet, SETUP is last */
1844 if (xfer->flags_int.control_act) {
1845 temp.last_frame = 1;
1846 temp.setup_alt_next = 0;
1847 }
1848 }
1849 ehci_setup_standard_chain_sub(&temp);
1850 }
1851 x = 1;
1852 } else {
1853 x = 0;
1854 }
1855
1856 while (x != xfer->nframes) {
1857
1858 /* DATA0 / DATA1 message */
1859
1860 temp.len = xfer->frlengths[x];
1861 temp.pc = xfer->frbuffers + x;
1862
1863 x++;
1864
1865 if (x == xfer->nframes) {
1866 if (xfer->flags_int.control_xfr) {
1867 /* no STATUS stage yet, DATA is last */
1868 if (xfer->flags_int.control_act) {
1869 temp.last_frame = 1;
1870 temp.setup_alt_next = 0;
1871 }
1872 } else {
1873 temp.last_frame = 1;
1874 temp.setup_alt_next = 0;
1875 }
1876 }
1877 /* keep previous data toggle and error count */
1878
1879 temp.qtd_status &=
1880 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1881 EHCI_QTD_SET_TOGGLE(1));
1882
1883 if (temp.len == 0) {
1884
1885 /* make sure that we send an USB packet */
1886
1887 temp.shortpkt = 0;
1888
1889 } else {
1890
1891 /* regular data transfer */
1892
1893 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1894 }
1895
1896 /* set endpoint direction */
1897
1898 temp.qtd_status |=
1899 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1900 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1901 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1902 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1903 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1904
1905 ehci_setup_standard_chain_sub(&temp);
1906 }
1907
1908 /* check if we should append a status stage */
1909
1910 if (xfer->flags_int.control_xfr &&
1911 !xfer->flags_int.control_act) {
1912
1913 /*
1914 * Send a DATA1 message and invert the current endpoint
1915 * direction.
1916 */
1917
1918 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1919 EHCI_QTD_SET_TOGGLE(1));
1920 temp.qtd_status |=
1921 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1922 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1923 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1924 EHCI_QTD_SET_TOGGLE(1)) :
1925 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1926 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1927 EHCI_QTD_SET_TOGGLE(1));
1928
1929 temp.len = 0;
1930 temp.pc = NULL;
1931 temp.shortpkt = 0;
1932 temp.last_frame = 1;
1933 temp.setup_alt_next = 0;
1934
1935 ehci_setup_standard_chain_sub(&temp);
1936 }
1937 td = temp.td;
1938
1939 /* the last TD terminates the transfer: */
1940 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1941 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1942
1943 usb_pc_cpu_flush(td->page_cache);
1944
1945 /* must have at least one frame! */
1946
1947 xfer->td_transfer_last = td;
1948
1949 #ifdef USB_DEBUG
1950 if (ehcidebug > 8) {
1951 DPRINTF("nexttog=%d; data before transfer:\n",
1952 xfer->endpoint->toggle_next);
1953 ehci_dump_sqtds(temp.sc,
1954 xfer->td_transfer_first);
1955 }
1956 #endif
1957
1958 methods = xfer->endpoint->methods;
1959
1960 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1961
1962 /* the "qh_link" field is filled when the QH is added */
1963
1964 qh_endp =
1965 (EHCI_QH_SET_ADDR(xfer->address) |
1966 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1967 EHCI_QH_SET_MPL(xfer->max_packet_size));
1968
1969 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1970 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1971 if (methods != &ehci_device_intr_methods)
1972 qh_endp |= EHCI_QH_SET_NRL(8);
1973 } else {
1974
1975 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1976 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1977 } else {
1978 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1979 }
1980
1981 if (methods == &ehci_device_ctrl_methods) {
1982 qh_endp |= EHCI_QH_CTL;
1983 }
1984 if (methods != &ehci_device_intr_methods) {
1985 /* Only try one time per microframe! */
1986 qh_endp |= EHCI_QH_SET_NRL(1);
1987 }
1988 }
1989
1990 if (temp.auto_data_toggle == 0) {
1991 /* software computes the data toggle */
1992 qh_endp |= EHCI_QH_DTC;
1993 }
1994
1995 qh->qh_endp = htohc32(temp.sc, qh_endp);
1996
1997 qh_endphub =
1998 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1999 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
2000 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
2001 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2002 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2003
2004 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2005 qh->qh_curqtd = 0;
2006
2007 /* fill the overlay qTD */
2008
2009 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2010 /* DATA1 is next */
2011 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2012 } else {
2013 qh->qh_qtd.qtd_status = 0;
2014 }
2015
2016 td = xfer->td_transfer_first;
2017
2018 qh->qh_qtd.qtd_next = td->qtd_self;
2019 qh->qh_qtd.qtd_altnext =
2020 htohc32(temp.sc, EHCI_LINK_TERMINATE);
2021
2022 /* properly reset reserved fields */
2023 qh->qh_qtd.qtd_buffer[0] = 0;
2024 qh->qh_qtd.qtd_buffer[1] = 0;
2025 qh->qh_qtd.qtd_buffer[2] = 0;
2026 qh->qh_qtd.qtd_buffer[3] = 0;
2027 qh->qh_qtd.qtd_buffer[4] = 0;
2028 qh->qh_qtd.qtd_buffer_hi[0] = 0;
2029 qh->qh_qtd.qtd_buffer_hi[1] = 0;
2030 qh->qh_qtd.qtd_buffer_hi[2] = 0;
2031 qh->qh_qtd.qtd_buffer_hi[3] = 0;
2032 qh->qh_qtd.qtd_buffer_hi[4] = 0;
2033
2034 usb_pc_cpu_flush(qh->page_cache);
2035
2036 if (xfer->xroot->udev->flags.self_suspended == 0) {
2037 EHCI_APPEND_QH(qh, *qh_last);
2038 }
2039 }
2040
2041 static void
ehci_root_intr(ehci_softc_t * sc)2042 ehci_root_intr(ehci_softc_t *sc)
2043 {
2044 uint16_t i;
2045 uint16_t m;
2046
2047 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2048
2049 /* clear any old interrupt data */
2050 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2051
2052 /* set bits */
2053 m = (sc->sc_noport + 1);
2054 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2055 m = (8 * sizeof(sc->sc_hub_idata));
2056 }
2057 for (i = 1; i < m; i++) {
2058 /* pick out CHANGE bits from the status register */
2059 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2060 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2061 DPRINTF("port %d changed\n", i);
2062 }
2063 }
2064 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2065 sizeof(sc->sc_hub_idata));
2066 }
2067
2068 static void
ehci_isoc_fs_done(ehci_softc_t * sc,struct usb_xfer * xfer)2069 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2070 {
2071 uint32_t nframes = xfer->nframes;
2072 uint32_t status;
2073 uint32_t *plen = xfer->frlengths;
2074 uint16_t len = 0;
2075 ehci_sitd_t *td = xfer->td_transfer_first;
2076 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2077
2078 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2079 xfer, xfer->endpoint);
2080
2081 while (nframes--) {
2082 if (td == NULL) {
2083 panic("%s:%d: out of TD's\n",
2084 __FUNCTION__, __LINE__);
2085 }
2086 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2087 pp_last = &sc->sc_isoc_fs_p_last[0];
2088 }
2089 #ifdef USB_DEBUG
2090 if (ehcidebug > 15) {
2091 DPRINTF("isoc FS-TD\n");
2092 ehci_dump_sitd(sc, td);
2093 }
2094 #endif
2095 usb_pc_cpu_invalidate(td->page_cache);
2096 status = hc32toh(sc, td->sitd_status);
2097
2098 len = EHCI_SITD_GET_LEN(status);
2099
2100 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2101
2102 if (*plen >= len) {
2103 len = *plen - len;
2104 } else {
2105 len = 0;
2106 }
2107
2108 *plen = len;
2109
2110 /* remove FS-TD from schedule */
2111 EHCI_REMOVE_FS_TD(td, *pp_last);
2112
2113 pp_last++;
2114 plen++;
2115 td = td->obj_next;
2116 }
2117
2118 xfer->aframes = xfer->nframes;
2119 }
2120
2121 static void
ehci_isoc_hs_done(ehci_softc_t * sc,struct usb_xfer * xfer)2122 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2123 {
2124 uint32_t nframes = xfer->nframes;
2125 uint32_t status;
2126 uint32_t *plen = xfer->frlengths;
2127 uint16_t len = 0;
2128 uint8_t td_no = 0;
2129 ehci_itd_t *td = xfer->td_transfer_first;
2130 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2131
2132 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2133 xfer, xfer->endpoint);
2134
2135 while (nframes) {
2136 if (td == NULL) {
2137 panic("%s:%d: out of TD's\n",
2138 __FUNCTION__, __LINE__);
2139 }
2140 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2141 pp_last = &sc->sc_isoc_hs_p_last[0];
2142 }
2143 #ifdef USB_DEBUG
2144 if (ehcidebug > 15) {
2145 DPRINTF("isoc HS-TD\n");
2146 ehci_dump_itd(sc, td);
2147 }
2148 #endif
2149
2150 usb_pc_cpu_invalidate(td->page_cache);
2151 status = hc32toh(sc, td->itd_status[td_no]);
2152
2153 len = EHCI_ITD_GET_LEN(status);
2154
2155 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2156
2157 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2158
2159 if (*plen >= len) {
2160 /*
2161 * The length is valid. NOTE: The
2162 * complete length is written back
2163 * into the status field, and not the
2164 * remainder like with other transfer
2165 * descriptor types.
2166 */
2167 } else {
2168 /* Invalid length - truncate */
2169 len = 0;
2170 }
2171
2172 *plen = len;
2173 plen++;
2174 nframes--;
2175 }
2176
2177 td_no++;
2178
2179 if ((td_no == 8) || (nframes == 0)) {
2180 /* remove HS-TD from schedule */
2181 EHCI_REMOVE_HS_TD(td, *pp_last);
2182 pp_last++;
2183
2184 td_no = 0;
2185 td = td->obj_next;
2186 }
2187 }
2188 xfer->aframes = xfer->nframes;
2189 }
2190
2191 /* NOTE: "done" can be run two times in a row,
2192 * from close and from interrupt
2193 */
2194 static void
ehci_device_done(struct usb_xfer * xfer,usb_error_t error)2195 ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2196 {
2197 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2198 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2199
2200 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2201
2202 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2203 xfer, xfer->endpoint, error);
2204
2205 if ((methods == &ehci_device_bulk_methods) ||
2206 (methods == &ehci_device_ctrl_methods)) {
2207 #ifdef USB_DEBUG
2208 if (ehcidebug > 8) {
2209 DPRINTF("nexttog=%d; data after transfer:\n",
2210 xfer->endpoint->toggle_next);
2211 ehci_dump_sqtds(sc,
2212 xfer->td_transfer_first);
2213 }
2214 #endif
2215
2216 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2217 sc->sc_async_p_last);
2218 }
2219 if (methods == &ehci_device_intr_methods) {
2220 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2221 sc->sc_intr_p_last[xfer->qh_pos]);
2222 }
2223 /*
2224 * Only finish isochronous transfers once which will update
2225 * "xfer->frlengths".
2226 */
2227 if (xfer->td_transfer_first &&
2228 xfer->td_transfer_last) {
2229 if (methods == &ehci_device_isoc_fs_methods) {
2230 ehci_isoc_fs_done(sc, xfer);
2231 }
2232 if (methods == &ehci_device_isoc_hs_methods) {
2233 ehci_isoc_hs_done(sc, xfer);
2234 }
2235 xfer->td_transfer_first = NULL;
2236 xfer->td_transfer_last = NULL;
2237 }
2238 /* dequeue transfer and start next transfer */
2239 usbd_transfer_done(xfer, error);
2240 }
2241
2242 /*------------------------------------------------------------------------*
2243 * ehci bulk support
2244 *------------------------------------------------------------------------*/
2245 static void
ehci_device_bulk_open(struct usb_xfer * xfer)2246 ehci_device_bulk_open(struct usb_xfer *xfer)
2247 {
2248 return;
2249 }
2250
2251 static void
ehci_device_bulk_close(struct usb_xfer * xfer)2252 ehci_device_bulk_close(struct usb_xfer *xfer)
2253 {
2254 ehci_device_done(xfer, USB_ERR_CANCELLED);
2255 }
2256
2257 static void
ehci_device_bulk_enter(struct usb_xfer * xfer)2258 ehci_device_bulk_enter(struct usb_xfer *xfer)
2259 {
2260 return;
2261 }
2262
2263 static void
ehci_doorbell_async(struct ehci_softc * sc)2264 ehci_doorbell_async(struct ehci_softc *sc)
2265 {
2266 uint32_t temp;
2267
2268 /*
2269 * XXX Performance quirk: Some Host Controllers have a too low
2270 * interrupt rate. Issue an IAAD to stimulate the Host
2271 * Controller after queueing the BULK transfer.
2272 *
2273 * XXX Force the host controller to refresh any QH caches.
2274 */
2275 temp = EOREAD4(sc, EHCI_USBCMD);
2276 if (!(temp & EHCI_CMD_IAAD))
2277 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2278 }
2279
2280 static void
ehci_device_bulk_start(struct usb_xfer * xfer)2281 ehci_device_bulk_start(struct usb_xfer *xfer)
2282 {
2283 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2284
2285 /* setup TD's and QH */
2286 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2287
2288 /* put transfer on interrupt queue */
2289 ehci_transfer_intr_enqueue(xfer);
2290
2291 /*
2292 * XXX Certain nVidia chipsets choke when using the IAAD
2293 * feature too frequently.
2294 */
2295 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2296 return;
2297
2298 ehci_doorbell_async(sc);
2299 }
2300
2301 struct usb_pipe_methods ehci_device_bulk_methods =
2302 {
2303 .open = ehci_device_bulk_open,
2304 .close = ehci_device_bulk_close,
2305 .enter = ehci_device_bulk_enter,
2306 .start = ehci_device_bulk_start,
2307 };
2308
2309 /*------------------------------------------------------------------------*
2310 * ehci control support
2311 *------------------------------------------------------------------------*/
2312 static void
ehci_device_ctrl_open(struct usb_xfer * xfer)2313 ehci_device_ctrl_open(struct usb_xfer *xfer)
2314 {
2315 return;
2316 }
2317
2318 static void
ehci_device_ctrl_close(struct usb_xfer * xfer)2319 ehci_device_ctrl_close(struct usb_xfer *xfer)
2320 {
2321 ehci_device_done(xfer, USB_ERR_CANCELLED);
2322 }
2323
2324 static void
ehci_device_ctrl_enter(struct usb_xfer * xfer)2325 ehci_device_ctrl_enter(struct usb_xfer *xfer)
2326 {
2327 return;
2328 }
2329
2330 static void
ehci_device_ctrl_start(struct usb_xfer * xfer)2331 ehci_device_ctrl_start(struct usb_xfer *xfer)
2332 {
2333 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2334
2335 /* setup TD's and QH */
2336 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2337
2338 /* put transfer on interrupt queue */
2339 ehci_transfer_intr_enqueue(xfer);
2340 }
2341
2342 struct usb_pipe_methods ehci_device_ctrl_methods =
2343 {
2344 .open = ehci_device_ctrl_open,
2345 .close = ehci_device_ctrl_close,
2346 .enter = ehci_device_ctrl_enter,
2347 .start = ehci_device_ctrl_start,
2348 };
2349
2350 /*------------------------------------------------------------------------*
2351 * ehci interrupt support
2352 *------------------------------------------------------------------------*/
2353 static void
ehci_device_intr_open(struct usb_xfer * xfer)2354 ehci_device_intr_open(struct usb_xfer *xfer)
2355 {
2356 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2357 uint16_t best;
2358 uint16_t bit;
2359 uint16_t x;
2360
2361 usb_hs_bandwidth_alloc(xfer);
2362
2363 /*
2364 * Find the best QH position corresponding to the given interval:
2365 */
2366
2367 best = 0;
2368 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2369 while (bit) {
2370 if (xfer->interval >= bit) {
2371 x = bit;
2372 best = bit;
2373 while (x & bit) {
2374 if (sc->sc_intr_stat[x] <
2375 sc->sc_intr_stat[best]) {
2376 best = x;
2377 }
2378 x++;
2379 }
2380 break;
2381 }
2382 bit >>= 1;
2383 }
2384
2385 sc->sc_intr_stat[best]++;
2386 xfer->qh_pos = best;
2387
2388 DPRINTFN(3, "best=%d interval=%d\n",
2389 best, xfer->interval);
2390 }
2391
2392 static void
ehci_device_intr_close(struct usb_xfer * xfer)2393 ehci_device_intr_close(struct usb_xfer *xfer)
2394 {
2395 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2396
2397 sc->sc_intr_stat[xfer->qh_pos]--;
2398
2399 ehci_device_done(xfer, USB_ERR_CANCELLED);
2400
2401 /* bandwidth must be freed after device done */
2402 usb_hs_bandwidth_free(xfer);
2403 }
2404
2405 static void
ehci_device_intr_enter(struct usb_xfer * xfer)2406 ehci_device_intr_enter(struct usb_xfer *xfer)
2407 {
2408 return;
2409 }
2410
2411 static void
ehci_device_intr_start(struct usb_xfer * xfer)2412 ehci_device_intr_start(struct usb_xfer *xfer)
2413 {
2414 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2415
2416 /* setup TD's and QH */
2417 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2418
2419 /* put transfer on interrupt queue */
2420 ehci_transfer_intr_enqueue(xfer);
2421 }
2422
2423 struct usb_pipe_methods ehci_device_intr_methods =
2424 {
2425 .open = ehci_device_intr_open,
2426 .close = ehci_device_intr_close,
2427 .enter = ehci_device_intr_enter,
2428 .start = ehci_device_intr_start,
2429 };
2430
2431 /*------------------------------------------------------------------------*
2432 * ehci full speed isochronous support
2433 *------------------------------------------------------------------------*/
2434 static void
ehci_device_isoc_fs_open(struct usb_xfer * xfer)2435 ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2436 {
2437 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2438 ehci_sitd_t *td;
2439 uint32_t sitd_portaddr;
2440 uint8_t ds;
2441
2442 sitd_portaddr =
2443 EHCI_SITD_SET_ADDR(xfer->address) |
2444 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2445 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2446 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2447
2448 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2449 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2450
2451 sitd_portaddr = htohc32(sc, sitd_portaddr);
2452
2453 /* initialize all TD's */
2454
2455 for (ds = 0; ds != 2; ds++) {
2456
2457 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2458
2459 td->sitd_portaddr = sitd_portaddr;
2460
2461 /*
2462 * TODO: make some kind of automatic
2463 * SMASK/CMASK selection based on micro-frame
2464 * usage
2465 *
2466 * micro-frame usage (8 microframes per 1ms)
2467 */
2468 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2469
2470 usb_pc_cpu_flush(td->page_cache);
2471 }
2472 }
2473 }
2474
2475 static void
ehci_device_isoc_fs_close(struct usb_xfer * xfer)2476 ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2477 {
2478 ehci_device_done(xfer, USB_ERR_CANCELLED);
2479 }
2480
2481 static void
ehci_device_isoc_fs_enter(struct usb_xfer * xfer)2482 ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2483 {
2484 struct usb_page_search buf_res;
2485 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2486 ehci_sitd_t *td;
2487 ehci_sitd_t *td_last = NULL;
2488 ehci_sitd_t **pp_last;
2489 uint32_t *plen;
2490 uint32_t buf_offset;
2491 uint32_t nframes;
2492 uint32_t temp;
2493 uint32_t sitd_mask;
2494 uint16_t tlen;
2495 uint8_t sa;
2496 uint8_t sb;
2497
2498 #ifdef USB_DEBUG
2499 uint8_t once = 1;
2500
2501 #endif
2502
2503 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2504 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2505
2506 /* get the current frame index */
2507
2508 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2509
2510 /*
2511 * check if the frame index is within the window where the frames
2512 * will be inserted
2513 */
2514 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2515 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2516
2517 if ((xfer->endpoint->is_synced == 0) ||
2518 (buf_offset < xfer->nframes)) {
2519 /*
2520 * If there is data underflow or the pipe queue is empty we
2521 * schedule the transfer a few frames ahead of the current
2522 * frame position. Else two isochronous transfers might
2523 * overlap.
2524 */
2525 xfer->endpoint->isoc_next = (nframes + 3) &
2526 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2527 xfer->endpoint->is_synced = 1;
2528 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2529 }
2530 /*
2531 * compute how many milliseconds the insertion is ahead of the
2532 * current frame position:
2533 */
2534 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2535 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2536
2537 /*
2538 * pre-compute when the isochronous transfer will be finished:
2539 */
2540 xfer->isoc_time_complete =
2541 usb_isoc_time_expand(&sc->sc_bus, nframes) +
2542 buf_offset + xfer->nframes;
2543
2544 /* get the real number of frames */
2545
2546 nframes = xfer->nframes;
2547
2548 buf_offset = 0;
2549
2550 plen = xfer->frlengths;
2551
2552 /* toggle the DMA set we are using */
2553 xfer->flags_int.curr_dma_set ^= 1;
2554
2555 /* get next DMA set */
2556 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2557 xfer->td_transfer_first = td;
2558
2559 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2560
2561 /* store starting position */
2562
2563 xfer->qh_pos = xfer->endpoint->isoc_next;
2564
2565 while (nframes--) {
2566 if (td == NULL) {
2567 panic("%s:%d: out of TD's\n",
2568 __FUNCTION__, __LINE__);
2569 }
2570 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2571 pp_last = &sc->sc_isoc_fs_p_last[0];
2572
2573 /* reuse sitd_portaddr and sitd_back from last transfer */
2574
2575 if (*plen > xfer->max_frame_size) {
2576 #ifdef USB_DEBUG
2577 if (once) {
2578 once = 0;
2579 printf("%s: frame length(%d) exceeds %d "
2580 "bytes (frame truncated)\n",
2581 __FUNCTION__, *plen,
2582 xfer->max_frame_size);
2583 }
2584 #endif
2585 *plen = xfer->max_frame_size;
2586 }
2587
2588 /* allocate a slot */
2589
2590 sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2591 xfer->isoc_time_complete - nframes - 1);
2592
2593 if (sa == 255) {
2594 /*
2595 * Schedule is FULL, set length to zero:
2596 */
2597
2598 *plen = 0;
2599 sa = USB_FS_ISOC_UFRAME_MAX - 1;
2600 }
2601 if (*plen) {
2602 /*
2603 * only call "usbd_get_page()" when we have a
2604 * non-zero length
2605 */
2606 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2607 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2608 buf_offset += *plen;
2609 /*
2610 * NOTE: We need to subtract one from the offset so
2611 * that we are on a valid page!
2612 */
2613 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2614 &buf_res);
2615 temp = buf_res.physaddr & ~0xFFF;
2616 } else {
2617 td->sitd_bp[0] = 0;
2618 temp = 0;
2619 }
2620
2621 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2622 tlen = *plen;
2623 if (tlen <= 188) {
2624 temp |= 1; /* T-count = 1, TP = ALL */
2625 tlen = 1;
2626 } else {
2627 tlen += 187;
2628 tlen /= 188;
2629 temp |= tlen; /* T-count = [1..6] */
2630 temp |= 8; /* TP = Begin */
2631 }
2632
2633 tlen += sa;
2634
2635 if (tlen >= 8) {
2636 sb = 0;
2637 } else {
2638 sb = (1 << tlen);
2639 }
2640
2641 sa = (1 << sa);
2642 sa = (sb - sa) & 0x3F;
2643 sb = 0;
2644 } else {
2645 sb = (-(4 << sa)) & 0xFE;
2646 sa = (1 << sa) & 0x3F;
2647 }
2648
2649 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2650 EHCI_SITD_SET_CMASK(sb));
2651
2652 td->sitd_bp[1] = htohc32(sc, temp);
2653
2654 td->sitd_mask = htohc32(sc, sitd_mask);
2655
2656 if (nframes == 0) {
2657 td->sitd_status = htohc32(sc,
2658 EHCI_SITD_IOC |
2659 EHCI_SITD_ACTIVE |
2660 EHCI_SITD_SET_LEN(*plen));
2661 } else {
2662 td->sitd_status = htohc32(sc,
2663 EHCI_SITD_ACTIVE |
2664 EHCI_SITD_SET_LEN(*plen));
2665 }
2666 usb_pc_cpu_flush(td->page_cache);
2667
2668 #ifdef USB_DEBUG
2669 if (ehcidebug > 15) {
2670 DPRINTF("FS-TD %d\n", nframes);
2671 ehci_dump_sitd(sc, td);
2672 }
2673 #endif
2674 /* insert TD into schedule */
2675 EHCI_APPEND_FS_TD(td, *pp_last);
2676 pp_last++;
2677
2678 plen++;
2679 td_last = td;
2680 td = td->obj_next;
2681 }
2682
2683 xfer->td_transfer_last = td_last;
2684
2685 /* update isoc_next */
2686 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2687 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2688
2689 /*
2690 * We don't allow cancelling of the SPLIT transaction USB FULL
2691 * speed transfer, because it disturbs the bandwidth
2692 * computation algorithm.
2693 */
2694 xfer->flags_int.can_cancel_immed = 0;
2695 }
2696
2697 static void
ehci_device_isoc_fs_start(struct usb_xfer * xfer)2698 ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2699 {
2700 /*
2701 * We don't allow cancelling of the SPLIT transaction USB FULL
2702 * speed transfer, because it disturbs the bandwidth
2703 * computation algorithm.
2704 */
2705 xfer->flags_int.can_cancel_immed = 0;
2706
2707 /* set a default timeout */
2708 if (xfer->timeout == 0)
2709 xfer->timeout = 500; /* ms */
2710
2711 /* put transfer on interrupt queue */
2712 ehci_transfer_intr_enqueue(xfer);
2713 }
2714
2715 struct usb_pipe_methods ehci_device_isoc_fs_methods =
2716 {
2717 .open = ehci_device_isoc_fs_open,
2718 .close = ehci_device_isoc_fs_close,
2719 .enter = ehci_device_isoc_fs_enter,
2720 .start = ehci_device_isoc_fs_start,
2721 };
2722
2723 /*------------------------------------------------------------------------*
2724 * ehci high speed isochronous support
2725 *------------------------------------------------------------------------*/
2726 static void
ehci_device_isoc_hs_open(struct usb_xfer * xfer)2727 ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2728 {
2729 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2730 ehci_itd_t *td;
2731 uint32_t temp;
2732 uint8_t ds;
2733
2734 usb_hs_bandwidth_alloc(xfer);
2735
2736 /* initialize all TD's */
2737
2738 for (ds = 0; ds != 2; ds++) {
2739
2740 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2741
2742 /* set TD inactive */
2743 td->itd_status[0] = 0;
2744 td->itd_status[1] = 0;
2745 td->itd_status[2] = 0;
2746 td->itd_status[3] = 0;
2747 td->itd_status[4] = 0;
2748 td->itd_status[5] = 0;
2749 td->itd_status[6] = 0;
2750 td->itd_status[7] = 0;
2751
2752 /* set endpoint and address */
2753 td->itd_bp[0] = htohc32(sc,
2754 EHCI_ITD_SET_ADDR(xfer->address) |
2755 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2756
2757 temp =
2758 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2759
2760 /* set direction */
2761 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2762 temp |= EHCI_ITD_SET_DIR_IN;
2763 }
2764 /* set maximum packet size */
2765 td->itd_bp[1] = htohc32(sc, temp);
2766
2767 /* set transfer multiplier */
2768 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2769
2770 usb_pc_cpu_flush(td->page_cache);
2771 }
2772 }
2773 }
2774
2775 static void
ehci_device_isoc_hs_close(struct usb_xfer * xfer)2776 ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2777 {
2778 ehci_device_done(xfer, USB_ERR_CANCELLED);
2779
2780 /* bandwidth must be freed after device done */
2781 usb_hs_bandwidth_free(xfer);
2782 }
2783
2784 static void
ehci_device_isoc_hs_enter(struct usb_xfer * xfer)2785 ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2786 {
2787 struct usb_page_search buf_res;
2788 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2789 ehci_itd_t *td;
2790 ehci_itd_t *td_last = NULL;
2791 ehci_itd_t **pp_last;
2792 bus_size_t page_addr;
2793 uint32_t *plen;
2794 uint32_t status;
2795 uint32_t buf_offset;
2796 uint32_t nframes;
2797 uint32_t itd_offset[8 + 1];
2798 uint8_t x;
2799 uint8_t td_no;
2800 uint8_t page_no;
2801 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2802
2803 #ifdef USB_DEBUG
2804 uint8_t once = 1;
2805
2806 #endif
2807
2808 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2809 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2810
2811 /* get the current frame index */
2812
2813 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2814
2815 /*
2816 * check if the frame index is within the window where the frames
2817 * will be inserted
2818 */
2819 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2820 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2821
2822 if ((xfer->endpoint->is_synced == 0) ||
2823 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2824 /*
2825 * If there is data underflow or the pipe queue is empty we
2826 * schedule the transfer a few frames ahead of the current
2827 * frame position. Else two isochronous transfers might
2828 * overlap.
2829 */
2830 xfer->endpoint->isoc_next = (nframes + 3) &
2831 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2832 xfer->endpoint->is_synced = 1;
2833 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2834 }
2835 /*
2836 * compute how many milliseconds the insertion is ahead of the
2837 * current frame position:
2838 */
2839 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2840 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2841
2842 /*
2843 * pre-compute when the isochronous transfer will be finished:
2844 */
2845 xfer->isoc_time_complete =
2846 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2847 (((xfer->nframes << shift) + 7) / 8);
2848
2849 /* get the real number of frames */
2850
2851 nframes = xfer->nframes;
2852
2853 buf_offset = 0;
2854 td_no = 0;
2855
2856 plen = xfer->frlengths;
2857
2858 /* toggle the DMA set we are using */
2859 xfer->flags_int.curr_dma_set ^= 1;
2860
2861 /* get next DMA set */
2862 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2863 xfer->td_transfer_first = td;
2864
2865 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2866
2867 /* store starting position */
2868
2869 xfer->qh_pos = xfer->endpoint->isoc_next;
2870
2871 while (nframes) {
2872 if (td == NULL) {
2873 panic("%s:%d: out of TD's\n",
2874 __FUNCTION__, __LINE__);
2875 }
2876 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2877 pp_last = &sc->sc_isoc_hs_p_last[0];
2878 }
2879 /* range check */
2880 if (*plen > xfer->max_frame_size) {
2881 #ifdef USB_DEBUG
2882 if (once) {
2883 once = 0;
2884 printf("%s: frame length(%d) exceeds %d bytes "
2885 "(frame truncated)\n",
2886 __FUNCTION__, *plen, xfer->max_frame_size);
2887 }
2888 #endif
2889 *plen = xfer->max_frame_size;
2890 }
2891
2892 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2893 status = (EHCI_ITD_SET_LEN(*plen) |
2894 EHCI_ITD_ACTIVE |
2895 EHCI_ITD_SET_PG(0));
2896 td->itd_status[td_no] = htohc32(sc, status);
2897 itd_offset[td_no] = buf_offset;
2898 buf_offset += *plen;
2899 plen++;
2900 nframes --;
2901 } else {
2902 td->itd_status[td_no] = 0; /* not active */
2903 itd_offset[td_no] = buf_offset;
2904 }
2905
2906 td_no++;
2907
2908 if ((td_no == 8) || (nframes == 0)) {
2909
2910 /* the rest of the transfers are not active, if any */
2911 for (x = td_no; x != 8; x++) {
2912 td->itd_status[x] = 0; /* not active */
2913 }
2914
2915 /* check if there is any data to be transferred */
2916 if (itd_offset[0] != buf_offset) {
2917 page_no = 0;
2918 itd_offset[td_no] = buf_offset;
2919
2920 /* get first page offset */
2921 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2922 /* get page address */
2923 page_addr = buf_res.physaddr & ~0xFFF;
2924 /* update page address */
2925 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2926 td->itd_bp[0] |= htohc32(sc, page_addr);
2927
2928 for (x = 0; x != td_no; x++) {
2929 /* set page number and page offset */
2930 status = (EHCI_ITD_SET_PG(page_no) |
2931 (buf_res.physaddr & 0xFFF));
2932 td->itd_status[x] |= htohc32(sc, status);
2933
2934 /* get next page offset */
2935 if (itd_offset[x + 1] == buf_offset) {
2936 /*
2937 * We subtract one so that
2938 * we don't go off the last
2939 * page!
2940 */
2941 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2942 } else {
2943 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2944 }
2945
2946 /* check if we need a new page */
2947 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2948 /* new page needed */
2949 page_addr = buf_res.physaddr & ~0xFFF;
2950 if (page_no == 6) {
2951 panic("%s: too many pages\n", __FUNCTION__);
2952 }
2953 page_no++;
2954 /* update page address */
2955 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2956 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2957 }
2958 }
2959 }
2960 /* set IOC bit if we are complete */
2961 if (nframes == 0) {
2962 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2963 }
2964 usb_pc_cpu_flush(td->page_cache);
2965 #ifdef USB_DEBUG
2966 if (ehcidebug > 15) {
2967 DPRINTF("HS-TD %d\n", nframes);
2968 ehci_dump_itd(sc, td);
2969 }
2970 #endif
2971 /* insert TD into schedule */
2972 EHCI_APPEND_HS_TD(td, *pp_last);
2973 pp_last++;
2974
2975 td_no = 0;
2976 td_last = td;
2977 td = td->obj_next;
2978 }
2979 }
2980
2981 xfer->td_transfer_last = td_last;
2982
2983 /* update isoc_next */
2984 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2985 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2986 }
2987
2988 static void
ehci_device_isoc_hs_start(struct usb_xfer * xfer)2989 ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2990 {
2991 /* put transfer on interrupt queue */
2992 ehci_transfer_intr_enqueue(xfer);
2993 }
2994
2995 struct usb_pipe_methods ehci_device_isoc_hs_methods =
2996 {
2997 .open = ehci_device_isoc_hs_open,
2998 .close = ehci_device_isoc_hs_close,
2999 .enter = ehci_device_isoc_hs_enter,
3000 .start = ehci_device_isoc_hs_start,
3001 };
3002
3003 /*------------------------------------------------------------------------*
3004 * ehci root control support
3005 *------------------------------------------------------------------------*
3006 * Simulate a hardware hub by handling all the necessary requests.
3007 *------------------------------------------------------------------------*/
3008
3009 static const
3010 struct usb_device_descriptor ehci_devd =
3011 {
3012 sizeof(struct usb_device_descriptor),
3013 UDESC_DEVICE, /* type */
3014 {0x00, 0x02}, /* USB version */
3015 UDCLASS_HUB, /* class */
3016 UDSUBCLASS_HUB, /* subclass */
3017 UDPROTO_HSHUBSTT, /* protocol */
3018 64, /* max packet */
3019 {0}, {0}, {0x00, 0x01}, /* device id */
3020 1, 2, 0, /* string indicies */
3021 1 /* # of configurations */
3022 };
3023
3024 static const
3025 struct usb_device_qualifier ehci_odevd =
3026 {
3027 sizeof(struct usb_device_qualifier),
3028 UDESC_DEVICE_QUALIFIER, /* type */
3029 {0x00, 0x02}, /* USB version */
3030 UDCLASS_HUB, /* class */
3031 UDSUBCLASS_HUB, /* subclass */
3032 UDPROTO_FSHUB, /* protocol */
3033 0, /* max packet */
3034 0, /* # of configurations */
3035 0
3036 };
3037
3038 static const struct ehci_config_desc ehci_confd = {
3039 .confd = {
3040 .bLength = sizeof(struct usb_config_descriptor),
3041 .bDescriptorType = UDESC_CONFIG,
3042 .wTotalLength[0] = sizeof(ehci_confd),
3043 .bNumInterface = 1,
3044 .bConfigurationValue = 1,
3045 .iConfiguration = 0,
3046 .bmAttributes = UC_SELF_POWERED,
3047 .bMaxPower = 0 /* max power */
3048 },
3049 .ifcd = {
3050 .bLength = sizeof(struct usb_interface_descriptor),
3051 .bDescriptorType = UDESC_INTERFACE,
3052 .bNumEndpoints = 1,
3053 .bInterfaceClass = UICLASS_HUB,
3054 .bInterfaceSubClass = UISUBCLASS_HUB,
3055 .bInterfaceProtocol = 0,
3056 },
3057 .endpd = {
3058 .bLength = sizeof(struct usb_endpoint_descriptor),
3059 .bDescriptorType = UDESC_ENDPOINT,
3060 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3061 .bmAttributes = UE_INTERRUPT,
3062 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3063 .bInterval = 255,
3064 },
3065 };
3066
3067 static const
3068 struct usb_hub_descriptor ehci_hubd =
3069 {
3070 .bDescLength = 0, /* dynamic length */
3071 .bDescriptorType = UDESC_HUB,
3072 };
3073
3074 static void
ehci_disown(ehci_softc_t * sc,uint16_t index,uint8_t lowspeed)3075 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3076 {
3077 uint32_t port;
3078 uint32_t v;
3079
3080 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3081
3082 port = EHCI_PORTSC(index);
3083 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3084 EOWRITE4(sc, port, v | EHCI_PS_PO);
3085 }
3086
3087 static usb_error_t
ehci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)3088 ehci_roothub_exec(struct usb_device *udev,
3089 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3090 {
3091 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3092 const char *str_ptr;
3093 const void *ptr;
3094 uint32_t port;
3095 uint32_t v;
3096 uint16_t len;
3097 uint16_t i;
3098 uint16_t value;
3099 uint16_t index;
3100 usb_error_t err;
3101
3102 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3103
3104 /* buffer reset */
3105 ptr = (const void *)&sc->sc_hub_desc;
3106 len = 0;
3107 err = 0;
3108
3109 value = UGETW(req->wValue);
3110 index = UGETW(req->wIndex);
3111
3112 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3113 "wValue=0x%04x wIndex=0x%04x\n",
3114 req->bmRequestType, req->bRequest,
3115 UGETW(req->wLength), value, index);
3116
3117 #define C(x,y) ((x) | ((y) << 8))
3118 switch (C(req->bRequest, req->bmRequestType)) {
3119 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3120 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3121 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3122 /*
3123 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3124 * for the integrated root hub.
3125 */
3126 break;
3127 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3128 len = 1;
3129 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3130 break;
3131 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3132 switch (value >> 8) {
3133 case UDESC_DEVICE:
3134 if ((value & 0xff) != 0) {
3135 err = USB_ERR_IOERROR;
3136 goto done;
3137 }
3138 len = sizeof(ehci_devd);
3139 ptr = (const void *)&ehci_devd;
3140 break;
3141 /*
3142 * We can't really operate at another speed,
3143 * but the specification says we need this
3144 * descriptor:
3145 */
3146 case UDESC_DEVICE_QUALIFIER:
3147 if ((value & 0xff) != 0) {
3148 err = USB_ERR_IOERROR;
3149 goto done;
3150 }
3151 len = sizeof(ehci_odevd);
3152 ptr = (const void *)&ehci_odevd;
3153 break;
3154
3155 case UDESC_CONFIG:
3156 if ((value & 0xff) != 0) {
3157 err = USB_ERR_IOERROR;
3158 goto done;
3159 }
3160 len = sizeof(ehci_confd);
3161 ptr = (const void *)&ehci_confd;
3162 break;
3163
3164 case UDESC_STRING:
3165 switch (value & 0xff) {
3166 case 0: /* Language table */
3167 str_ptr = "\001";
3168 break;
3169
3170 case 1: /* Vendor */
3171 str_ptr = sc->sc_vendor;
3172 break;
3173
3174 case 2: /* Product */
3175 str_ptr = "EHCI root HUB";
3176 break;
3177
3178 default:
3179 str_ptr = "";
3180 break;
3181 }
3182
3183 len = usb_make_str_desc(
3184 sc->sc_hub_desc.temp,
3185 sizeof(sc->sc_hub_desc.temp),
3186 str_ptr);
3187 break;
3188 default:
3189 err = USB_ERR_IOERROR;
3190 goto done;
3191 }
3192 break;
3193 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3194 len = 1;
3195 sc->sc_hub_desc.temp[0] = 0;
3196 break;
3197 case C(UR_GET_STATUS, UT_READ_DEVICE):
3198 len = 2;
3199 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3200 break;
3201 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3202 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3203 len = 2;
3204 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3205 break;
3206 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3207 if (value >= EHCI_MAX_DEVICES) {
3208 err = USB_ERR_IOERROR;
3209 goto done;
3210 }
3211 sc->sc_addr = value;
3212 break;
3213 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3214 if ((value != 0) && (value != 1)) {
3215 err = USB_ERR_IOERROR;
3216 goto done;
3217 }
3218 sc->sc_conf = value;
3219 break;
3220 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3221 break;
3222 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3223 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3224 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3225 err = USB_ERR_IOERROR;
3226 goto done;
3227 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3228 break;
3229 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3230 break;
3231 /* Hub requests */
3232 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3233 break;
3234 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3235 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3236
3237 if ((index < 1) ||
3238 (index > sc->sc_noport)) {
3239 err = USB_ERR_IOERROR;
3240 goto done;
3241 }
3242 port = EHCI_PORTSC(index);
3243 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3244 switch (value) {
3245 case UHF_PORT_ENABLE:
3246 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3247 break;
3248 case UHF_PORT_SUSPEND:
3249 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3250
3251 /*
3252 * waking up a High Speed device is rather
3253 * complicated if
3254 */
3255 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3256 }
3257 /* wait 20ms for resume sequence to complete */
3258 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3259
3260 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3261 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3262
3263 /* 4ms settle time */
3264 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3265 break;
3266 case UHF_PORT_POWER:
3267 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3268 break;
3269 case UHF_PORT_TEST:
3270 DPRINTFN(3, "clear port test "
3271 "%d\n", index);
3272 break;
3273 case UHF_PORT_INDICATOR:
3274 DPRINTFN(3, "clear port ind "
3275 "%d\n", index);
3276 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3277 break;
3278 case UHF_C_PORT_CONNECTION:
3279 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3280 break;
3281 case UHF_C_PORT_ENABLE:
3282 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3283 break;
3284 case UHF_C_PORT_SUSPEND:
3285 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3286 break;
3287 case UHF_C_PORT_OVER_CURRENT:
3288 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3289 break;
3290 case UHF_C_PORT_RESET:
3291 sc->sc_isreset = 0;
3292 break;
3293 default:
3294 err = USB_ERR_IOERROR;
3295 goto done;
3296 }
3297 break;
3298 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3299 if ((value & 0xff) != 0) {
3300 err = USB_ERR_IOERROR;
3301 goto done;
3302 }
3303 v = EREAD4(sc, EHCI_HCSPARAMS);
3304
3305 sc->sc_hub_desc.hubd = ehci_hubd;
3306 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3307
3308 if (EHCI_HCS_PPC(v))
3309 i = UHD_PWR_INDIVIDUAL;
3310 else
3311 i = UHD_PWR_NO_SWITCH;
3312
3313 if (EHCI_HCS_P_INDICATOR(v))
3314 i |= UHD_PORT_IND;
3315
3316 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3317 /* XXX can't find out? */
3318 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3319 /* XXX don't know if ports are removable or not */
3320 sc->sc_hub_desc.hubd.bDescLength =
3321 8 + ((sc->sc_noport + 7) / 8);
3322 len = sc->sc_hub_desc.hubd.bDescLength;
3323 break;
3324 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3325 len = 16;
3326 memset(sc->sc_hub_desc.temp, 0, 16);
3327 break;
3328 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3329 DPRINTFN(9, "get port status i=%d\n",
3330 index);
3331 if ((index < 1) ||
3332 (index > sc->sc_noport)) {
3333 err = USB_ERR_IOERROR;
3334 goto done;
3335 }
3336 v = EOREAD4(sc, EHCI_PORTSC(index));
3337 DPRINTFN(9, "port status=0x%04x\n", v);
3338 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3339 if ((v & 0xc000000) == 0x8000000)
3340 i = UPS_HIGH_SPEED;
3341 else if ((v & 0xc000000) == 0x4000000)
3342 i = UPS_LOW_SPEED;
3343 else
3344 i = 0;
3345 } else {
3346 i = UPS_HIGH_SPEED;
3347 }
3348 if (v & EHCI_PS_CS)
3349 i |= UPS_CURRENT_CONNECT_STATUS;
3350 if (v & EHCI_PS_PE)
3351 i |= UPS_PORT_ENABLED;
3352 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3353 i |= UPS_SUSPEND;
3354 if (v & EHCI_PS_OCA)
3355 i |= UPS_OVERCURRENT_INDICATOR;
3356 if (v & EHCI_PS_PR)
3357 i |= UPS_RESET;
3358 if (v & EHCI_PS_PP)
3359 i |= UPS_PORT_POWER;
3360 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3361 i = 0;
3362 if (v & EHCI_PS_CSC)
3363 i |= UPS_C_CONNECT_STATUS;
3364 if (v & EHCI_PS_PEC)
3365 i |= UPS_C_PORT_ENABLED;
3366 if (v & EHCI_PS_OCC)
3367 i |= UPS_C_OVERCURRENT_INDICATOR;
3368 if (v & EHCI_PS_FPR)
3369 i |= UPS_C_SUSPEND;
3370 if (sc->sc_isreset)
3371 i |= UPS_C_PORT_RESET;
3372 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3373 len = sizeof(sc->sc_hub_desc.ps);
3374 break;
3375 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3376 err = USB_ERR_IOERROR;
3377 goto done;
3378 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3379 break;
3380 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3381 if ((index < 1) ||
3382 (index > sc->sc_noport)) {
3383 err = USB_ERR_IOERROR;
3384 goto done;
3385 }
3386 port = EHCI_PORTSC(index);
3387 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3388 switch (value) {
3389 case UHF_PORT_ENABLE:
3390 EOWRITE4(sc, port, v | EHCI_PS_PE);
3391 break;
3392 case UHF_PORT_SUSPEND:
3393 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3394 break;
3395 case UHF_PORT_RESET:
3396 DPRINTFN(6, "reset port %d\n", index);
3397 #ifdef USB_DEBUG
3398 if (ehcinohighspeed) {
3399 /*
3400 * Connect USB device to companion
3401 * controller.
3402 */
3403 ehci_disown(sc, index, 1);
3404 break;
3405 }
3406 #endif
3407 if (EHCI_PS_IS_LOWSPEED(v) &&
3408 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3409 /* Low speed device, give up ownership. */
3410 ehci_disown(sc, index, 1);
3411 break;
3412 }
3413 /* Start reset sequence. */
3414 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3415 EOWRITE4(sc, port, v | EHCI_PS_PR);
3416
3417 /* Wait for reset to complete. */
3418 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3419 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3420
3421 /* Terminate reset sequence. */
3422 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3423 EOWRITE4(sc, port, v);
3424
3425 /* Wait for HC to complete reset. */
3426 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3427 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3428
3429 v = EOREAD4(sc, port);
3430 DPRINTF("ehci after reset, status=0x%08x\n", v);
3431 if (v & EHCI_PS_PR) {
3432 device_printf(sc->sc_bus.bdev,
3433 "port reset timeout\n");
3434 err = USB_ERR_TIMEOUT;
3435 goto done;
3436 }
3437 if (!(v & EHCI_PS_PE) &&
3438 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3439 /* Not a high speed device, give up ownership.*/
3440 ehci_disown(sc, index, 0);
3441 break;
3442 }
3443 sc->sc_isreset = 1;
3444 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3445 index, v);
3446 break;
3447
3448 case UHF_PORT_POWER:
3449 DPRINTFN(3, "set port power %d\n", index);
3450 EOWRITE4(sc, port, v | EHCI_PS_PP);
3451 break;
3452
3453 case UHF_PORT_TEST:
3454 DPRINTFN(3, "set port test %d\n", index);
3455 break;
3456
3457 case UHF_PORT_INDICATOR:
3458 DPRINTFN(3, "set port ind %d\n", index);
3459 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3460 break;
3461
3462 default:
3463 err = USB_ERR_IOERROR;
3464 goto done;
3465 }
3466 break;
3467 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3468 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3469 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3470 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3471 break;
3472 default:
3473 err = USB_ERR_IOERROR;
3474 goto done;
3475 }
3476 done:
3477 *plength = len;
3478 *pptr = ptr;
3479 return (err);
3480 }
3481
3482 static void
ehci_xfer_setup(struct usb_setup_params * parm)3483 ehci_xfer_setup(struct usb_setup_params *parm)
3484 {
3485 struct usb_page_search page_info;
3486 struct usb_page_cache *pc;
3487 ehci_softc_t *sc;
3488 struct usb_xfer *xfer;
3489 void *last_obj;
3490 uint32_t nqtd;
3491 uint32_t nqh;
3492 uint32_t nsitd;
3493 uint32_t nitd;
3494 uint32_t n;
3495
3496 sc = EHCI_BUS2SC(parm->udev->bus);
3497 xfer = parm->curr_xfer;
3498
3499 nqtd = 0;
3500 nqh = 0;
3501 nsitd = 0;
3502 nitd = 0;
3503
3504 /*
3505 * compute maximum number of some structures
3506 */
3507 if (parm->methods == &ehci_device_ctrl_methods) {
3508
3509 /*
3510 * The proof for the "nqtd" formula is illustrated like
3511 * this:
3512 *
3513 * +------------------------------------+
3514 * | |
3515 * | |remainder -> |
3516 * | +-----+---+ |
3517 * | | xxx | x | frm 0 |
3518 * | +-----+---++ |
3519 * | | xxx | xx | frm 1 |
3520 * | +-----+----+ |
3521 * | ... |
3522 * +------------------------------------+
3523 *
3524 * "xxx" means a completely full USB transfer descriptor
3525 *
3526 * "x" and "xx" means a short USB packet
3527 *
3528 * For the remainder of an USB transfer modulo
3529 * "max_data_length" we need two USB transfer descriptors.
3530 * One to transfer the remaining data and one to finalise
3531 * with a zero length packet in case the "force_short_xfer"
3532 * flag is set. We only need two USB transfer descriptors in
3533 * the case where the transfer length of the first one is a
3534 * factor of "max_frame_size". The rest of the needed USB
3535 * transfer descriptors is given by the buffer size divided
3536 * by the maximum data payload.
3537 */
3538 parm->hc_max_packet_size = 0x400;
3539 parm->hc_max_packet_count = 1;
3540 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3541 xfer->flags_int.bdma_enable = 1;
3542
3543 usbd_transfer_setup_sub(parm);
3544
3545 nqh = 1;
3546 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3547 + (xfer->max_data_length / xfer->max_hc_frame_size));
3548
3549 } else if (parm->methods == &ehci_device_bulk_methods) {
3550
3551 parm->hc_max_packet_size = 0x400;
3552 parm->hc_max_packet_count = 1;
3553 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3554 xfer->flags_int.bdma_enable = 1;
3555
3556 usbd_transfer_setup_sub(parm);
3557
3558 nqh = 1;
3559 nqtd = ((2 * xfer->nframes)
3560 + (xfer->max_data_length / xfer->max_hc_frame_size));
3561
3562 } else if (parm->methods == &ehci_device_intr_methods) {
3563
3564 if (parm->speed == USB_SPEED_HIGH) {
3565 parm->hc_max_packet_size = 0x400;
3566 parm->hc_max_packet_count = 3;
3567 } else if (parm->speed == USB_SPEED_FULL) {
3568 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3569 parm->hc_max_packet_count = 1;
3570 } else {
3571 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3572 parm->hc_max_packet_count = 1;
3573 }
3574
3575 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3576 xfer->flags_int.bdma_enable = 1;
3577
3578 usbd_transfer_setup_sub(parm);
3579
3580 nqh = 1;
3581 nqtd = ((2 * xfer->nframes)
3582 + (xfer->max_data_length / xfer->max_hc_frame_size));
3583
3584 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3585
3586 parm->hc_max_packet_size = 0x3FF;
3587 parm->hc_max_packet_count = 1;
3588 parm->hc_max_frame_size = 0x3FF;
3589 xfer->flags_int.bdma_enable = 1;
3590
3591 usbd_transfer_setup_sub(parm);
3592
3593 nsitd = xfer->nframes;
3594
3595 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3596
3597 parm->hc_max_packet_size = 0x400;
3598 parm->hc_max_packet_count = 3;
3599 parm->hc_max_frame_size = 0xC00;
3600 xfer->flags_int.bdma_enable = 1;
3601
3602 usbd_transfer_setup_sub(parm);
3603
3604 nitd = ((xfer->nframes + 7) / 8) <<
3605 usbd_xfer_get_fps_shift(xfer);
3606
3607 } else {
3608
3609 parm->hc_max_packet_size = 0x400;
3610 parm->hc_max_packet_count = 1;
3611 parm->hc_max_frame_size = 0x400;
3612
3613 usbd_transfer_setup_sub(parm);
3614 }
3615
3616 alloc_dma_set:
3617
3618 if (parm->err) {
3619 return;
3620 }
3621 /*
3622 * Allocate queue heads and transfer descriptors
3623 */
3624 last_obj = NULL;
3625
3626 if (usbd_transfer_setup_sub_malloc(
3627 parm, &pc, sizeof(ehci_itd_t),
3628 EHCI_ITD_ALIGN, nitd)) {
3629 parm->err = USB_ERR_NOMEM;
3630 return;
3631 }
3632 if (parm->buf) {
3633 for (n = 0; n != nitd; n++) {
3634 ehci_itd_t *td;
3635
3636 usbd_get_page(pc + n, 0, &page_info);
3637
3638 td = page_info.buffer;
3639
3640 /* init TD */
3641 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3642 td->obj_next = last_obj;
3643 td->page_cache = pc + n;
3644
3645 last_obj = td;
3646
3647 usb_pc_cpu_flush(pc + n);
3648 }
3649 }
3650 if (usbd_transfer_setup_sub_malloc(
3651 parm, &pc, sizeof(ehci_sitd_t),
3652 EHCI_SITD_ALIGN, nsitd)) {
3653 parm->err = USB_ERR_NOMEM;
3654 return;
3655 }
3656 if (parm->buf) {
3657 for (n = 0; n != nsitd; n++) {
3658 ehci_sitd_t *td;
3659
3660 usbd_get_page(pc + n, 0, &page_info);
3661
3662 td = page_info.buffer;
3663
3664 /* init TD */
3665 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3666 td->obj_next = last_obj;
3667 td->page_cache = pc + n;
3668
3669 last_obj = td;
3670
3671 usb_pc_cpu_flush(pc + n);
3672 }
3673 }
3674 if (usbd_transfer_setup_sub_malloc(
3675 parm, &pc, sizeof(ehci_qtd_t),
3676 EHCI_QTD_ALIGN, nqtd)) {
3677 parm->err = USB_ERR_NOMEM;
3678 return;
3679 }
3680 if (parm->buf) {
3681 for (n = 0; n != nqtd; n++) {
3682 ehci_qtd_t *qtd;
3683
3684 usbd_get_page(pc + n, 0, &page_info);
3685
3686 qtd = page_info.buffer;
3687
3688 /* init TD */
3689 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3690 qtd->obj_next = last_obj;
3691 qtd->page_cache = pc + n;
3692
3693 last_obj = qtd;
3694
3695 usb_pc_cpu_flush(pc + n);
3696 }
3697 }
3698 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3699
3700 last_obj = NULL;
3701
3702 if (usbd_transfer_setup_sub_malloc(
3703 parm, &pc, sizeof(ehci_qh_t),
3704 EHCI_QH_ALIGN, nqh)) {
3705 parm->err = USB_ERR_NOMEM;
3706 return;
3707 }
3708 if (parm->buf) {
3709 for (n = 0; n != nqh; n++) {
3710 ehci_qh_t *qh;
3711
3712 usbd_get_page(pc + n, 0, &page_info);
3713
3714 qh = page_info.buffer;
3715
3716 /* init QH */
3717 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3718 qh->obj_next = last_obj;
3719 qh->page_cache = pc + n;
3720
3721 last_obj = qh;
3722
3723 usb_pc_cpu_flush(pc + n);
3724 }
3725 }
3726 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3727
3728 if (!xfer->flags_int.curr_dma_set) {
3729 xfer->flags_int.curr_dma_set = 1;
3730 goto alloc_dma_set;
3731 }
3732 }
3733
3734 static void
ehci_xfer_unsetup(struct usb_xfer * xfer)3735 ehci_xfer_unsetup(struct usb_xfer *xfer)
3736 {
3737 return;
3738 }
3739
3740 static void
ehci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3741 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3742 struct usb_endpoint *ep)
3743 {
3744 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3745
3746 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3747 ep, udev->address,
3748 edesc->bEndpointAddress, udev->flags.usb_mode,
3749 sc->sc_addr);
3750
3751 if (udev->device_index != sc->sc_addr) {
3752
3753 if ((udev->speed != USB_SPEED_HIGH) &&
3754 ((udev->hs_hub_addr == 0) ||
3755 (udev->hs_port_no == 0) ||
3756 (udev->parent_hs_hub == NULL) ||
3757 (udev->parent_hs_hub->hub == NULL))) {
3758 /* We need a transaction translator */
3759 goto done;
3760 }
3761 switch (edesc->bmAttributes & UE_XFERTYPE) {
3762 case UE_CONTROL:
3763 ep->methods = &ehci_device_ctrl_methods;
3764 break;
3765 case UE_INTERRUPT:
3766 ep->methods = &ehci_device_intr_methods;
3767 break;
3768 case UE_ISOCHRONOUS:
3769 if (udev->speed == USB_SPEED_HIGH) {
3770 ep->methods = &ehci_device_isoc_hs_methods;
3771 } else if (udev->speed == USB_SPEED_FULL) {
3772 ep->methods = &ehci_device_isoc_fs_methods;
3773 }
3774 break;
3775 case UE_BULK:
3776 ep->methods = &ehci_device_bulk_methods;
3777 break;
3778 default:
3779 /* do nothing */
3780 break;
3781 }
3782 }
3783 done:
3784 return;
3785 }
3786
3787 static void
ehci_get_dma_delay(struct usb_device * udev,uint32_t * pus)3788 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3789 {
3790 /*
3791 * Wait until the hardware has finished any possible use of
3792 * the transfer descriptor(s) and QH
3793 */
3794 *pus = (1125); /* microseconds */
3795 }
3796
3797 static void
ehci_device_resume(struct usb_device * udev)3798 ehci_device_resume(struct usb_device *udev)
3799 {
3800 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3801 struct usb_xfer *xfer;
3802 struct usb_pipe_methods *methods;
3803
3804 DPRINTF("\n");
3805
3806 USB_BUS_LOCK(udev->bus);
3807
3808 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3809
3810 if (xfer->xroot->udev == udev) {
3811
3812 methods = xfer->endpoint->methods;
3813
3814 if ((methods == &ehci_device_bulk_methods) ||
3815 (methods == &ehci_device_ctrl_methods)) {
3816 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3817 sc->sc_async_p_last);
3818 }
3819 if (methods == &ehci_device_intr_methods) {
3820 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3821 sc->sc_intr_p_last[xfer->qh_pos]);
3822 }
3823 }
3824 }
3825
3826 USB_BUS_UNLOCK(udev->bus);
3827
3828 return;
3829 }
3830
3831 static void
ehci_device_suspend(struct usb_device * udev)3832 ehci_device_suspend(struct usb_device *udev)
3833 {
3834 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3835 struct usb_xfer *xfer;
3836 struct usb_pipe_methods *methods;
3837
3838 DPRINTF("\n");
3839
3840 USB_BUS_LOCK(udev->bus);
3841
3842 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3843
3844 if (xfer->xroot->udev == udev) {
3845
3846 methods = xfer->endpoint->methods;
3847
3848 if ((methods == &ehci_device_bulk_methods) ||
3849 (methods == &ehci_device_ctrl_methods)) {
3850 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3851 sc->sc_async_p_last);
3852 }
3853 if (methods == &ehci_device_intr_methods) {
3854 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3855 sc->sc_intr_p_last[xfer->qh_pos]);
3856 }
3857 }
3858 }
3859
3860 USB_BUS_UNLOCK(udev->bus);
3861 }
3862
3863 static void
ehci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)3864 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3865 {
3866 struct ehci_softc *sc = EHCI_BUS2SC(bus);
3867
3868 switch (state) {
3869 case USB_HW_POWER_SUSPEND:
3870 case USB_HW_POWER_SHUTDOWN:
3871 ehci_suspend(sc);
3872 break;
3873 case USB_HW_POWER_RESUME:
3874 ehci_resume(sc);
3875 break;
3876 default:
3877 break;
3878 }
3879 }
3880
3881 static void
ehci_set_hw_power(struct usb_bus * bus)3882 ehci_set_hw_power(struct usb_bus *bus)
3883 {
3884 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3885 uint32_t temp;
3886 uint32_t flags;
3887
3888 DPRINTF("\n");
3889
3890 USB_BUS_LOCK(bus);
3891
3892 flags = bus->hw_power_state;
3893
3894 temp = EOREAD4(sc, EHCI_USBCMD);
3895
3896 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3897
3898 if (flags & (USB_HW_POWER_CONTROL |
3899 USB_HW_POWER_BULK)) {
3900 DPRINTF("Async is active\n");
3901 temp |= EHCI_CMD_ASE;
3902 }
3903 if (flags & (USB_HW_POWER_INTERRUPT |
3904 USB_HW_POWER_ISOC)) {
3905 DPRINTF("Periodic is active\n");
3906 temp |= EHCI_CMD_PSE;
3907 }
3908 EOWRITE4(sc, EHCI_USBCMD, temp);
3909
3910 USB_BUS_UNLOCK(bus);
3911
3912 return;
3913 }
3914
3915 static void
ehci_start_dma_delay_second(struct usb_xfer * xfer)3916 ehci_start_dma_delay_second(struct usb_xfer *xfer)
3917 {
3918 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3919
3920 DPRINTF("\n");
3921
3922 /* trigger doorbell */
3923 ehci_doorbell_async(sc);
3924
3925 /* give the doorbell 4ms */
3926 usbd_transfer_timeout_ms(xfer,
3927 (void (*)(void *))&usb_dma_delay_done_cb, 4);
3928 }
3929
3930 /*
3931 * Ring the doorbell twice before freeing any DMA descriptors. Some host
3932 * controllers apparently cache the QH descriptors and need a message
3933 * that the cache needs to be discarded.
3934 */
3935 static void
ehci_start_dma_delay(struct usb_xfer * xfer)3936 ehci_start_dma_delay(struct usb_xfer *xfer)
3937 {
3938 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3939
3940 DPRINTF("\n");
3941
3942 /* trigger doorbell */
3943 ehci_doorbell_async(sc);
3944
3945 /* give the doorbell 4ms */
3946 usbd_transfer_timeout_ms(xfer,
3947 (void (*)(void *))&ehci_start_dma_delay_second, 4);
3948 }
3949
3950 struct usb_bus_methods ehci_bus_methods =
3951 {
3952 .endpoint_init = ehci_ep_init,
3953 .xfer_setup = ehci_xfer_setup,
3954 .xfer_unsetup = ehci_xfer_unsetup,
3955 .get_dma_delay = ehci_get_dma_delay,
3956 .device_resume = ehci_device_resume,
3957 .device_suspend = ehci_device_suspend,
3958 .set_hw_power = ehci_set_hw_power,
3959 .set_hw_power_sleep = ehci_set_hw_power_sleep,
3960 .roothub_exec = ehci_roothub_exec,
3961 .xfer_poll = ehci_do_poll,
3962 .start_dma_delay = ehci_start_dma_delay,
3963 };
3964