1 /*-
2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
32 *
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
38 *
39 * Thanks are going to Steve Bauer and Jason Wright.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
45 #include <sys/mbuf.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
50
51 #include <net/if.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57
58 #include <net/bpf.h>
59
60 #include <net/if_vlan_var.h>
61
62 #include <machine/bus.h>
63 #include <machine/resource.h>
64 #include <sys/bus.h>
65 #include <sys/rman.h>
66
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
69
70 #include <dev/mii/mii.h>
71 #include <dev/mii/miivar.h>
72 #include "miidevs.h"
73
74 #include <dev/mii/lxtphyreg.h>
75
76 #include "miibus_if.h"
77
78 #include <dev/tx/if_txreg.h>
79 #include <dev/tx/if_txvar.h>
80
81 MODULE_DEPEND(tx, pci, 1, 1, 1);
82 MODULE_DEPEND(tx, ether, 1, 1, 1);
83 MODULE_DEPEND(tx, miibus, 1, 1, 1);
84
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static void epic_ifstart(struct ifnet *);
89 static void epic_ifstart_locked(struct ifnet *);
90 static void epic_timer(void *);
91 static void epic_init(void *);
92 static void epic_init_locked(epic_softc_t *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
105 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
106 static u_int16_t epic_input_eepromw(epic_softc_t *);
107 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
108 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
109 static u_int8_t epic_read_eepromreg(epic_softc_t *);
110
111 static int epic_read_phy_reg(epic_softc_t *, int, int);
112 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
113
114 static int epic_miibus_readreg(device_t, int, int);
115 static int epic_miibus_writereg(device_t, int, int, int);
116 static void epic_miibus_statchg(device_t);
117 static void epic_miibus_mediainit(device_t);
118
119 static int epic_ifmedia_upd(struct ifnet *);
120 static int epic_ifmedia_upd_locked(struct ifnet *);
121 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
122
123 static int epic_probe(device_t);
124 static int epic_attach(device_t);
125 static int epic_shutdown(device_t);
126 static int epic_detach(device_t);
127 static void epic_release(epic_softc_t *);
128 static struct epic_type *epic_devtype(device_t);
129
130 static device_method_t epic_methods[] = {
131 /* Device interface */
132 DEVMETHOD(device_probe, epic_probe),
133 DEVMETHOD(device_attach, epic_attach),
134 DEVMETHOD(device_detach, epic_detach),
135 DEVMETHOD(device_shutdown, epic_shutdown),
136
137 /* MII interface */
138 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
139 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
140 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
141 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
142
143 { 0, 0 }
144 };
145
146 static driver_t epic_driver = {
147 "tx",
148 epic_methods,
149 sizeof(epic_softc_t)
150 };
151
152 static devclass_t epic_devclass;
153
154 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0);
155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
156
157 static struct epic_type epic_devs[] = {
158 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" },
159 { 0, 0, NULL }
160 };
161
162 static int
epic_probe(device_t dev)163 epic_probe(device_t dev)
164 {
165 struct epic_type *t;
166
167 t = epic_devtype(dev);
168
169 if (t != NULL) {
170 device_set_desc(dev, t->name);
171 return (BUS_PROBE_DEFAULT);
172 }
173
174 return (ENXIO);
175 }
176
177 static struct epic_type *
epic_devtype(device_t dev)178 epic_devtype(device_t dev)
179 {
180 struct epic_type *t;
181
182 t = epic_devs;
183
184 while (t->name != NULL) {
185 if ((pci_get_vendor(dev) == t->ven_id) &&
186 (pci_get_device(dev) == t->dev_id)) {
187 return (t);
188 }
189 t++;
190 }
191 return (NULL);
192 }
193
194 #ifdef EPIC_USEIOSPACE
195 #define EPIC_RES SYS_RES_IOPORT
196 #define EPIC_RID PCIR_BASEIO
197 #else
198 #define EPIC_RES SYS_RES_MEMORY
199 #define EPIC_RID PCIR_BASEMEM
200 #endif
201
202 static void
epic_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)203 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
204 {
205 u_int32_t *addr;
206
207 if (error)
208 return;
209
210 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
211 addr = arg;
212 *addr = segs->ds_addr;
213 }
214
215 /*
216 * Attach routine: map registers, allocate softc, rings and descriptors.
217 * Reset to known state.
218 */
219 static int
epic_attach(device_t dev)220 epic_attach(device_t dev)
221 {
222 struct ifnet *ifp;
223 epic_softc_t *sc;
224 int error;
225 int i, rid, tmp;
226 u_char eaddr[6];
227
228 sc = device_get_softc(dev);
229
230 /* Preinitialize softc structure. */
231 sc->dev = dev;
232 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
233 MTX_DEF);
234
235 /* Fill ifnet structure. */
236 ifp = sc->ifp = if_alloc(IFT_ETHER);
237 if (ifp == NULL) {
238 device_printf(dev, "can not if_alloc()\n");
239 error = ENOSPC;
240 goto fail;
241 }
242 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
243 ifp->if_softc = sc;
244 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
245 ifp->if_ioctl = epic_ifioctl;
246 ifp->if_start = epic_ifstart;
247 ifp->if_init = epic_init;
248 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
249
250 /* Enable busmastering. */
251 pci_enable_busmaster(dev);
252
253 rid = EPIC_RID;
254 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
255 if (sc->res == NULL) {
256 device_printf(dev, "couldn't map ports/memory\n");
257 error = ENXIO;
258 goto fail;
259 }
260
261 /* Allocate interrupt. */
262 rid = 0;
263 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
264 RF_SHAREABLE | RF_ACTIVE);
265 if (sc->irq == NULL) {
266 device_printf(dev, "couldn't map interrupt\n");
267 error = ENXIO;
268 goto fail;
269 }
270
271 /* Allocate DMA tags. */
272 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
273 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
274 MCLBYTES * EPIC_MAX_FRAGS, EPIC_MAX_FRAGS, MCLBYTES, 0, NULL, NULL,
275 &sc->mtag);
276 if (error) {
277 device_printf(dev, "couldn't allocate dma tag\n");
278 goto fail;
279 }
280
281 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
282 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
283 sizeof(struct epic_rx_desc) * RX_RING_SIZE,
284 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, NULL,
285 NULL, &sc->rtag);
286 if (error) {
287 device_printf(dev, "couldn't allocate dma tag\n");
288 goto fail;
289 }
290
291 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
292 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
293 sizeof(struct epic_tx_desc) * TX_RING_SIZE,
294 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0,
295 NULL, NULL, &sc->ttag);
296 if (error) {
297 device_printf(dev, "couldn't allocate dma tag\n");
298 goto fail;
299 }
300
301 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
302 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
303 sizeof(struct epic_frag_list) * TX_RING_SIZE,
304 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0,
305 NULL, NULL, &sc->ftag);
306 if (error) {
307 device_printf(dev, "couldn't allocate dma tag\n");
308 goto fail;
309 }
310
311 /* Allocate DMA safe memory and get the DMA addresses. */
312 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist,
313 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap);
314 if (error) {
315 device_printf(dev, "couldn't allocate dma memory\n");
316 goto fail;
317 }
318 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist,
319 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr,
320 &sc->frag_addr, 0);
321 if (error) {
322 device_printf(dev, "couldn't map dma memory\n");
323 goto fail;
324 }
325 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
326 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap);
327 if (error) {
328 device_printf(dev, "couldn't allocate dma memory\n");
329 goto fail;
330 }
331 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
332 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr,
333 &sc->tx_addr, 0);
334 if (error) {
335 device_printf(dev, "couldn't map dma memory\n");
336 goto fail;
337 }
338 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
339 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap);
340 if (error) {
341 device_printf(dev, "couldn't allocate dma memory\n");
342 goto fail;
343 }
344 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
345 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr,
346 &sc->rx_addr, 0);
347 if (error) {
348 device_printf(dev, "couldn't map dma memory\n");
349 goto fail;
350 }
351
352 /* Bring the chip out of low-power mode. */
353 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
354 DELAY(500);
355
356 /* Workaround for Application Note 7-15. */
357 for (i = 0; i < 16; i++)
358 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
359
360 /* Read MAC address from EEPROM. */
361 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
362 ((u_int16_t *)eaddr)[i] = epic_read_eeprom(sc,i);
363
364 /* Set Non-Volatile Control Register from EEPROM. */
365 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
366
367 /* Set defaults. */
368 sc->tx_threshold = TRANSMIT_THRESHOLD;
369 sc->txcon = TXCON_DEFAULT;
370 sc->miicfg = MIICFG_SMI_ENABLE;
371 sc->phyid = EPIC_UNKN_PHY;
372 sc->serinst = -1;
373
374 /* Fetch card id. */
375 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2);
376 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2);
377
378 if (sc->cardvend != SMC_VENDORID)
379 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend);
380
381 /* Do ifmedia setup. */
382 error = mii_attach(dev, &sc->miibus, ifp, epic_ifmedia_upd,
383 epic_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
384 if (error != 0) {
385 device_printf(dev, "attaching PHYs failed\n");
386 goto fail;
387 }
388
389 /* board type and ... */
390 printf(" type ");
391 for(i = 0x2c; i < 0x32; i++) {
392 tmp = epic_read_eeprom(sc, i);
393 if (' ' == (u_int8_t)tmp)
394 break;
395 printf("%c", (u_int8_t)tmp);
396 tmp >>= 8;
397 if (' ' == (u_int8_t)tmp)
398 break;
399 printf("%c", (u_int8_t)tmp);
400 }
401 printf("\n");
402
403 /* Initialize rings. */
404 if (epic_init_rings(sc)) {
405 device_printf(dev, "failed to init rings\n");
406 error = ENXIO;
407 goto fail;
408 }
409
410 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
411 ifp->if_capabilities |= IFCAP_VLAN_MTU;
412 ifp->if_capenable |= IFCAP_VLAN_MTU;
413 callout_init_mtx(&sc->timer, &sc->lock, 0);
414
415 /* Attach to OS's managers. */
416 ether_ifattach(ifp, eaddr);
417
418 /* Activate our interrupt handler. */
419 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
420 NULL, epic_intr, sc, &sc->sc_ih);
421 if (error) {
422 device_printf(dev, "couldn't set up irq\n");
423 ether_ifdetach(ifp);
424 goto fail;
425 }
426
427 return (0);
428 fail:
429 epic_release(sc);
430 return (error);
431 }
432
433 /*
434 * Free any resources allocated by the driver.
435 */
436 static void
epic_release(epic_softc_t * sc)437 epic_release(epic_softc_t *sc)
438 {
439 if (sc->ifp != NULL)
440 if_free(sc->ifp);
441 if (sc->irq)
442 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
443 if (sc->res)
444 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res);
445 epic_free_rings(sc);
446 if (sc->tx_flist) {
447 bus_dmamap_unload(sc->ftag, sc->fmap);
448 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap);
449 bus_dmamap_destroy(sc->ftag, sc->fmap);
450 }
451 if (sc->tx_desc) {
452 bus_dmamap_unload(sc->ttag, sc->tmap);
453 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap);
454 bus_dmamap_destroy(sc->ttag, sc->tmap);
455 }
456 if (sc->rx_desc) {
457 bus_dmamap_unload(sc->rtag, sc->rmap);
458 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
459 bus_dmamap_destroy(sc->rtag, sc->rmap);
460 }
461 if (sc->mtag)
462 bus_dma_tag_destroy(sc->mtag);
463 if (sc->ftag)
464 bus_dma_tag_destroy(sc->ftag);
465 if (sc->ttag)
466 bus_dma_tag_destroy(sc->ttag);
467 if (sc->rtag)
468 bus_dma_tag_destroy(sc->rtag);
469 mtx_destroy(&sc->lock);
470 }
471
472 /*
473 * Detach driver and free resources.
474 */
475 static int
epic_detach(device_t dev)476 epic_detach(device_t dev)
477 {
478 struct ifnet *ifp;
479 epic_softc_t *sc;
480
481 sc = device_get_softc(dev);
482 ifp = sc->ifp;
483
484 EPIC_LOCK(sc);
485 epic_stop(sc);
486 EPIC_UNLOCK(sc);
487 callout_drain(&sc->timer);
488 ether_ifdetach(ifp);
489 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
490
491 bus_generic_detach(dev);
492 device_delete_child(dev, sc->miibus);
493
494 epic_release(sc);
495 return (0);
496 }
497
498 #undef EPIC_RES
499 #undef EPIC_RID
500
501 /*
502 * Stop all chip I/O so that the kernel's probe routines don't
503 * get confused by errant DMAs when rebooting.
504 */
505 static int
epic_shutdown(device_t dev)506 epic_shutdown(device_t dev)
507 {
508 epic_softc_t *sc;
509
510 sc = device_get_softc(dev);
511
512 EPIC_LOCK(sc);
513 epic_stop(sc);
514 EPIC_UNLOCK(sc);
515 return (0);
516 }
517
518 /*
519 * This is if_ioctl handler.
520 */
521 static int
epic_ifioctl(struct ifnet * ifp,u_long command,caddr_t data)522 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data)
523 {
524 epic_softc_t *sc = ifp->if_softc;
525 struct mii_data *mii;
526 struct ifreq *ifr = (struct ifreq *) data;
527 int error = 0;
528
529 switch (command) {
530 case SIOCSIFMTU:
531 if (ifp->if_mtu == ifr->ifr_mtu)
532 break;
533
534 /* XXX Though the datasheet doesn't imply any
535 * limitations on RX and TX sizes beside max 64Kb
536 * DMA transfer, seems we can't send more then 1600
537 * data bytes per ethernet packet (transmitter hangs
538 * up if more data is sent).
539 */
540 EPIC_LOCK(sc);
541 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
542 ifp->if_mtu = ifr->ifr_mtu;
543 epic_stop(sc);
544 epic_init_locked(sc);
545 } else
546 error = EINVAL;
547 EPIC_UNLOCK(sc);
548 break;
549
550 case SIOCSIFFLAGS:
551 /*
552 * If the interface is marked up and stopped, then start it.
553 * If it is marked down and running, then stop it.
554 */
555 EPIC_LOCK(sc);
556 if (ifp->if_flags & IFF_UP) {
557 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
558 epic_init_locked(sc);
559 EPIC_UNLOCK(sc);
560 break;
561 }
562 } else {
563 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
564 epic_stop(sc);
565 EPIC_UNLOCK(sc);
566 break;
567 }
568 }
569
570 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
571 epic_stop_activity(sc);
572 epic_set_mc_table(sc);
573 epic_set_rx_mode(sc);
574 epic_start_activity(sc);
575 EPIC_UNLOCK(sc);
576 break;
577
578 case SIOCADDMULTI:
579 case SIOCDELMULTI:
580 EPIC_LOCK(sc);
581 epic_set_mc_table(sc);
582 EPIC_UNLOCK(sc);
583 error = 0;
584 break;
585
586 case SIOCSIFMEDIA:
587 case SIOCGIFMEDIA:
588 mii = device_get_softc(sc->miibus);
589 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
590 break;
591
592 default:
593 error = ether_ioctl(ifp, command, data);
594 break;
595 }
596 return (error);
597 }
598
599 static void
epic_dma_map_txbuf(void * arg,bus_dma_segment_t * segs,int nseg,bus_size_t mapsize,int error)600 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
601 bus_size_t mapsize, int error)
602 {
603 struct epic_frag_list *flist;
604 int i;
605
606 if (error)
607 return;
608
609 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments"));
610 flist = arg;
611 /* Fill fragments list. */
612 for (i = 0; i < nseg; i++) {
613 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
614 flist->frag[i].fraglen = segs[i].ds_len;
615 flist->frag[i].fragaddr = segs[i].ds_addr;
616 }
617 flist->numfrags = nseg;
618 }
619
620 static void
epic_dma_map_rxbuf(void * arg,bus_dma_segment_t * segs,int nseg,bus_size_t mapsize,int error)621 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
622 bus_size_t mapsize, int error)
623 {
624 struct epic_rx_desc *desc;
625
626 if (error)
627 return;
628
629 KASSERT(nseg == 1, ("too many DMA segments"));
630 desc = arg;
631 desc->bufaddr = segs->ds_addr;
632 }
633
634 /*
635 * This is if_start handler. It takes mbufs from if_snd queue
636 * and queue them for transmit, one by one, until TX ring become full
637 * or queue become empty.
638 */
639 static void
epic_ifstart(struct ifnet * ifp)640 epic_ifstart(struct ifnet * ifp)
641 {
642 epic_softc_t *sc = ifp->if_softc;
643
644 EPIC_LOCK(sc);
645 epic_ifstart_locked(ifp);
646 EPIC_UNLOCK(sc);
647 }
648
649 static void
epic_ifstart_locked(struct ifnet * ifp)650 epic_ifstart_locked(struct ifnet * ifp)
651 {
652 epic_softc_t *sc = ifp->if_softc;
653 struct epic_tx_buffer *buf;
654 struct epic_tx_desc *desc;
655 struct epic_frag_list *flist;
656 struct mbuf *m0, *m;
657 int error;
658
659 while (sc->pending_txs < TX_RING_SIZE) {
660 buf = sc->tx_buffer + sc->cur_tx;
661 desc = sc->tx_desc + sc->cur_tx;
662 flist = sc->tx_flist + sc->cur_tx;
663
664 /* Get next packet to send. */
665 IF_DEQUEUE(&ifp->if_snd, m0);
666
667 /* If nothing to send, return. */
668 if (m0 == NULL)
669 return;
670
671 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
672 epic_dma_map_txbuf, flist, 0);
673
674 if (error && error != EFBIG) {
675 m_freem(m0);
676 ifp->if_oerrors++;
677 continue;
678 }
679
680 /*
681 * If packet was more than EPIC_MAX_FRAGS parts,
682 * recopy packet to a newly allocated mbuf cluster.
683 */
684 if (error) {
685 m = m_defrag(m0, M_NOWAIT);
686 if (m == NULL) {
687 m_freem(m0);
688 ifp->if_oerrors++;
689 continue;
690 }
691 m_freem(m0);
692 m0 = m;
693
694 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
695 epic_dma_map_txbuf, flist, 0);
696 if (error) {
697 m_freem(m);
698 ifp->if_oerrors++;
699 continue;
700 }
701 }
702 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
703
704 buf->mbuf = m0;
705 sc->pending_txs++;
706 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
707 desc->control = 0x01;
708 desc->txlength =
709 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
710 desc->status = 0x8000;
711 bus_dmamap_sync(sc->ttag, sc->tmap,
712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
713 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
714 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
715
716 /* Set watchdog timer. */
717 sc->tx_timeout = 8;
718
719 BPF_MTAP(ifp, m0);
720 }
721
722 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
723 }
724
725 /*
726 * Synopsis: Finish all received frames.
727 */
728 static void
epic_rx_done(epic_softc_t * sc)729 epic_rx_done(epic_softc_t *sc)
730 {
731 struct ifnet *ifp = sc->ifp;
732 u_int16_t len;
733 struct epic_rx_buffer *buf;
734 struct epic_rx_desc *desc;
735 struct mbuf *m;
736 bus_dmamap_t map;
737 int error;
738
739 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD);
740 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
741 buf = sc->rx_buffer + sc->cur_rx;
742 desc = sc->rx_desc + sc->cur_rx;
743
744 /* Switch to next descriptor. */
745 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK;
746
747 /*
748 * Check for RX errors. This should only happen if
749 * SAVE_ERRORED_PACKETS is set. RX errors generate
750 * RXE interrupt usually.
751 */
752 if ((desc->status & 1) == 0) {
753 ifp->if_ierrors++;
754 desc->status = 0x8000;
755 continue;
756 }
757
758 /* Save packet length and mbuf contained packet. */
759 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
760 len = desc->rxlength - ETHER_CRC_LEN;
761 m = buf->mbuf;
762
763 /* Try to get an mbuf cluster. */
764 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
765 if (buf->mbuf == NULL) {
766 buf->mbuf = m;
767 desc->status = 0x8000;
768 ifp->if_ierrors++;
769 continue;
770 }
771 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
772 m_adj(buf->mbuf, ETHER_ALIGN);
773
774 /* Point to new mbuf, and give descriptor to chip. */
775 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf,
776 epic_dma_map_rxbuf, desc, 0);
777 if (error) {
778 buf->mbuf = m;
779 desc->status = 0x8000;
780 ifp->if_ierrors++;
781 continue;
782 }
783
784 desc->status = 0x8000;
785 bus_dmamap_unload(sc->mtag, buf->map);
786 map = buf->map;
787 buf->map = sc->sparemap;
788 sc->sparemap = map;
789 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
790
791 /* First mbuf in packet holds the ethernet and packet headers */
792 m->m_pkthdr.rcvif = ifp;
793 m->m_pkthdr.len = m->m_len = len;
794
795 /* Give mbuf to OS. */
796 EPIC_UNLOCK(sc);
797 (*ifp->if_input)(ifp, m);
798 EPIC_LOCK(sc);
799
800 /* Successfuly received frame */
801 ifp->if_ipackets++;
802 }
803 bus_dmamap_sync(sc->rtag, sc->rmap,
804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
805 }
806
807 /*
808 * Synopsis: Do last phase of transmission. I.e. if desc is
809 * transmitted, decrease pending_txs counter, free mbuf contained
810 * packet, switch to next descriptor and repeat until no packets
811 * are pending or descriptor is not transmitted yet.
812 */
813 static void
epic_tx_done(epic_softc_t * sc)814 epic_tx_done(epic_softc_t *sc)
815 {
816 struct epic_tx_buffer *buf;
817 struct epic_tx_desc *desc;
818 u_int16_t status;
819
820 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD);
821 while (sc->pending_txs > 0) {
822 buf = sc->tx_buffer + sc->dirty_tx;
823 desc = sc->tx_desc + sc->dirty_tx;
824 status = desc->status;
825
826 /*
827 * If packet is not transmitted, thou followed
828 * packets are not transmitted too.
829 */
830 if (status & 0x8000)
831 break;
832
833 /* Packet is transmitted. Switch to next and free mbuf. */
834 sc->pending_txs--;
835 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
836 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
837 bus_dmamap_unload(sc->mtag, buf->map);
838 m_freem(buf->mbuf);
839 buf->mbuf = NULL;
840
841 /* Check for errors and collisions. */
842 if (status & 0x0001)
843 sc->ifp->if_opackets++;
844 else
845 sc->ifp->if_oerrors++;
846 sc->ifp->if_collisions += (status >> 8) & 0x1F;
847 #ifdef EPIC_DIAG
848 if ((status & 0x1001) == 0x1001)
849 device_printf(sc->dev,
850 "Tx ERROR: excessive coll. number\n");
851 #endif
852 }
853
854 if (sc->pending_txs < TX_RING_SIZE)
855 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
856 bus_dmamap_sync(sc->ttag, sc->tmap,
857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
858 }
859
860 /*
861 * Interrupt function
862 */
863 static void
epic_intr(void * arg)864 epic_intr(void *arg)
865 {
866 epic_softc_t *sc;
867 int status, i;
868
869 sc = arg;
870 i = 4;
871 EPIC_LOCK(sc);
872 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
873 CSR_WRITE_4(sc, INTSTAT, status);
874
875 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
876 epic_rx_done(sc);
877 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
878 #ifdef EPIC_DIAG
879 if (status & INTSTAT_OVW)
880 device_printf(sc->dev, "RX buffer overflow\n");
881 if (status & INTSTAT_RQE)
882 device_printf(sc->dev, "RX FIFO overflow\n");
883 #endif
884 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
885 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
886 sc->ifp->if_ierrors++;
887 }
888 }
889
890 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
891 epic_tx_done(sc);
892 if (sc->ifp->if_snd.ifq_head != NULL)
893 epic_ifstart_locked(sc->ifp);
894 }
895
896 /* Check for rare errors */
897 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
898 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
899 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
900 INTSTAT_APE|INTSTAT_DPE)) {
901 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
902 (status & INTSTAT_PMA) ? "PMA " : "",
903 (status & INTSTAT_PTA) ? "PTA " : "",
904 (status & INTSTAT_APE) ? "APE " : "",
905 (status & INTSTAT_DPE) ? "DPE" : "");
906
907 epic_stop(sc);
908 epic_init_locked(sc);
909 break;
910 }
911
912 if (status & INTSTAT_RXE) {
913 #ifdef EPIC_DIAG
914 device_printf(sc->dev, "CRC/Alignment error\n");
915 #endif
916 sc->ifp->if_ierrors++;
917 }
918
919 if (status & INTSTAT_TXU) {
920 epic_tx_underrun(sc);
921 sc->ifp->if_oerrors++;
922 }
923 }
924 }
925
926 /* If no packets are pending, then no timeouts. */
927 if (sc->pending_txs == 0)
928 sc->tx_timeout = 0;
929 EPIC_UNLOCK(sc);
930 }
931
932 /*
933 * Handle the TX underrun error: increase the TX threshold
934 * and restart the transmitter.
935 */
936 static void
epic_tx_underrun(epic_softc_t * sc)937 epic_tx_underrun(epic_softc_t *sc)
938 {
939 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
940 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
941 #ifdef EPIC_DIAG
942 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
943 #endif
944 } else {
945 sc->tx_threshold += 0x40;
946 #ifdef EPIC_DIAG
947 device_printf(sc->dev,
948 "Tx UNDERRUN: TX threshold increased to %d\n",
949 sc->tx_threshold);
950 #endif
951 }
952
953 /* We must set TXUGO to reset the stuck transmitter. */
954 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
955
956 /* Update the TX threshold */
957 epic_stop_activity(sc);
958 epic_set_tx_mode(sc);
959 epic_start_activity(sc);
960 }
961
962 /*
963 * This function is called once a second when the interface is running
964 * and performs two functions. First, it provides a timer for the mii
965 * to help with autonegotiation. Second, it checks for transmit
966 * timeouts.
967 */
968 static void
epic_timer(void * arg)969 epic_timer(void *arg)
970 {
971 epic_softc_t *sc = arg;
972 struct mii_data *mii;
973 struct ifnet *ifp;
974
975 ifp = sc->ifp;
976 EPIC_ASSERT_LOCKED(sc);
977 if (sc->tx_timeout && --sc->tx_timeout == 0) {
978 device_printf(sc->dev, "device timeout %d packets\n",
979 sc->pending_txs);
980
981 /* Try to finish queued packets. */
982 epic_tx_done(sc);
983
984 /* If not successful. */
985 if (sc->pending_txs > 0) {
986 ifp->if_oerrors += sc->pending_txs;
987
988 /* Reinitialize board. */
989 device_printf(sc->dev, "reinitialization\n");
990 epic_stop(sc);
991 epic_init_locked(sc);
992 } else
993 device_printf(sc->dev,
994 "seems we can continue normaly\n");
995
996 /* Start output. */
997 if (ifp->if_snd.ifq_head)
998 epic_ifstart_locked(ifp);
999 }
1000
1001 mii = device_get_softc(sc->miibus);
1002 mii_tick(mii);
1003
1004 callout_reset(&sc->timer, hz, epic_timer, sc);
1005 }
1006
1007 /*
1008 * Set media options.
1009 */
1010 static int
epic_ifmedia_upd(struct ifnet * ifp)1011 epic_ifmedia_upd(struct ifnet *ifp)
1012 {
1013 epic_softc_t *sc;
1014 int error;
1015
1016 sc = ifp->if_softc;
1017 EPIC_LOCK(sc);
1018 error = epic_ifmedia_upd_locked(ifp);
1019 EPIC_UNLOCK(sc);
1020 return (error);
1021 }
1022
1023 static int
epic_ifmedia_upd_locked(struct ifnet * ifp)1024 epic_ifmedia_upd_locked(struct ifnet *ifp)
1025 {
1026 epic_softc_t *sc;
1027 struct mii_data *mii;
1028 struct ifmedia *ifm;
1029 struct mii_softc *miisc;
1030 int cfg, media;
1031
1032 sc = ifp->if_softc;
1033 mii = device_get_softc(sc->miibus);
1034 ifm = &mii->mii_media;
1035 media = ifm->ifm_cur->ifm_media;
1036
1037 /* Do not do anything if interface is not up. */
1038 if ((ifp->if_flags & IFF_UP) == 0)
1039 return (0);
1040
1041 /*
1042 * Lookup current selected PHY.
1043 */
1044 if (IFM_INST(media) == sc->serinst) {
1045 sc->phyid = EPIC_SERIAL;
1046 sc->physc = NULL;
1047 } else {
1048 /* If we're not selecting serial interface, select MII mode. */
1049 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1050 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1051
1052 /* Default to unknown PHY. */
1053 sc->phyid = EPIC_UNKN_PHY;
1054
1055 /* Lookup selected PHY. */
1056 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1057 if (IFM_INST(media) == miisc->mii_inst) {
1058 sc->physc = miisc;
1059 break;
1060 }
1061 }
1062
1063 /* Identify selected PHY. */
1064 if (sc->physc) {
1065 int id1, id2, model, oui;
1066
1067 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1068 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1069
1070 oui = MII_OUI(id1, id2);
1071 model = MII_MODEL(id2);
1072 switch (oui) {
1073 case MII_OUI_xxQUALSEMI:
1074 if (model == MII_MODEL_xxQUALSEMI_QS6612)
1075 sc->phyid = EPIC_QS6612_PHY;
1076 break;
1077 case MII_OUI_ALTIMA:
1078 if (model == MII_MODEL_ALTIMA_AC101)
1079 sc->phyid = EPIC_AC101_PHY;
1080 break;
1081 case MII_OUI_xxLEVEL1:
1082 if (model == MII_MODEL_xxLEVEL1_LXT970)
1083 sc->phyid = EPIC_LXT970_PHY;
1084 break;
1085 }
1086 }
1087 }
1088
1089 /*
1090 * Do PHY specific card setup.
1091 */
1092
1093 /*
1094 * Call this, to isolate all not selected PHYs and
1095 * set up selected.
1096 */
1097 mii_mediachg(mii);
1098
1099 /* Do our own setup. */
1100 switch (sc->phyid) {
1101 case EPIC_QS6612_PHY:
1102 break;
1103 case EPIC_AC101_PHY:
1104 /* We have to powerup fiber tranceivers. */
1105 if (IFM_SUBTYPE(media) == IFM_100_FX)
1106 sc->miicfg |= MIICFG_694_ENABLE;
1107 else
1108 sc->miicfg &= ~MIICFG_694_ENABLE;
1109 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1110
1111 break;
1112 case EPIC_LXT970_PHY:
1113 /* We have to powerup fiber tranceivers. */
1114 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1115 if (IFM_SUBTYPE(media) == IFM_100_FX)
1116 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1117 else
1118 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1119 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1120
1121 break;
1122 case EPIC_SERIAL:
1123 /* Select serial PHY (10base2/BNC usually). */
1124 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1125 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1126
1127 /* There is no driver to fill this. */
1128 mii->mii_media_active = media;
1129 mii->mii_media_status = 0;
1130
1131 /*
1132 * We need to call this manually as it wasn't called
1133 * in mii_mediachg().
1134 */
1135 epic_miibus_statchg(sc->dev);
1136 break;
1137 default:
1138 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1139 return (EINVAL);
1140 }
1141
1142 return (0);
1143 }
1144
1145 /*
1146 * Report current media status.
1147 */
1148 static void
epic_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1149 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1150 {
1151 epic_softc_t *sc;
1152 struct mii_data *mii;
1153
1154 sc = ifp->if_softc;
1155 mii = device_get_softc(sc->miibus);
1156 EPIC_LOCK(sc);
1157
1158 /* Nothing should be selected if interface is down. */
1159 if ((ifp->if_flags & IFF_UP) == 0) {
1160 ifmr->ifm_active = IFM_NONE;
1161 ifmr->ifm_status = 0;
1162 EPIC_UNLOCK(sc);
1163 return;
1164 }
1165
1166 /* Call underlying pollstat, if not serial PHY. */
1167 if (sc->phyid != EPIC_SERIAL)
1168 mii_pollstat(mii);
1169
1170 /* Simply copy media info. */
1171 ifmr->ifm_active = mii->mii_media_active;
1172 ifmr->ifm_status = mii->mii_media_status;
1173 EPIC_UNLOCK(sc);
1174 }
1175
1176 /*
1177 * Callback routine, called on media change.
1178 */
1179 static void
epic_miibus_statchg(device_t dev)1180 epic_miibus_statchg(device_t dev)
1181 {
1182 epic_softc_t *sc;
1183 struct mii_data *mii;
1184 int media;
1185
1186 sc = device_get_softc(dev);
1187 mii = device_get_softc(sc->miibus);
1188 media = mii->mii_media_active;
1189
1190 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1191
1192 /*
1193 * If we are in full-duplex mode or loopback operation,
1194 * we need to decouple receiver and transmitter.
1195 */
1196 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1197 sc->txcon |= TXCON_FULL_DUPLEX;
1198
1199 /* On some cards we need manualy set fullduplex led. */
1200 if (sc->cardid == SMC9432FTX ||
1201 sc->cardid == SMC9432FTX_SC) {
1202 if (IFM_OPTIONS(media) & IFM_FDX)
1203 sc->miicfg |= MIICFG_694_ENABLE;
1204 else
1205 sc->miicfg &= ~MIICFG_694_ENABLE;
1206
1207 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1208 }
1209
1210 epic_stop_activity(sc);
1211 epic_set_tx_mode(sc);
1212 epic_start_activity(sc);
1213 }
1214
1215 static void
epic_miibus_mediainit(device_t dev)1216 epic_miibus_mediainit(device_t dev)
1217 {
1218 epic_softc_t *sc;
1219 struct mii_data *mii;
1220 struct ifmedia *ifm;
1221 int media;
1222
1223 sc = device_get_softc(dev);
1224 mii = device_get_softc(sc->miibus);
1225 ifm = &mii->mii_media;
1226
1227 /*
1228 * Add Serial Media Interface if present, this applies to
1229 * SMC9432BTX serie.
1230 */
1231 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1232 /* Store its instance. */
1233 sc->serinst = mii->mii_instance++;
1234
1235 /* Add as 10base2/BNC media. */
1236 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1237 ifmedia_add(ifm, media, 0, NULL);
1238
1239 /* Report to user. */
1240 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1241 }
1242 }
1243
1244 /*
1245 * Reset chip and update media.
1246 */
1247 static void
epic_init(void * xsc)1248 epic_init(void *xsc)
1249 {
1250 epic_softc_t *sc = xsc;
1251
1252 EPIC_LOCK(sc);
1253 epic_init_locked(sc);
1254 EPIC_UNLOCK(sc);
1255 }
1256
1257 static void
epic_init_locked(epic_softc_t * sc)1258 epic_init_locked(epic_softc_t *sc)
1259 {
1260 struct ifnet *ifp = sc->ifp;
1261 int i;
1262
1263 /* If interface is already running, then we need not do anything. */
1264 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1265 return;
1266 }
1267
1268 /* Soft reset the chip (we have to power up card before). */
1269 CSR_WRITE_4(sc, GENCTL, 0);
1270 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1271
1272 /*
1273 * Reset takes 15 pci ticks which depends on PCI bus speed.
1274 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1275 */
1276 DELAY(500);
1277
1278 /* Wake up */
1279 CSR_WRITE_4(sc, GENCTL, 0);
1280
1281 /* Workaround for Application Note 7-15 */
1282 for (i = 0; i < 16; i++)
1283 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1284
1285 /* Give rings to EPIC */
1286 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1287 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1288
1289 /* Put node address to EPIC. */
1290 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IF_LLADDR(sc->ifp))[0]);
1291 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IF_LLADDR(sc->ifp))[1]);
1292 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IF_LLADDR(sc->ifp))[2]);
1293
1294 /* Set tx mode, includeing transmit threshold. */
1295 epic_set_tx_mode(sc);
1296
1297 /* Compute and set RXCON. */
1298 epic_set_rx_mode(sc);
1299
1300 /* Set multicast table. */
1301 epic_set_mc_table(sc);
1302
1303 /* Enable interrupts by setting the interrupt mask. */
1304 CSR_WRITE_4(sc, INTMASK,
1305 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1306 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1307 INTSTAT_FATAL);
1308
1309 /* Acknowledge all pending interrupts. */
1310 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1311
1312 /* Enable interrupts, set for PCI read multiple and etc */
1313 CSR_WRITE_4(sc, GENCTL,
1314 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1315 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1316
1317 /* Mark interface running ... */
1318 if (ifp->if_flags & IFF_UP)
1319 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1320 else
1321 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1322
1323 /* ... and free */
1324 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1325
1326 /* Start Rx process */
1327 epic_start_activity(sc);
1328
1329 /* Set appropriate media */
1330 epic_ifmedia_upd_locked(ifp);
1331
1332 callout_reset(&sc->timer, hz, epic_timer, sc);
1333 }
1334
1335 /*
1336 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1337 * access RXCON.
1338 */
1339 static void
epic_set_rx_mode(epic_softc_t * sc)1340 epic_set_rx_mode(epic_softc_t *sc)
1341 {
1342 u_int32_t flags;
1343 u_int32_t rxcon;
1344
1345 flags = sc->ifp->if_flags;
1346 rxcon = RXCON_DEFAULT;
1347
1348 #ifdef EPIC_EARLY_RX
1349 rxcon |= RXCON_EARLY_RX;
1350 #endif
1351
1352 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1353
1354 CSR_WRITE_4(sc, RXCON, rxcon);
1355 }
1356
1357 /*
1358 * Synopsis: Set transmit control register. Chip must be in idle state to
1359 * access TXCON.
1360 */
1361 static void
epic_set_tx_mode(epic_softc_t * sc)1362 epic_set_tx_mode(epic_softc_t *sc)
1363 {
1364
1365 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1366 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1367
1368 CSR_WRITE_4(sc, TXCON, sc->txcon);
1369 }
1370
1371 /*
1372 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1373 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch
1374 * individual frames, multicast filter must be manually programmed).
1375 *
1376 * Note: EPIC must be in idle state.
1377 */
1378 static void
epic_set_mc_table(epic_softc_t * sc)1379 epic_set_mc_table(epic_softc_t *sc)
1380 {
1381 struct ifnet *ifp;
1382 struct ifmultiaddr *ifma;
1383 u_int16_t filter[4];
1384 u_int8_t h;
1385
1386 ifp = sc->ifp;
1387 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1388 CSR_WRITE_4(sc, MC0, 0xFFFF);
1389 CSR_WRITE_4(sc, MC1, 0xFFFF);
1390 CSR_WRITE_4(sc, MC2, 0xFFFF);
1391 CSR_WRITE_4(sc, MC3, 0xFFFF);
1392 return;
1393 }
1394
1395 filter[0] = 0;
1396 filter[1] = 0;
1397 filter[2] = 0;
1398 filter[3] = 0;
1399
1400 if_maddr_rlock(ifp);
1401 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1402 if (ifma->ifma_addr->sa_family != AF_LINK)
1403 continue;
1404 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1405 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1406 filter[h >> 4] |= 1 << (h & 0xF);
1407 }
1408 if_maddr_runlock(ifp);
1409
1410 CSR_WRITE_4(sc, MC0, filter[0]);
1411 CSR_WRITE_4(sc, MC1, filter[1]);
1412 CSR_WRITE_4(sc, MC2, filter[2]);
1413 CSR_WRITE_4(sc, MC3, filter[3]);
1414 }
1415
1416
1417 /*
1418 * Synopsis: Start receive process and transmit one, if they need.
1419 */
1420 static void
epic_start_activity(epic_softc_t * sc)1421 epic_start_activity(epic_softc_t *sc)
1422 {
1423
1424 /* Start rx process. */
1425 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1426 (sc->pending_txs ? COMMAND_TXQUEUED : 0));
1427 }
1428
1429 /*
1430 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1431 * packet needs to be queued to stop Tx DMA.
1432 */
1433 static void
epic_stop_activity(epic_softc_t * sc)1434 epic_stop_activity(epic_softc_t *sc)
1435 {
1436 int status, i;
1437
1438 /* Stop Tx and Rx DMA. */
1439 CSR_WRITE_4(sc, COMMAND,
1440 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1441
1442 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */
1443 for (i = 0; i < 0x1000; i++) {
1444 status = CSR_READ_4(sc, INTSTAT) &
1445 (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1446 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1447 break;
1448 DELAY(1);
1449 }
1450
1451 /* Catch all finished packets. */
1452 epic_rx_done(sc);
1453 epic_tx_done(sc);
1454
1455 status = CSR_READ_4(sc, INTSTAT);
1456
1457 if ((status & INTSTAT_RXIDLE) == 0)
1458 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1459
1460 if ((status & INTSTAT_TXIDLE) == 0)
1461 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1462
1463 /*
1464 * May need to queue one more packet if TQE, this is rare
1465 * but existing case.
1466 */
1467 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1468 (void)epic_queue_last_packet(sc);
1469 }
1470
1471 /*
1472 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1473 * a packet from current descriptor will be copied to internal RAM. We
1474 * compose a dummy packet here and queue it for transmission.
1475 *
1476 * XXX the packet will then be actually sent over network...
1477 */
1478 static int
epic_queue_last_packet(epic_softc_t * sc)1479 epic_queue_last_packet(epic_softc_t *sc)
1480 {
1481 struct epic_tx_desc *desc;
1482 struct epic_frag_list *flist;
1483 struct epic_tx_buffer *buf;
1484 struct mbuf *m0;
1485 int error, i;
1486
1487 device_printf(sc->dev, "queue last packet\n");
1488
1489 desc = sc->tx_desc + sc->cur_tx;
1490 flist = sc->tx_flist + sc->cur_tx;
1491 buf = sc->tx_buffer + sc->cur_tx;
1492
1493 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1494 return (EBUSY);
1495
1496 MGETHDR(m0, M_NOWAIT, MT_DATA);
1497 if (m0 == NULL)
1498 return (ENOBUFS);
1499
1500 /* Prepare mbuf. */
1501 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN);
1502 m0->m_pkthdr.len = m0->m_len;
1503 m0->m_pkthdr.rcvif = sc->ifp;
1504 bzero(mtod(m0, caddr_t), m0->m_len);
1505
1506 /* Fill fragments list. */
1507 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
1508 epic_dma_map_txbuf, flist, 0);
1509 if (error) {
1510 m_freem(m0);
1511 return (error);
1512 }
1513 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
1514
1515 /* Fill in descriptor. */
1516 buf->mbuf = m0;
1517 sc->pending_txs++;
1518 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1519 desc->control = 0x01;
1520 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
1521 desc->status = 0x8000;
1522 bus_dmamap_sync(sc->ttag, sc->tmap,
1523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1524 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1525
1526 /* Launch transmission. */
1527 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1528
1529 /* Wait Tx DMA to stop (for how long??? XXX) */
1530 for (i = 0; i < 1000; i++) {
1531 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1532 break;
1533 DELAY(1);
1534 }
1535
1536 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1537 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1538 else
1539 epic_tx_done(sc);
1540
1541 return (0);
1542 }
1543
1544 /*
1545 * Synopsis: Shut down board and deallocates rings.
1546 */
1547 static void
epic_stop(epic_softc_t * sc)1548 epic_stop(epic_softc_t *sc)
1549 {
1550
1551 EPIC_ASSERT_LOCKED(sc);
1552
1553 sc->tx_timeout = 0;
1554 callout_stop(&sc->timer);
1555
1556 /* Disable interrupts */
1557 CSR_WRITE_4(sc, INTMASK, 0);
1558 CSR_WRITE_4(sc, GENCTL, 0);
1559
1560 /* Try to stop Rx and TX processes */
1561 epic_stop_activity(sc);
1562
1563 /* Reset chip */
1564 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1565 DELAY(1000);
1566
1567 /* Make chip go to bed */
1568 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1569
1570 /* Mark as stopped */
1571 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1572 }
1573
1574 /*
1575 * Synopsis: This function should free all memory allocated for rings.
1576 */
1577 static void
epic_free_rings(epic_softc_t * sc)1578 epic_free_rings(epic_softc_t *sc)
1579 {
1580 int i;
1581
1582 for (i = 0; i < RX_RING_SIZE; i++) {
1583 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1584 struct epic_rx_desc *desc = sc->rx_desc + i;
1585
1586 desc->status = 0;
1587 desc->buflength = 0;
1588 desc->bufaddr = 0;
1589
1590 if (buf->mbuf) {
1591 bus_dmamap_unload(sc->mtag, buf->map);
1592 bus_dmamap_destroy(sc->mtag, buf->map);
1593 m_freem(buf->mbuf);
1594 }
1595 buf->mbuf = NULL;
1596 }
1597
1598 if (sc->sparemap != NULL)
1599 bus_dmamap_destroy(sc->mtag, sc->sparemap);
1600
1601 for (i = 0; i < TX_RING_SIZE; i++) {
1602 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1603 struct epic_tx_desc *desc = sc->tx_desc + i;
1604
1605 desc->status = 0;
1606 desc->buflength = 0;
1607 desc->bufaddr = 0;
1608
1609 if (buf->mbuf) {
1610 bus_dmamap_unload(sc->mtag, buf->map);
1611 bus_dmamap_destroy(sc->mtag, buf->map);
1612 m_freem(buf->mbuf);
1613 }
1614 buf->mbuf = NULL;
1615 }
1616 }
1617
1618 /*
1619 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1620 * Point Tx descs to fragment lists. Check that all descs and fraglists
1621 * are bounded and aligned properly.
1622 */
1623 static int
epic_init_rings(epic_softc_t * sc)1624 epic_init_rings(epic_softc_t *sc)
1625 {
1626 int error, i;
1627
1628 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1629
1630 /* Initialize the RX descriptor ring. */
1631 for (i = 0; i < RX_RING_SIZE; i++) {
1632 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1633 struct epic_rx_desc *desc = sc->rx_desc + i;
1634
1635 desc->status = 0; /* Owned by driver */
1636 desc->next = sc->rx_addr +
1637 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc);
1638
1639 if ((desc->next & 3) ||
1640 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1641 epic_free_rings(sc);
1642 return (EFAULT);
1643 }
1644
1645 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1646 if (buf->mbuf == NULL) {
1647 epic_free_rings(sc);
1648 return (ENOBUFS);
1649 }
1650 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1651 m_adj(buf->mbuf, ETHER_ALIGN);
1652
1653 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1654 if (error) {
1655 epic_free_rings(sc);
1656 return (error);
1657 }
1658 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1659 epic_dma_map_rxbuf, desc, 0);
1660 if (error) {
1661 epic_free_rings(sc);
1662 return (error);
1663 }
1664 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1665
1666 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */
1667 desc->status = 0x8000; /* Set owner bit to NIC */
1668 }
1669 bus_dmamap_sync(sc->rtag, sc->rmap,
1670 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1671
1672 /* Create the spare DMA map. */
1673 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap);
1674 if (error) {
1675 epic_free_rings(sc);
1676 return (error);
1677 }
1678
1679 /* Initialize the TX descriptor ring. */
1680 for (i = 0; i < TX_RING_SIZE; i++) {
1681 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1682 struct epic_tx_desc *desc = sc->tx_desc + i;
1683
1684 desc->status = 0;
1685 desc->next = sc->tx_addr +
1686 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc);
1687
1688 if ((desc->next & 3) ||
1689 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1690 epic_free_rings(sc);
1691 return (EFAULT);
1692 }
1693
1694 buf->mbuf = NULL;
1695 desc->bufaddr = sc->frag_addr +
1696 i * sizeof(struct epic_frag_list);
1697
1698 if ((desc->bufaddr & 3) ||
1699 ((desc->bufaddr & PAGE_MASK) +
1700 sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1701 epic_free_rings(sc);
1702 return (EFAULT);
1703 }
1704
1705 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1706 if (error) {
1707 epic_free_rings(sc);
1708 return (error);
1709 }
1710 }
1711 bus_dmamap_sync(sc->ttag, sc->tmap,
1712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1713 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1714
1715 return (0);
1716 }
1717
1718 /*
1719 * EEPROM operation functions
1720 */
1721 static void
epic_write_eepromreg(epic_softc_t * sc,u_int8_t val)1722 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1723 {
1724 u_int16_t i;
1725
1726 CSR_WRITE_1(sc, EECTL, val);
1727
1728 for (i = 0; i < 0xFF; i++) {
1729 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0)
1730 break;
1731 }
1732 }
1733
1734 static u_int8_t
epic_read_eepromreg(epic_softc_t * sc)1735 epic_read_eepromreg(epic_softc_t *sc)
1736 {
1737
1738 return (CSR_READ_1(sc, EECTL));
1739 }
1740
1741 static u_int8_t
epic_eeprom_clock(epic_softc_t * sc,u_int8_t val)1742 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1743 {
1744
1745 epic_write_eepromreg(sc, val);
1746 epic_write_eepromreg(sc, (val | 0x4));
1747 epic_write_eepromreg(sc, val);
1748
1749 return (epic_read_eepromreg(sc));
1750 }
1751
1752 static void
epic_output_eepromw(epic_softc_t * sc,u_int16_t val)1753 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1754 {
1755 int i;
1756
1757 for (i = 0xF; i >= 0; i--) {
1758 if (val & (1 << i))
1759 epic_eeprom_clock(sc, 0x0B);
1760 else
1761 epic_eeprom_clock(sc, 0x03);
1762 }
1763 }
1764
1765 static u_int16_t
epic_input_eepromw(epic_softc_t * sc)1766 epic_input_eepromw(epic_softc_t *sc)
1767 {
1768 u_int16_t retval = 0;
1769 int i;
1770
1771 for (i = 0xF; i >= 0; i--) {
1772 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1773 retval |= (1 << i);
1774 }
1775
1776 return (retval);
1777 }
1778
1779 static int
epic_read_eeprom(epic_softc_t * sc,u_int16_t loc)1780 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1781 {
1782 u_int16_t dataval;
1783 u_int16_t read_cmd;
1784
1785 epic_write_eepromreg(sc, 3);
1786
1787 if (epic_read_eepromreg(sc) & 0x40)
1788 read_cmd = (loc & 0x3F) | 0x180;
1789 else
1790 read_cmd = (loc & 0xFF) | 0x600;
1791
1792 epic_output_eepromw(sc, read_cmd);
1793
1794 dataval = epic_input_eepromw(sc);
1795
1796 epic_write_eepromreg(sc, 1);
1797
1798 return (dataval);
1799 }
1800
1801 /*
1802 * Here goes MII read/write routines.
1803 */
1804 static int
epic_read_phy_reg(epic_softc_t * sc,int phy,int reg)1805 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1806 {
1807 int i;
1808
1809 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1810
1811 for (i = 0; i < 0x100; i++) {
1812 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1813 break;
1814 DELAY(1);
1815 }
1816
1817 return (CSR_READ_4(sc, MIIDATA));
1818 }
1819
1820 static void
epic_write_phy_reg(epic_softc_t * sc,int phy,int reg,int val)1821 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1822 {
1823 int i;
1824
1825 CSR_WRITE_4(sc, MIIDATA, val);
1826 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1827
1828 for(i = 0; i < 0x100; i++) {
1829 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0)
1830 break;
1831 DELAY(1);
1832 }
1833 }
1834
1835 static int
epic_miibus_readreg(device_t dev,int phy,int reg)1836 epic_miibus_readreg(device_t dev, int phy, int reg)
1837 {
1838 epic_softc_t *sc;
1839
1840 sc = device_get_softc(dev);
1841
1842 return (PHY_READ_2(sc, phy, reg));
1843 }
1844
1845 static int
epic_miibus_writereg(device_t dev,int phy,int reg,int data)1846 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1847 {
1848 epic_softc_t *sc;
1849
1850 sc = device_get_softc(dev);
1851
1852 PHY_WRITE_2(sc, phy, reg, data);
1853
1854 return (0);
1855 }
1856