1 /*-
2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
4 * Copyright (c) 1997,1998 Luigi Rizzo
5 * Copyright (c) 1994,1995 Hannu Savolainen
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #ifdef HAVE_KERNEL_OPTION_HEADERS
31 #include "opt_snd.h"
32 #endif
33
34 #include <dev/sound/pcm/sound.h>
35
36 SND_DECLARE_FILE("$FreeBSD: stable/9/sys/dev/sound/isa/mss.c 193640 2009-06-07 19:12:08Z ariff $");
37
38 /* board-specific include files */
39 #include <dev/sound/isa/mss.h>
40 #include <dev/sound/isa/sb.h>
41 #include <dev/sound/chip.h>
42
43 #include <isa/isavar.h>
44
45 #include "mixer_if.h"
46
47 #define MSS_DEFAULT_BUFSZ (4096)
48 #define MSS_INDEXED_REGS 0x20
49 #define OPL_INDEXED_REGS 0x19
50
51 struct mss_info;
52
53 struct mss_chinfo {
54 struct mss_info *parent;
55 struct pcm_channel *channel;
56 struct snd_dbuf *buffer;
57 int dir;
58 u_int32_t fmt, blksz;
59 };
60
61 struct mss_info {
62 struct resource *io_base; /* primary I/O address for the board */
63 int io_rid;
64 struct resource *conf_base; /* and the opti931 also has a config space */
65 int conf_rid;
66 struct resource *irq;
67 int irq_rid;
68 struct resource *drq1; /* play */
69 int drq1_rid;
70 struct resource *drq2; /* rec */
71 int drq2_rid;
72 void *ih;
73 bus_dma_tag_t parent_dmat;
74 struct mtx *lock;
75
76 char mss_indexed_regs[MSS_INDEXED_REGS];
77 char opl_indexed_regs[OPL_INDEXED_REGS];
78 int bd_id; /* used to hold board-id info, eg. sb version,
79 * mss codec type, etc. etc.
80 */
81 int opti_offset; /* offset from config_base for opti931 */
82 u_long bd_flags; /* board-specific flags */
83 int optibase; /* base address for OPTi9xx config */
84 struct resource *indir; /* Indirect register index address */
85 int indir_rid;
86 int password; /* password for opti9xx cards */
87 int passwdreg; /* password register */
88 unsigned int bufsize;
89 struct mss_chinfo pch, rch;
90 };
91
92 static int mss_probe(device_t dev);
93 static int mss_attach(device_t dev);
94
95 static driver_intr_t mss_intr;
96
97 /* prototypes for local functions */
98 static int mss_detect(device_t dev, struct mss_info *mss);
99 #ifndef PC98
100 static int opti_detect(device_t dev, struct mss_info *mss);
101 #endif
102 static char *ymf_test(device_t dev, struct mss_info *mss);
103 static void ad_unmute(struct mss_info *mss);
104
105 /* mixer set funcs */
106 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
107 static int mss_set_recsrc(struct mss_info *mss, int mask);
108
109 /* io funcs */
110 static int ad_wait_init(struct mss_info *mss, int x);
111 static int ad_read(struct mss_info *mss, int reg);
112 static void ad_write(struct mss_info *mss, int reg, u_char data);
113 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
114 static void ad_enter_MCE(struct mss_info *mss);
115 static void ad_leave_MCE(struct mss_info *mss);
116
117 /* OPTi-specific functions */
118 static void opti_write(struct mss_info *mss, u_char reg,
119 u_char data);
120 #ifndef PC98
121 static u_char opti_read(struct mss_info *mss, u_char reg);
122 #endif
123 static int opti_init(device_t dev, struct mss_info *mss);
124
125 /* io primitives */
126 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
127 static u_char conf_rd(struct mss_info *mss, u_char reg);
128
129 static int pnpmss_probe(device_t dev);
130 static int pnpmss_attach(device_t dev);
131
132 static driver_intr_t opti931_intr;
133
134 static u_int32_t mss_fmt[] = {
135 SND_FORMAT(AFMT_U8, 1, 0),
136 SND_FORMAT(AFMT_U8, 2, 0),
137 SND_FORMAT(AFMT_S16_LE, 1, 0),
138 SND_FORMAT(AFMT_S16_LE, 2, 0),
139 SND_FORMAT(AFMT_MU_LAW, 1, 0),
140 SND_FORMAT(AFMT_MU_LAW, 2, 0),
141 SND_FORMAT(AFMT_A_LAW, 1, 0),
142 SND_FORMAT(AFMT_A_LAW, 2, 0),
143 0
144 };
145 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
146
147 static u_int32_t guspnp_fmt[] = {
148 SND_FORMAT(AFMT_U8, 1, 0),
149 SND_FORMAT(AFMT_U8, 2, 0),
150 SND_FORMAT(AFMT_S16_LE, 1, 0),
151 SND_FORMAT(AFMT_S16_LE, 2, 0),
152 SND_FORMAT(AFMT_A_LAW, 1, 0),
153 SND_FORMAT(AFMT_A_LAW, 2, 0),
154 0
155 };
156 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
157
158 static u_int32_t opti931_fmt[] = {
159 SND_FORMAT(AFMT_U8, 1, 0),
160 SND_FORMAT(AFMT_U8, 2, 0),
161 SND_FORMAT(AFMT_S16_LE, 1, 0),
162 SND_FORMAT(AFMT_S16_LE, 2, 0),
163 0
164 };
165 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
166
167 #define MD_AD1848 0x91
168 #define MD_AD1845 0x92
169 #define MD_CS42XX 0xA1
170 #define MD_CS423X 0xA2
171 #define MD_OPTI930 0xB0
172 #define MD_OPTI931 0xB1
173 #define MD_OPTI925 0xB2
174 #define MD_OPTI924 0xB3
175 #define MD_GUSPNP 0xB8
176 #define MD_GUSMAX 0xB9
177 #define MD_YM0020 0xC1
178 #define MD_VIVO 0xD1
179
180 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
181
182 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
183
184 static void
mss_lock(struct mss_info * mss)185 mss_lock(struct mss_info *mss)
186 {
187 snd_mtxlock(mss->lock);
188 }
189
190 static void
mss_unlock(struct mss_info * mss)191 mss_unlock(struct mss_info *mss)
192 {
193 snd_mtxunlock(mss->lock);
194 }
195
196 static int
port_rd(struct resource * port,int off)197 port_rd(struct resource *port, int off)
198 {
199 if (port)
200 return bus_space_read_1(rman_get_bustag(port),
201 rman_get_bushandle(port),
202 off);
203 else
204 return -1;
205 }
206
207 static void
port_wr(struct resource * port,int off,u_int8_t data)208 port_wr(struct resource *port, int off, u_int8_t data)
209 {
210 if (port)
211 bus_space_write_1(rman_get_bustag(port),
212 rman_get_bushandle(port),
213 off, data);
214 }
215
216 static int
io_rd(struct mss_info * mss,int reg)217 io_rd(struct mss_info *mss, int reg)
218 {
219 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
220 return port_rd(mss->io_base, reg);
221 }
222
223 static void
io_wr(struct mss_info * mss,int reg,u_int8_t data)224 io_wr(struct mss_info *mss, int reg, u_int8_t data)
225 {
226 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
227 port_wr(mss->io_base, reg, data);
228 }
229
230 static void
conf_wr(struct mss_info * mss,u_char reg,u_char value)231 conf_wr(struct mss_info *mss, u_char reg, u_char value)
232 {
233 port_wr(mss->conf_base, 0, reg);
234 port_wr(mss->conf_base, 1, value);
235 }
236
237 static u_char
conf_rd(struct mss_info * mss,u_char reg)238 conf_rd(struct mss_info *mss, u_char reg)
239 {
240 port_wr(mss->conf_base, 0, reg);
241 return port_rd(mss->conf_base, 1);
242 }
243
244 static void
opti_wr(struct mss_info * mss,u_char reg,u_char value)245 opti_wr(struct mss_info *mss, u_char reg, u_char value)
246 {
247 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
248 port_wr(mss->conf_base, mss->opti_offset + 1, value);
249 }
250
251 static u_char
opti_rd(struct mss_info * mss,u_char reg)252 opti_rd(struct mss_info *mss, u_char reg)
253 {
254 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
255 return port_rd(mss->conf_base, mss->opti_offset + 1);
256 }
257
258 static void
gus_wr(struct mss_info * mss,u_char reg,u_char value)259 gus_wr(struct mss_info *mss, u_char reg, u_char value)
260 {
261 port_wr(mss->conf_base, 3, reg);
262 port_wr(mss->conf_base, 5, value);
263 }
264
265 static u_char
gus_rd(struct mss_info * mss,u_char reg)266 gus_rd(struct mss_info *mss, u_char reg)
267 {
268 port_wr(mss->conf_base, 3, reg);
269 return port_rd(mss->conf_base, 5);
270 }
271
272 static void
mss_release_resources(struct mss_info * mss,device_t dev)273 mss_release_resources(struct mss_info *mss, device_t dev)
274 {
275 if (mss->irq) {
276 if (mss->ih)
277 bus_teardown_intr(dev, mss->irq, mss->ih);
278 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
279 mss->irq);
280 mss->irq = 0;
281 }
282 if (mss->drq2) {
283 if (mss->drq2 != mss->drq1) {
284 isa_dma_release(rman_get_start(mss->drq2));
285 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
286 mss->drq2);
287 }
288 mss->drq2 = 0;
289 }
290 if (mss->drq1) {
291 isa_dma_release(rman_get_start(mss->drq1));
292 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
293 mss->drq1);
294 mss->drq1 = 0;
295 }
296 if (mss->io_base) {
297 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
298 mss->io_base);
299 mss->io_base = 0;
300 }
301 if (mss->conf_base) {
302 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
303 mss->conf_base);
304 mss->conf_base = 0;
305 }
306 if (mss->indir) {
307 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
308 mss->indir);
309 mss->indir = 0;
310 }
311 if (mss->parent_dmat) {
312 bus_dma_tag_destroy(mss->parent_dmat);
313 mss->parent_dmat = 0;
314 }
315 if (mss->lock) snd_mtxfree(mss->lock);
316
317 free(mss, M_DEVBUF);
318 }
319
320 static int
mss_alloc_resources(struct mss_info * mss,device_t dev)321 mss_alloc_resources(struct mss_info *mss, device_t dev)
322 {
323 int pdma, rdma, ok = 1;
324 if (!mss->io_base)
325 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
326 &mss->io_rid, RF_ACTIVE);
327 if (!mss->irq)
328 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
329 &mss->irq_rid, RF_ACTIVE);
330 if (!mss->drq1)
331 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
332 &mss->drq1_rid,
333 RF_ACTIVE);
334 if (mss->conf_rid >= 0 && !mss->conf_base)
335 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
336 &mss->conf_rid,
337 RF_ACTIVE);
338 if (mss->drq2_rid >= 0 && !mss->drq2)
339 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
340 &mss->drq2_rid,
341 RF_ACTIVE);
342
343 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
344 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
345 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
346
347 if (ok) {
348 pdma = rman_get_start(mss->drq1);
349 isa_dma_acquire(pdma);
350 isa_dmainit(pdma, mss->bufsize);
351 mss->bd_flags &= ~BD_F_DUPLEX;
352 if (mss->drq2) {
353 rdma = rman_get_start(mss->drq2);
354 isa_dma_acquire(rdma);
355 isa_dmainit(rdma, mss->bufsize);
356 mss->bd_flags |= BD_F_DUPLEX;
357 } else mss->drq2 = mss->drq1;
358 }
359 return ok;
360 }
361
362 /*
363 * The various mixers use a variety of bitmasks etc. The Voxware
364 * driver had a very nice technique to describe a mixer and interface
365 * to it. A table defines, for each channel, which register, bits,
366 * offset, polarity to use. This procedure creates the new value
367 * using the table and the old value.
368 */
369
370 static void
change_bits(mixer_tab * t,u_char * regval,int dev,int chn,int newval)371 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
372 {
373 u_char mask;
374 int shift;
375
376 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
377 "r %d p %d bit %d off %d\n",
378 dev, chn, newval, *regval,
379 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
380 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
381
382 if ( (*t)[dev][chn].polarity == 1) /* reverse */
383 newval = 100 - newval ;
384
385 mask = (1 << (*t)[dev][chn].nbits) - 1;
386 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
387 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
388
389 *regval &= ~(mask << shift); /* Filter out the previous value */
390 *regval |= (newval & mask) << shift; /* Set the new value */
391 }
392
393 /* -------------------------------------------------------------------- */
394 /* only one source can be set... */
395 static int
mss_set_recsrc(struct mss_info * mss,int mask)396 mss_set_recsrc(struct mss_info *mss, int mask)
397 {
398 u_char recdev;
399
400 switch (mask) {
401 case SOUND_MASK_LINE:
402 case SOUND_MASK_LINE3:
403 recdev = 0;
404 break;
405
406 case SOUND_MASK_CD:
407 case SOUND_MASK_LINE1:
408 recdev = 0x40;
409 break;
410
411 case SOUND_MASK_IMIX:
412 recdev = 0xc0;
413 break;
414
415 case SOUND_MASK_MIC:
416 default:
417 mask = SOUND_MASK_MIC;
418 recdev = 0x80;
419 }
420 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
421 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
422 return mask;
423 }
424
425 /* there are differences in the mixer depending on the actual sound card. */
426 static int
mss_mixer_set(struct mss_info * mss,int dev,int left,int right)427 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
428 {
429 int regoffs;
430 mixer_tab *mix_d;
431 u_char old, val;
432
433 switch (mss->bd_id) {
434 case MD_OPTI931:
435 mix_d = &opti931_devices;
436 break;
437 case MD_OPTI930:
438 mix_d = &opti930_devices;
439 break;
440 default:
441 mix_d = &mix_devices;
442 }
443
444 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
445 DEB(printf("nbits = 0 for dev %d\n", dev));
446 return -1;
447 }
448
449 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
450
451 /* Set the left channel */
452
453 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
454 old = val = ad_read(mss, regoffs);
455 /* if volume is 0, mute chan. Otherwise, unmute. */
456 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
457 change_bits(mix_d, &val, dev, LEFT_CHN, left);
458 ad_write(mss, regoffs, val);
459
460 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
461 dev, regoffs, old, val));
462
463 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
464 /* Set the right channel */
465 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
466 old = val = ad_read(mss, regoffs);
467 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
468 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
469 ad_write(mss, regoffs, val);
470
471 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
472 dev, regoffs, old, val));
473 }
474 return 0; /* success */
475 }
476
477 /* -------------------------------------------------------------------- */
478
479 static int
mssmix_init(struct snd_mixer * m)480 mssmix_init(struct snd_mixer *m)
481 {
482 struct mss_info *mss = mix_getdevinfo(m);
483
484 mix_setdevs(m, MODE2_MIXER_DEVICES);
485 mix_setrecdevs(m, MSS_REC_DEVICES);
486 switch(mss->bd_id) {
487 case MD_OPTI930:
488 mix_setdevs(m, OPTI930_MIXER_DEVICES);
489 break;
490
491 case MD_OPTI931:
492 mix_setdevs(m, OPTI931_MIXER_DEVICES);
493 mss_lock(mss);
494 ad_write(mss, 20, 0x88);
495 ad_write(mss, 21, 0x88);
496 mss_unlock(mss);
497 break;
498
499 case MD_AD1848:
500 mix_setdevs(m, MODE1_MIXER_DEVICES);
501 break;
502
503 case MD_GUSPNP:
504 case MD_GUSMAX:
505 /* this is only necessary in mode 3 ... */
506 mss_lock(mss);
507 ad_write(mss, 22, 0x88);
508 ad_write(mss, 23, 0x88);
509 mss_unlock(mss);
510 break;
511 }
512 return 0;
513 }
514
515 static int
mssmix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)516 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
517 {
518 struct mss_info *mss = mix_getdevinfo(m);
519
520 mss_lock(mss);
521 mss_mixer_set(mss, dev, left, right);
522 mss_unlock(mss);
523
524 return left | (right << 8);
525 }
526
527 static u_int32_t
mssmix_setrecsrc(struct snd_mixer * m,u_int32_t src)528 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
529 {
530 struct mss_info *mss = mix_getdevinfo(m);
531
532 mss_lock(mss);
533 src = mss_set_recsrc(mss, src);
534 mss_unlock(mss);
535 return src;
536 }
537
538 static kobj_method_t mssmix_mixer_methods[] = {
539 KOBJMETHOD(mixer_init, mssmix_init),
540 KOBJMETHOD(mixer_set, mssmix_set),
541 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
542 KOBJMETHOD_END
543 };
544 MIXER_DECLARE(mssmix_mixer);
545
546 /* -------------------------------------------------------------------- */
547
548 static int
ymmix_init(struct snd_mixer * m)549 ymmix_init(struct snd_mixer *m)
550 {
551 struct mss_info *mss = mix_getdevinfo(m);
552
553 mssmix_init(m);
554 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
555 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
556 /* Set master volume */
557 mss_lock(mss);
558 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
559 conf_wr(mss, OPL3SAx_VOLUMER, 7);
560 mss_unlock(mss);
561
562 return 0;
563 }
564
565 static int
ymmix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)566 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
567 {
568 struct mss_info *mss = mix_getdevinfo(m);
569 int t, l, r;
570
571 mss_lock(mss);
572 switch (dev) {
573 case SOUND_MIXER_VOLUME:
574 if (left) t = 15 - (left * 15) / 100;
575 else t = 0x80; /* mute */
576 conf_wr(mss, OPL3SAx_VOLUMEL, t);
577 if (right) t = 15 - (right * 15) / 100;
578 else t = 0x80; /* mute */
579 conf_wr(mss, OPL3SAx_VOLUMER, t);
580 break;
581
582 case SOUND_MIXER_MIC:
583 t = left;
584 if (left) t = 31 - (left * 31) / 100;
585 else t = 0x80; /* mute */
586 conf_wr(mss, OPL3SAx_MIC, t);
587 break;
588
589 case SOUND_MIXER_BASS:
590 l = (left * 7) / 100;
591 r = (right * 7) / 100;
592 t = (r << 4) | l;
593 conf_wr(mss, OPL3SAx_BASS, t);
594 break;
595
596 case SOUND_MIXER_TREBLE:
597 l = (left * 7) / 100;
598 r = (right * 7) / 100;
599 t = (r << 4) | l;
600 conf_wr(mss, OPL3SAx_TREBLE, t);
601 break;
602
603 default:
604 mss_mixer_set(mss, dev, left, right);
605 }
606 mss_unlock(mss);
607
608 return left | (right << 8);
609 }
610
611 static u_int32_t
ymmix_setrecsrc(struct snd_mixer * m,u_int32_t src)612 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
613 {
614 struct mss_info *mss = mix_getdevinfo(m);
615 mss_lock(mss);
616 src = mss_set_recsrc(mss, src);
617 mss_unlock(mss);
618 return src;
619 }
620
621 static kobj_method_t ymmix_mixer_methods[] = {
622 KOBJMETHOD(mixer_init, ymmix_init),
623 KOBJMETHOD(mixer_set, ymmix_set),
624 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
625 KOBJMETHOD_END
626 };
627 MIXER_DECLARE(ymmix_mixer);
628
629 /* -------------------------------------------------------------------- */
630 /*
631 * XXX This might be better off in the gusc driver.
632 */
633 static void
gusmax_setup(struct mss_info * mss,device_t dev,struct resource * alt)634 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
635 {
636 static const unsigned char irq_bits[16] = {
637 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
638 };
639 static const unsigned char dma_bits[8] = {
640 0, 1, 0, 2, 0, 3, 4, 5
641 };
642 device_t parent = device_get_parent(dev);
643 unsigned char irqctl, dmactl;
644 int s;
645
646 s = splhigh();
647
648 port_wr(alt, 0x0f, 0x05);
649 port_wr(alt, 0x00, 0x0c);
650 port_wr(alt, 0x0b, 0x00);
651
652 port_wr(alt, 0x0f, 0x00);
653
654 irqctl = irq_bits[isa_get_irq(parent)];
655 /* Share the IRQ with the MIDI driver. */
656 irqctl |= 0x40;
657 dmactl = dma_bits[isa_get_drq(parent)];
658 if (device_get_flags(parent) & DV_F_DUAL_DMA)
659 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
660 << 3;
661
662 /*
663 * Set the DMA and IRQ control latches.
664 */
665 port_wr(alt, 0x00, 0x0c);
666 port_wr(alt, 0x0b, dmactl | 0x80);
667 port_wr(alt, 0x00, 0x4c);
668 port_wr(alt, 0x0b, irqctl);
669
670 port_wr(alt, 0x00, 0x0c);
671 port_wr(alt, 0x0b, dmactl);
672 port_wr(alt, 0x00, 0x4c);
673 port_wr(alt, 0x0b, irqctl);
674
675 port_wr(mss->conf_base, 2, 0);
676 port_wr(alt, 0x00, 0x0c);
677 port_wr(mss->conf_base, 2, 0);
678
679 splx(s);
680 }
681
682 static int
mss_init(struct mss_info * mss,device_t dev)683 mss_init(struct mss_info *mss, device_t dev)
684 {
685 u_char r6, r9;
686 struct resource *alt;
687 int rid, tmp;
688
689 mss->bd_flags |= BD_F_MCE_BIT;
690 switch(mss->bd_id) {
691 case MD_OPTI931:
692 /*
693 * The MED3931 v.1.0 allocates 3 bytes for the config
694 * space, whereas v.2.0 allocates 4 bytes. What I know
695 * for sure is that the upper two ports must be used,
696 * and they should end on a boundary of 4 bytes. So I
697 * need the following trick.
698 */
699 mss->opti_offset =
700 (rman_get_start(mss->conf_base) & ~3) + 2
701 - rman_get_start(mss->conf_base);
702 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
703 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
704 ad_write(mss, 10, 2); /* enable interrupts */
705 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
706 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
707 break;
708
709 case MD_GUSPNP:
710 case MD_GUSMAX:
711 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
712 DELAY(1000 * 30);
713 /* release reset and enable DAC */
714 gus_wr(mss, 0x4c /* _URSTI */, 3);
715 DELAY(1000 * 30);
716 /* end of reset */
717
718 rid = 0;
719 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
720 RF_ACTIVE);
721 if (alt == NULL) {
722 printf("XXX couldn't init GUS PnP/MAX\n");
723 break;
724 }
725 port_wr(alt, 0, 0xC); /* enable int and dma */
726 if (mss->bd_id == MD_GUSMAX)
727 gusmax_setup(mss, dev, alt);
728 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
729
730 /*
731 * unmute left & right line. Need to go in mode3, unmute,
732 * and back to mode 2
733 */
734 tmp = ad_read(mss, 0x0c);
735 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
736 ad_write(mss, 0x19, 0); /* unmute left */
737 ad_write(mss, 0x1b, 0); /* unmute right */
738 ad_write(mss, 0x0c, tmp); /* restore old mode */
739
740 /* send codec interrupts on irq1 and only use that one */
741 gus_wr(mss, 0x5a, 0x4f);
742
743 /* enable access to hidden regs */
744 tmp = gus_rd(mss, 0x5b /* IVERI */);
745 gus_wr(mss, 0x5b, tmp | 1);
746 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
747 break;
748
749 case MD_YM0020:
750 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
751 r6 = conf_rd(mss, OPL3SAx_DMACONF);
752 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
753 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
754 /* yamaha - set volume to max */
755 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
756 conf_wr(mss, OPL3SAx_VOLUMER, 0);
757 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
758 break;
759 }
760 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
761 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
762 ad_enter_MCE(mss);
763 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
764 ad_leave_MCE(mss);
765 ad_write(mss, 10, 2); /* int enable */
766 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
767 /* the following seem required on the CS4232 */
768 ad_unmute(mss);
769 return 0;
770 }
771
772
773 /*
774 * main irq handler for the CS423x. The OPTi931 code is
775 * a separate one.
776 * The correct way to operate for a device with multiple internal
777 * interrupt sources is to loop on the status register and ack
778 * interrupts until all interrupts are served and none are reported. At
779 * this point the IRQ line to the ISA IRQ controller should go low
780 * and be raised at the next interrupt.
781 *
782 * Since the ISA IRQ controller is sent EOI _before_ passing control
783 * to the isr, it might happen that we serve an interrupt early, in
784 * which case the status register at the next interrupt should just
785 * say that there are no more interrupts...
786 */
787
788 static void
mss_intr(void * arg)789 mss_intr(void *arg)
790 {
791 struct mss_info *mss = arg;
792 u_char c = 0, served = 0;
793 int i;
794
795 DEB(printf("mss_intr\n"));
796 mss_lock(mss);
797 ad_read(mss, 11); /* fake read of status bits */
798
799 /* loop until there are interrupts, but no more than 10 times. */
800 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
801 /* get exact reason for full-duplex boards */
802 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
803 c &= ~served;
804 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
805 served |= 0x10;
806 mss_unlock(mss);
807 chn_intr(mss->pch.channel);
808 mss_lock(mss);
809 }
810 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
811 served |= 0x20;
812 mss_unlock(mss);
813 chn_intr(mss->rch.channel);
814 mss_lock(mss);
815 }
816 /* now ack the interrupt */
817 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
818 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
819 }
820 if (i == 10) {
821 BVDDB(printf("mss_intr: irq, but not from mss\n"));
822 } else if (served == 0) {
823 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
824 /*
825 * this should not happen... I have no idea what to do now.
826 * maybe should do a sanity check and restart dmas ?
827 */
828 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
829 }
830 mss_unlock(mss);
831 }
832
833 /*
834 * AD_WAIT_INIT waits if we are initializing the board and
835 * we cannot modify its settings
836 */
837 static int
ad_wait_init(struct mss_info * mss,int x)838 ad_wait_init(struct mss_info *mss, int x)
839 {
840 int arg = x, n = 0; /* to shut up the compiler... */
841 for (; x > 0; x--)
842 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
843 else return n;
844 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
845 return n;
846 }
847
848 static int
ad_read(struct mss_info * mss,int reg)849 ad_read(struct mss_info *mss, int reg)
850 {
851 int x;
852
853 ad_wait_init(mss, 201000);
854 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
855 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
856 x = io_rd(mss, MSS_IDATA);
857 /* printf("ad_read %d, %x\n", reg, x); */
858 return x;
859 }
860
861 static void
ad_write(struct mss_info * mss,int reg,u_char data)862 ad_write(struct mss_info *mss, int reg, u_char data)
863 {
864 int x;
865
866 /* printf("ad_write %d, %x\n", reg, data); */
867 ad_wait_init(mss, 1002000);
868 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
869 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
870 io_wr(mss, MSS_IDATA, data);
871 }
872
873 static void
ad_write_cnt(struct mss_info * mss,int reg,u_short cnt)874 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
875 {
876 ad_write(mss, reg+1, cnt & 0xff);
877 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
878 }
879
880 static void
wait_for_calibration(struct mss_info * mss)881 wait_for_calibration(struct mss_info *mss)
882 {
883 int t;
884
885 /*
886 * Wait until the auto calibration process has finished.
887 *
888 * 1) Wait until the chip becomes ready (reads don't return 0x80).
889 * 2) Wait until the ACI bit of I11 gets on
890 * 3) Wait until the ACI bit of I11 gets off
891 */
892
893 t = ad_wait_init(mss, 1000000);
894 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
895
896 /*
897 * The calibration mode for chips that support it is set so that
898 * we never see ACI go on.
899 */
900 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
901 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
902 } else {
903 /*
904 * XXX This should only be enabled for cards that *really*
905 * need it. Are there any?
906 */
907 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
908 }
909 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
910 }
911
912 static void
ad_unmute(struct mss_info * mss)913 ad_unmute(struct mss_info *mss)
914 {
915 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
916 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
917 }
918
919 static void
ad_enter_MCE(struct mss_info * mss)920 ad_enter_MCE(struct mss_info *mss)
921 {
922 int prev;
923
924 mss->bd_flags |= BD_F_MCE_BIT;
925 ad_wait_init(mss, 203000);
926 prev = io_rd(mss, MSS_INDEX);
927 prev &= ~MSS_TRD;
928 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
929 }
930
931 static void
ad_leave_MCE(struct mss_info * mss)932 ad_leave_MCE(struct mss_info *mss)
933 {
934 u_char prev;
935
936 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
937 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
938 return;
939 }
940
941 ad_wait_init(mss, 1000000);
942
943 mss->bd_flags &= ~BD_F_MCE_BIT;
944
945 prev = io_rd(mss, MSS_INDEX);
946 prev &= ~MSS_TRD;
947 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
948 wait_for_calibration(mss);
949 }
950
951 static int
mss_speed(struct mss_chinfo * ch,int speed)952 mss_speed(struct mss_chinfo *ch, int speed)
953 {
954 struct mss_info *mss = ch->parent;
955 /*
956 * In the CS4231, the low 4 bits of I8 are used to hold the
957 * sample rate. Only a fixed number of values is allowed. This
958 * table lists them. The speed-setting routines scans the table
959 * looking for the closest match. This is the only supported method.
960 *
961 * In the CS4236, there is an alternate metod (which we do not
962 * support yet) which provides almost arbitrary frequency setting.
963 * In the AD1845, it looks like the sample rate can be
964 * almost arbitrary, and written directly to a register.
965 * In the OPTi931, there is a SB command which provides for
966 * almost arbitrary frequency setting.
967 *
968 */
969 ad_enter_MCE(mss);
970 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
971 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
972 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
973 /* XXX must also do something in I27 for the ad1845 */
974 } else {
975 int i, sel = 0; /* assume entry 0 does not contain -1 */
976 static int speeds[] =
977 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
978 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
979
980 for (i = 1; i < 16; i++)
981 if (speeds[i] > 0 &&
982 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
983 speed = speeds[sel];
984 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
985 ad_wait_init(mss, 10000);
986 }
987 ad_leave_MCE(mss);
988
989 return speed;
990 }
991
992 /*
993 * mss_format checks that the format is supported (or defaults to AFMT_U8)
994 * and returns the bit setting for the 1848 register corresponding to
995 * the desired format.
996 *
997 * fixed lr970724
998 */
999
1000 static int
mss_format(struct mss_chinfo * ch,u_int32_t format)1001 mss_format(struct mss_chinfo *ch, u_int32_t format)
1002 {
1003 struct mss_info *mss = ch->parent;
1004 int i, arg = AFMT_ENCODING(format);
1005
1006 /*
1007 * The data format uses 3 bits (just 2 on the 1848). For each
1008 * bit setting, the following array returns the corresponding format.
1009 * The code scans the array looking for a suitable format. In
1010 * case it is not found, default to AFMT_U8 (not such a good
1011 * choice, but let's do it for compatibility...).
1012 */
1013
1014 static int fmts[] =
1015 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1016 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1017
1018 ch->fmt = format;
1019 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1020 arg = i << 1;
1021 if (AFMT_CHANNEL(format) > 1) arg |= 1;
1022 arg <<= 4;
1023 ad_enter_MCE(mss);
1024 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1025 ad_wait_init(mss, 10000);
1026 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1027 ad_write(mss, 28, arg); /* capture mode */
1028 ad_wait_init(mss, 10000);
1029 }
1030 ad_leave_MCE(mss);
1031 return format;
1032 }
1033
1034 static int
mss_trigger(struct mss_chinfo * ch,int go)1035 mss_trigger(struct mss_chinfo *ch, int go)
1036 {
1037 struct mss_info *mss = ch->parent;
1038 u_char m;
1039 int retry, wr, cnt, ss;
1040
1041 ss = 1;
1042 ss <<= (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
1043 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1044
1045 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1046 m = ad_read(mss, 9);
1047 switch (go) {
1048 case PCMTRIG_START:
1049 cnt = (ch->blksz / ss) - 1;
1050
1051 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1052 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1053 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1054 break;
1055
1056 case PCMTRIG_STOP:
1057 case PCMTRIG_ABORT: /* XXX check this... */
1058 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1059 #if 0
1060 /*
1061 * try to disable DMA by clearing count registers. Not sure it
1062 * is needed, and it might cause false interrupts when the
1063 * DMA is re-enabled later.
1064 */
1065 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1066 #endif
1067 }
1068 /* on the OPTi931 the enable bit seems hard to set... */
1069 for (retry = 10; retry > 0; retry--) {
1070 ad_write(mss, 9, m);
1071 if (ad_read(mss, 9) == m) break;
1072 }
1073 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1074 m, ad_read(mss, 9)));
1075 return 0;
1076 }
1077
1078
1079 /*
1080 * the opti931 seems to miss interrupts when working in full
1081 * duplex, so we try some heuristics to catch them.
1082 */
1083 static void
opti931_intr(void * arg)1084 opti931_intr(void *arg)
1085 {
1086 struct mss_info *mss = (struct mss_info *)arg;
1087 u_char masked = 0, i11, mc11, c = 0;
1088 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1089 int loops = 10;
1090
1091 #if 0
1092 reason = io_rd(mss, MSS_STATUS);
1093 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1094 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1095 return;
1096 }
1097 #endif
1098 mss_lock(mss);
1099 i11 = ad_read(mss, 11); /* XXX what's for ? */
1100 again:
1101
1102 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1103 mc11 &= 0x0c;
1104 if (c & 0x10) {
1105 DEB(printf("Warning: CD interrupt\n");)
1106 mc11 |= 0x10;
1107 }
1108 if (c & 0x20) {
1109 DEB(printf("Warning: MPU interrupt\n");)
1110 mc11 |= 0x20;
1111 }
1112 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1113 mc11, masked));
1114 masked |= mc11;
1115 /*
1116 * the nice OPTi931 sets the IRQ line before setting the bits in
1117 * mc11. So, on some occasions I have to retry (max 10 times).
1118 */
1119 if (mc11 == 0) { /* perhaps can return ... */
1120 reason = io_rd(mss, MSS_STATUS);
1121 if (reason & 1) {
1122 DEB(printf("one more try...\n");)
1123 if (--loops) goto again;
1124 else BVDDB(printf("intr, but mc11 not set\n");)
1125 }
1126 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1127 mss_unlock(mss);
1128 return;
1129 }
1130
1131 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1132 mss_unlock(mss);
1133 chn_intr(mss->rch.channel);
1134 mss_lock(mss);
1135 }
1136 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1137 mss_unlock(mss);
1138 chn_intr(mss->pch.channel);
1139 mss_lock(mss);
1140 }
1141 opti_wr(mss, 11, ~mc11); /* ack */
1142 if (--loops) goto again;
1143 mss_unlock(mss);
1144 DEB(printf("xxx too many loops\n");)
1145 }
1146
1147 /* -------------------------------------------------------------------- */
1148 /* channel interface */
1149 static void *
msschan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)1150 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1151 {
1152 struct mss_info *mss = devinfo;
1153 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1154
1155 ch->parent = mss;
1156 ch->channel = c;
1157 ch->buffer = b;
1158 ch->dir = dir;
1159 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
1160 return NULL;
1161 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1162 return ch;
1163 }
1164
1165 static int
msschan_setformat(kobj_t obj,void * data,u_int32_t format)1166 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1167 {
1168 struct mss_chinfo *ch = data;
1169 struct mss_info *mss = ch->parent;
1170
1171 mss_lock(mss);
1172 mss_format(ch, format);
1173 mss_unlock(mss);
1174 return 0;
1175 }
1176
1177 static u_int32_t
msschan_setspeed(kobj_t obj,void * data,u_int32_t speed)1178 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1179 {
1180 struct mss_chinfo *ch = data;
1181 struct mss_info *mss = ch->parent;
1182 u_int32_t r;
1183
1184 mss_lock(mss);
1185 r = mss_speed(ch, speed);
1186 mss_unlock(mss);
1187
1188 return r;
1189 }
1190
1191 static u_int32_t
msschan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)1192 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1193 {
1194 struct mss_chinfo *ch = data;
1195
1196 ch->blksz = blocksize;
1197 sndbuf_resize(ch->buffer, 2, ch->blksz);
1198
1199 return ch->blksz;
1200 }
1201
1202 static int
msschan_trigger(kobj_t obj,void * data,int go)1203 msschan_trigger(kobj_t obj, void *data, int go)
1204 {
1205 struct mss_chinfo *ch = data;
1206 struct mss_info *mss = ch->parent;
1207
1208 if (!PCMTRIG_COMMON(go))
1209 return 0;
1210
1211 sndbuf_dma(ch->buffer, go);
1212 mss_lock(mss);
1213 mss_trigger(ch, go);
1214 mss_unlock(mss);
1215 return 0;
1216 }
1217
1218 static u_int32_t
msschan_getptr(kobj_t obj,void * data)1219 msschan_getptr(kobj_t obj, void *data)
1220 {
1221 struct mss_chinfo *ch = data;
1222 return sndbuf_dmaptr(ch->buffer);
1223 }
1224
1225 static struct pcmchan_caps *
msschan_getcaps(kobj_t obj,void * data)1226 msschan_getcaps(kobj_t obj, void *data)
1227 {
1228 struct mss_chinfo *ch = data;
1229
1230 switch(ch->parent->bd_id) {
1231 case MD_OPTI931:
1232 return &opti931_caps;
1233 break;
1234
1235 case MD_GUSPNP:
1236 case MD_GUSMAX:
1237 return &guspnp_caps;
1238 break;
1239
1240 default:
1241 return &mss_caps;
1242 break;
1243 }
1244 }
1245
1246 static kobj_method_t msschan_methods[] = {
1247 KOBJMETHOD(channel_init, msschan_init),
1248 KOBJMETHOD(channel_setformat, msschan_setformat),
1249 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1250 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1251 KOBJMETHOD(channel_trigger, msschan_trigger),
1252 KOBJMETHOD(channel_getptr, msschan_getptr),
1253 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1254 KOBJMETHOD_END
1255 };
1256 CHANNEL_DECLARE(msschan);
1257
1258 /* -------------------------------------------------------------------- */
1259
1260 /*
1261 * mss_probe() is the probe routine. Note, it is not necessary to
1262 * go through this for PnP devices, since they are already
1263 * indentified precisely using their PnP id.
1264 *
1265 * The base address supplied in the device refers to the old MSS
1266 * specs where the four 4 registers in io space contain configuration
1267 * information. Some boards (as an example, early MSS boards)
1268 * has such a block of registers, whereas others (generally CS42xx)
1269 * do not. In order to distinguish between the two and do not have
1270 * to supply two separate probe routines, the flags entry in isa_device
1271 * has a bit to mark this.
1272 *
1273 */
1274
1275 static int
mss_probe(device_t dev)1276 mss_probe(device_t dev)
1277 {
1278 u_char tmp, tmpx;
1279 int flags, irq, drq, result = ENXIO, setres = 0;
1280 struct mss_info *mss;
1281
1282 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1283
1284 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1285 if (!mss) return ENXIO;
1286
1287 mss->io_rid = 0;
1288 mss->conf_rid = -1;
1289 mss->irq_rid = 0;
1290 mss->drq1_rid = 0;
1291 mss->drq2_rid = -1;
1292 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1293 0, ~0, 8, RF_ACTIVE);
1294 if (!mss->io_base) {
1295 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1296 mss->io_rid = 0;
1297 /* XXX verify this */
1298 setres = 1;
1299 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1300 0x530, 8);
1301 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1302 0, ~0, 8, RF_ACTIVE);
1303 }
1304 if (!mss->io_base) goto no;
1305
1306 /* got irq/dma regs? */
1307 flags = device_get_flags(dev);
1308 irq = isa_get_irq(dev);
1309 drq = isa_get_drq(dev);
1310
1311 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1312
1313 /*
1314 * Check if the IO port returns valid signature. The original MS
1315 * Sound system returns 0x04 while some cards
1316 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1317 */
1318
1319 device_set_desc(dev, "MSS");
1320 tmpx = tmp = io_rd(mss, 3);
1321 if (tmp == 0xff) { /* Bus float */
1322 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1323 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1324 goto mss_probe_end;
1325 }
1326 tmp &= 0x3f;
1327 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00 || tmp == 0x05)) {
1328 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
1329 rman_get_start(mss->io_base), tmpx));
1330 goto no;
1331 }
1332 #ifdef PC98
1333 if (irq > 12) {
1334 #else
1335 if (irq > 11) {
1336 #endif
1337 printf("MSS: Bad IRQ %d\n", irq);
1338 goto no;
1339 }
1340 if (!(drq == 0 || drq == 1 || drq == 3)) {
1341 printf("MSS: Bad DMA %d\n", drq);
1342 goto no;
1343 }
1344 if (tmpx & 0x80) {
1345 /* 8-bit board: only drq1/3 and irq7/9 */
1346 if (drq == 0) {
1347 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1348 goto no;
1349 }
1350 if (!(irq == 7 || irq == 9)) {
1351 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1352 irq);
1353 goto no;
1354 }
1355 }
1356 mss_probe_end:
1357 result = mss_detect(dev, mss);
1358 no:
1359 mss_release_resources(mss, dev);
1360 #if 0
1361 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1362 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1363 #endif
1364 return result;
1365 }
1366
1367 static int
1368 mss_detect(device_t dev, struct mss_info *mss)
1369 {
1370 int i;
1371 u_char tmp = 0, tmp1, tmp2;
1372 char *name, *yamaha;
1373
1374 if (mss->bd_id != 0) {
1375 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1376 device_get_desc(dev));
1377 return 0;
1378 }
1379
1380 name = "AD1848";
1381 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1382
1383 #ifndef PC98
1384 if (opti_detect(dev, mss)) {
1385 switch (mss->bd_id) {
1386 case MD_OPTI924:
1387 name = "OPTi924";
1388 break;
1389 case MD_OPTI930:
1390 name = "OPTi930";
1391 break;
1392 }
1393 printf("Found OPTi device %s\n", name);
1394 if (opti_init(dev, mss) == 0) goto gotit;
1395 }
1396 #endif
1397
1398 /*
1399 * Check that the I/O address is in use.
1400 *
1401 * bit 7 of the base I/O port is known to be 0 after the chip has
1402 * performed its power on initialization. Just assume this has
1403 * happened before the OS is starting.
1404 *
1405 * If the I/O address is unused, it typically returns 0xff.
1406 */
1407
1408 for (i = 0; i < 10; i++)
1409 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1410 else break;
1411
1412 if (i >= 10) { /* Not an AD1848 */
1413 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1414 goto no;
1415 }
1416 /*
1417 * Test if it's possible to change contents of the indirect
1418 * registers. Registers 0 and 1 are ADC volume registers. The bit
1419 * 0x10 is read only so try to avoid using it.
1420 */
1421
1422 ad_write(mss, 0, 0xaa);
1423 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1424 tmp1 = ad_read(mss, 0);
1425 tmp2 = ad_read(mss, 1);
1426 if (tmp1 != 0xaa || tmp2 != 0x45) {
1427 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1428 goto no;
1429 }
1430
1431 ad_write(mss, 0, 0x45);
1432 ad_write(mss, 1, 0xaa);
1433 tmp1 = ad_read(mss, 0);
1434 tmp2 = ad_read(mss, 1);
1435 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1436 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1437 goto no;
1438 }
1439
1440 /*
1441 * The indirect register I12 has some read only bits. Lets try to
1442 * change them.
1443 */
1444
1445 tmp = ad_read(mss, 12);
1446 ad_write(mss, 12, (~tmp) & 0x0f);
1447 tmp1 = ad_read(mss, 12);
1448
1449 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1450 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1451 goto no;
1452 }
1453
1454 /*
1455 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1456 * 0x01=RevB
1457 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1458 */
1459
1460 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1461
1462 /*
1463 * The original AD1848/CS4248 has just 16 indirect registers. This
1464 * means that I0 and I16 should return the same value (etc.). Ensure
1465 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1466 * with new parts.
1467 */
1468
1469 ad_write(mss, 12, 0); /* Mode2=disabled */
1470 #if 0
1471 for (i = 0; i < 16; i++) {
1472 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1473 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1474 i, tmp1, tmp2));
1475 /*
1476 * note - this seems to fail on the 4232 on I11. So we just break
1477 * rather than fail. (which makes this test pointless - cg)
1478 */
1479 break; /* return 0; */
1480 }
1481 }
1482 #endif
1483 /*
1484 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1485 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1486 *
1487 * On the OPTi931, however, I12 is readonly and only contains the
1488 * chip revision ID (as in the CS4231A). The upper bits return 0.
1489 */
1490
1491 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1492
1493 tmp1 = ad_read(mss, 12);
1494 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1495 if ((tmp1 & 0xf0) == 0x00) {
1496 BVDDB(printf("this should be an OPTi931\n");)
1497 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1498 /*
1499 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1500 * We want to check that this is really a CS4231
1501 * Verify that setting I0 doesn't change I16.
1502 */
1503 ad_write(mss, 16, 0); /* Set I16 to known value */
1504 ad_write(mss, 0, 0x45);
1505 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1506
1507 ad_write(mss, 0, 0xaa);
1508 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1509 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1510 goto no;
1511 }
1512 /* Verify that some bits of I25 are read only. */
1513 tmp1 = ad_read(mss, 25); /* Original bits */
1514 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1515 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1516 int id;
1517
1518 /* It's at least CS4231 */
1519 name = "CS4231";
1520 mss->bd_id = MD_CS42XX;
1521
1522 /*
1523 * It could be an AD1845 or CS4231A as well.
1524 * CS4231 and AD1845 report the same revision info in I25
1525 * while the CS4231A reports different.
1526 */
1527
1528 id = ad_read(mss, 25) & 0xe7;
1529 /*
1530 * b7-b5 = version number;
1531 * 100 : all CS4231
1532 * 101 : CS4231A
1533 *
1534 * b2-b0 = chip id;
1535 */
1536 switch (id) {
1537
1538 case 0xa0:
1539 name = "CS4231A";
1540 mss->bd_id = MD_CS42XX;
1541 break;
1542
1543 case 0xa2:
1544 name = "CS4232";
1545 mss->bd_id = MD_CS42XX;
1546 break;
1547
1548 case 0xb2:
1549 /* strange: the 4231 data sheet says b4-b3 are XX
1550 * so this should be the same as 0xa2
1551 */
1552 name = "CS4232A";
1553 mss->bd_id = MD_CS42XX;
1554 break;
1555
1556 case 0x80:
1557 /*
1558 * It must be a CS4231 or AD1845. The register I23
1559 * of CS4231 is undefined and it appears to be read
1560 * only. AD1845 uses I23 for setting sample rate.
1561 * Assume the chip is AD1845 if I23 is changeable.
1562 */
1563
1564 tmp = ad_read(mss, 23);
1565
1566 ad_write(mss, 23, ~tmp);
1567 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1568 name = "AD1845";
1569 mss->bd_id = MD_AD1845;
1570 }
1571 ad_write(mss, 23, tmp); /* Restore */
1572
1573 yamaha = ymf_test(dev, mss);
1574 if (yamaha) {
1575 mss->bd_id = MD_YM0020;
1576 name = yamaha;
1577 }
1578 break;
1579
1580 case 0x83: /* CS4236 */
1581 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1582 name = "CS4236";
1583 mss->bd_id = MD_CS42XX;
1584 break;
1585
1586 default: /* Assume CS4231 */
1587 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1588 mss->bd_id = MD_CS42XX;
1589 }
1590 }
1591 ad_write(mss, 25, tmp1); /* Restore bits */
1592 gotit:
1593 BVDDB(printf("mss_detect() - Detected %s\n", name));
1594 device_set_desc(dev, name);
1595 device_set_flags(dev,
1596 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1597 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1598 return 0;
1599 no:
1600 return ENXIO;
1601 }
1602
1603 #ifndef PC98
1604 static int
1605 opti_detect(device_t dev, struct mss_info *mss)
1606 {
1607 int c;
1608 static const struct opticard {
1609 int boardid;
1610 int passwdreg;
1611 int password;
1612 int base;
1613 int indir_reg;
1614 } cards[] = {
1615 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1616 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1617 { 0 },
1618 };
1619 mss->conf_rid = 3;
1620 mss->indir_rid = 4;
1621 for (c = 0; cards[c].base; c++) {
1622 mss->optibase = cards[c].base;
1623 mss->password = cards[c].password;
1624 mss->passwdreg = cards[c].passwdreg;
1625 mss->bd_id = cards[c].boardid;
1626
1627 if (cards[c].indir_reg)
1628 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1629 &mss->indir_rid, cards[c].indir_reg,
1630 cards[c].indir_reg+1, 1, RF_ACTIVE);
1631
1632 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1633 &mss->conf_rid, mss->optibase, mss->optibase+9,
1634 9, RF_ACTIVE);
1635
1636 if (opti_read(mss, 1) != 0xff) {
1637 return 1;
1638 } else {
1639 if (mss->indir)
1640 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1641 mss->indir = NULL;
1642 if (mss->conf_base)
1643 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1644 mss->conf_base = NULL;
1645 }
1646 }
1647 return 0;
1648 }
1649 #endif
1650
1651 static char *
1652 ymf_test(device_t dev, struct mss_info *mss)
1653 {
1654 static int ports[] = {0x370, 0x310, 0x538};
1655 int p, i, j, version;
1656 static char *chipset[] = {
1657 NULL, /* 0 */
1658 "OPL3-SA2 (YMF711)", /* 1 */
1659 "OPL3-SA3 (YMF715)", /* 2 */
1660 "OPL3-SA3 (YMF715)", /* 3 */
1661 "OPL3-SAx (YMF719)", /* 4 */
1662 "OPL3-SAx (YMF719)", /* 5 */
1663 "OPL3-SAx (YMF719)", /* 6 */
1664 "OPL3-SAx (YMF719)", /* 7 */
1665 };
1666
1667 for (p = 0; p < 3; p++) {
1668 mss->conf_rid = 1;
1669 mss->conf_base = bus_alloc_resource(dev,
1670 SYS_RES_IOPORT,
1671 &mss->conf_rid,
1672 ports[p], ports[p] + 1, 2,
1673 RF_ACTIVE);
1674 if (!mss->conf_base) return 0;
1675
1676 /* Test the index port of the config registers */
1677 i = port_rd(mss->conf_base, 0);
1678 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1679 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1680 port_wr(mss->conf_base, 0, i);
1681 if (!j) {
1682 bus_release_resource(dev, SYS_RES_IOPORT,
1683 mss->conf_rid, mss->conf_base);
1684 #ifdef PC98
1685 /* PC98 need this. I don't know reason why. */
1686 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1687 #endif
1688 mss->conf_base = 0;
1689 continue;
1690 }
1691 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1692 return chipset[version];
1693 }
1694 return NULL;
1695 }
1696
1697 static int
1698 mss_doattach(device_t dev, struct mss_info *mss)
1699 {
1700 int pdma, rdma, flags = device_get_flags(dev);
1701 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1702
1703 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
1704 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1705 if (!mss_alloc_resources(mss, dev)) goto no;
1706 mss_init(mss, dev);
1707 pdma = rman_get_start(mss->drq1);
1708 rdma = rman_get_start(mss->drq2);
1709 if (flags & DV_F_TRUE_MSS) {
1710 /* has IRQ/DMA registers, set IRQ and DMA addr */
1711 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
1712 static char interrupt_bits[13] =
1713 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
1714 #else
1715 static char interrupt_bits[12] =
1716 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
1717 #endif
1718 static char pdma_bits[4] = {1, 2, -1, 3};
1719 static char valid_rdma[4] = {1, 0, -1, 0};
1720 char bits;
1721
1722 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1723 goto no;
1724 #ifndef PC98 /* CS423[12] in PC98 don't support this. */
1725 io_wr(mss, 0, bits | 0x40); /* config port */
1726 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1727 #endif
1728 /* Write IRQ+DMA setup */
1729 if (pdma_bits[pdma] == -1) goto no;
1730 bits |= pdma_bits[pdma];
1731 if (pdma != rdma) {
1732 if (rdma == valid_rdma[pdma]) bits |= 4;
1733 else {
1734 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1735 goto no;
1736 }
1737 }
1738 io_wr(mss, 0, bits);
1739 printf("drq/irq conf %x\n", io_rd(mss, 0));
1740 }
1741 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1742 switch (mss->bd_id) {
1743 case MD_OPTI931:
1744 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
1745 break;
1746 default:
1747 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
1748 }
1749 if (pdma == rdma)
1750 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1751 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
1752 /*boundary*/0,
1753 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1754 /*highaddr*/BUS_SPACE_MAXADDR,
1755 /*filter*/NULL, /*filterarg*/NULL,
1756 /*maxsize*/mss->bufsize, /*nsegments*/1,
1757 /*maxsegz*/0x3ffff, /*flags*/0,
1758 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
1759 &mss->parent_dmat) != 0) {
1760 device_printf(dev, "unable to create dma tag\n");
1761 goto no;
1762 }
1763
1764 if (pdma != rdma)
1765 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
1766 else
1767 status2[0] = '\0';
1768
1769 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
1770 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1771
1772 if (pcm_register(dev, mss, 1, 1)) goto no;
1773 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1774 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1775 pcm_setstatus(dev, status);
1776
1777 return 0;
1778 no:
1779 mss_release_resources(mss, dev);
1780 return ENXIO;
1781 }
1782
1783 static int
1784 mss_detach(device_t dev)
1785 {
1786 int r;
1787 struct mss_info *mss;
1788
1789 r = pcm_unregister(dev);
1790 if (r)
1791 return r;
1792
1793 mss = pcm_getdevinfo(dev);
1794 mss_release_resources(mss, dev);
1795
1796 return 0;
1797 }
1798
1799 static int
1800 mss_attach(device_t dev)
1801 {
1802 struct mss_info *mss;
1803 int flags = device_get_flags(dev);
1804
1805 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1806 if (!mss) return ENXIO;
1807
1808 mss->io_rid = 0;
1809 mss->conf_rid = -1;
1810 mss->irq_rid = 0;
1811 mss->drq1_rid = 0;
1812 mss->drq2_rid = -1;
1813 if (flags & DV_F_DUAL_DMA) {
1814 bus_set_resource(dev, SYS_RES_DRQ, 1,
1815 flags & DV_F_DRQ_MASK, 1);
1816 mss->drq2_rid = 1;
1817 }
1818 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1819 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1820 return mss_doattach(dev, mss);
1821 }
1822
1823 /*
1824 * mss_resume() is the code to allow a laptop to resume using the sound
1825 * card.
1826 *
1827 * This routine re-sets the state of the board to the state before going
1828 * to sleep. According to the yamaha docs this is the right thing to do,
1829 * but getting DMA restarted appears to be a bit of a trick, so the device
1830 * has to be closed and re-opened to be re-used, but there is no skipping
1831 * problem, and volume, bass/treble and most other things are restored
1832 * properly.
1833 *
1834 */
1835
1836 static int
1837 mss_resume(device_t dev)
1838 {
1839 /*
1840 * Restore the state taken below.
1841 */
1842 struct mss_info *mss;
1843 int i;
1844
1845 mss = pcm_getdevinfo(dev);
1846
1847 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
1848 /* This works on a Toshiba Libretto 100CT. */
1849 for (i = 0; i < MSS_INDEXED_REGS; i++)
1850 ad_write(mss, i, mss->mss_indexed_regs[i]);
1851 for (i = 0; i < OPL_INDEXED_REGS; i++)
1852 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1853 mss_intr(mss);
1854 }
1855
1856 if (mss->bd_id == MD_CS423X) {
1857 /* Needed on IBM Thinkpad 600E */
1858 mss_lock(mss);
1859 mss_format(&mss->pch, mss->pch.channel->format);
1860 mss_speed(&mss->pch, mss->pch.channel->speed);
1861 mss_unlock(mss);
1862 }
1863
1864 return 0;
1865
1866 }
1867
1868 /*
1869 * mss_suspend() is the code that gets called right before a laptop
1870 * suspends.
1871 *
1872 * This code saves the state of the sound card right before shutdown
1873 * so it can be restored above.
1874 *
1875 */
1876
1877 static int
1878 mss_suspend(device_t dev)
1879 {
1880 int i;
1881 struct mss_info *mss;
1882
1883 mss = pcm_getdevinfo(dev);
1884
1885 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
1886 {
1887 /* this stops playback. */
1888 conf_wr(mss, 0x12, 0x0c);
1889 for(i = 0; i < MSS_INDEXED_REGS; i++)
1890 mss->mss_indexed_regs[i] = ad_read(mss, i);
1891 for(i = 0; i < OPL_INDEXED_REGS; i++)
1892 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1893 mss->opl_indexed_regs[0x12] = 0x0;
1894 }
1895 return 0;
1896 }
1897
1898 static device_method_t mss_methods[] = {
1899 /* Device interface */
1900 DEVMETHOD(device_probe, mss_probe),
1901 DEVMETHOD(device_attach, mss_attach),
1902 DEVMETHOD(device_detach, mss_detach),
1903 DEVMETHOD(device_suspend, mss_suspend),
1904 DEVMETHOD(device_resume, mss_resume),
1905
1906 { 0, 0 }
1907 };
1908
1909 static driver_t mss_driver = {
1910 "pcm",
1911 mss_methods,
1912 PCM_SOFTC_SIZE,
1913 };
1914
1915 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1916 MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1917 MODULE_VERSION(snd_mss, 1);
1918
1919 static int
1920 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1921 {
1922 struct resource *sbport;
1923 int i, ret, rid;
1924
1925 rid = 0;
1926 ret = -1;
1927 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1928 if (sbport) {
1929 for (i = 0; i < 1000; i++) {
1930 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1931 DELAY((i > 100) ? 1000 : 10);
1932 else {
1933 port_wr(sbport, SBDSP_CMD, 0x09);
1934 break;
1935 }
1936 }
1937 for (i = 0; i < 1000; i++) {
1938 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1939 DELAY((i > 100) ? 1000 : 10);
1940 else {
1941 port_wr(sbport, SBDSP_CMD, 0x00);
1942 ret = 0;
1943 break;
1944 }
1945 }
1946 DELAY(1000);
1947 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1948 }
1949 return ret;
1950 }
1951
1952 static struct isa_pnp_id pnpmss_ids[] = {
1953 {0x0000630e, "CS423x"}, /* CSC0000 */
1954 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1955 {0x01000000, "CMI8330"}, /* @@@0001 */
1956 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1957 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1958 {0x1093143e, "OPTi931"}, /* OPT9310 */
1959 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1960 {0x0000143e, "OPTi924"}, /* OPT0924 */
1961 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1962 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1963 #if 0
1964 {0x0000561e, "GusPnP"}, /* GRV0000 */
1965 #endif
1966 {0},
1967 };
1968
1969 static int
1970 pnpmss_probe(device_t dev)
1971 {
1972 u_int32_t lid, vid;
1973
1974 lid = isa_get_logicalid(dev);
1975 vid = isa_get_vendorid(dev);
1976 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1977 return ENXIO;
1978 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1979 }
1980
1981 static int
1982 pnpmss_attach(device_t dev)
1983 {
1984 struct mss_info *mss;
1985
1986 mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
1987 mss->io_rid = 0;
1988 mss->conf_rid = -1;
1989 mss->irq_rid = 0;
1990 mss->drq1_rid = 0;
1991 mss->drq2_rid = 1;
1992 mss->bd_id = MD_CS42XX;
1993
1994 switch (isa_get_logicalid(dev)) {
1995 case 0x0000630e: /* CSC0000 */
1996 case 0x0001630e: /* CSC0100 */
1997 mss->bd_flags |= BD_F_MSS_OFFSET;
1998 mss->bd_id = MD_CS423X;
1999 break;
2000
2001 case 0x2100a865: /* YHM0021 */
2002 mss->io_rid = 1;
2003 mss->conf_rid = 4;
2004 mss->bd_id = MD_YM0020;
2005 break;
2006
2007 case 0x1110d315: /* ENS1011 */
2008 mss->io_rid = 1;
2009 mss->bd_id = MD_VIVO;
2010 break;
2011
2012 case 0x1093143e: /* OPT9310 */
2013 mss->bd_flags |= BD_F_MSS_OFFSET;
2014 mss->conf_rid = 3;
2015 mss->bd_id = MD_OPTI931;
2016 break;
2017
2018 case 0x5092143e: /* OPT9250 XXX guess */
2019 mss->io_rid = 1;
2020 mss->conf_rid = 3;
2021 mss->bd_id = MD_OPTI925;
2022 break;
2023
2024 case 0x0000143e: /* OPT0924 */
2025 mss->password = 0xe5;
2026 mss->passwdreg = 3;
2027 mss->optibase = 0xf0c;
2028 mss->io_rid = 2;
2029 mss->conf_rid = 3;
2030 mss->bd_id = MD_OPTI924;
2031 mss->bd_flags |= BD_F_924PNP;
2032 if(opti_init(dev, mss) != 0) {
2033 free(mss, M_DEVBUF);
2034 return ENXIO;
2035 }
2036 break;
2037
2038 case 0x1022b839: /* NMX2210 */
2039 mss->io_rid = 1;
2040 break;
2041
2042 case 0x01005407: /* AZT0001 */
2043 /* put into MSS mode first (snatched from NetBSD) */
2044 if (azt2320_mss_mode(mss, dev) == -1) {
2045 free(mss, M_DEVBUF);
2046 return ENXIO;
2047 }
2048
2049 mss->bd_flags |= BD_F_MSS_OFFSET;
2050 mss->io_rid = 2;
2051 break;
2052
2053 #if 0
2054 case 0x0000561e: /* GRV0000 */
2055 mss->bd_flags |= BD_F_MSS_OFFSET;
2056 mss->io_rid = 2;
2057 mss->conf_rid = 1;
2058 mss->drq1_rid = 1;
2059 mss->drq2_rid = 0;
2060 mss->bd_id = MD_GUSPNP;
2061 break;
2062 #endif
2063 case 0x01000000: /* @@@0001 */
2064 mss->drq2_rid = -1;
2065 break;
2066
2067 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2068 default:
2069 mss->bd_flags |= BD_F_MSS_OFFSET;
2070 break;
2071 }
2072 return mss_doattach(dev, mss);
2073 }
2074
2075 static int
2076 opti_init(device_t dev, struct mss_info *mss)
2077 {
2078 int flags = device_get_flags(dev);
2079 int basebits = 0;
2080
2081 if (!mss->conf_base) {
2082 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2083 mss->optibase, 0x9);
2084
2085 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2086 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2087 0x9, RF_ACTIVE);
2088 }
2089
2090 if (!mss->conf_base)
2091 return ENXIO;
2092
2093 if (!mss->io_base)
2094 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2095 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2096
2097 if (!mss->io_base) /* No hint specified, use 0x530 */
2098 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2099 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2100
2101 if (!mss->io_base)
2102 return ENXIO;
2103
2104 switch (rman_get_start(mss->io_base)) {
2105 case 0x530:
2106 basebits = 0x0;
2107 break;
2108 case 0xe80:
2109 basebits = 0x10;
2110 break;
2111 case 0xf40:
2112 basebits = 0x20;
2113 break;
2114 case 0x604:
2115 basebits = 0x30;
2116 break;
2117 default:
2118 printf("opti_init: invalid MSS base address!\n");
2119 return ENXIO;
2120 }
2121
2122
2123 switch (mss->bd_id) {
2124 case MD_OPTI924:
2125 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2126 opti_write(mss, 2, 0x00); /* Disable CD */
2127 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2128 opti_write(mss, 4, 0xf0);
2129 opti_write(mss, 5, 0x00);
2130 opti_write(mss, 6, 0x02); /* MPU stuff */
2131 break;
2132
2133 case MD_OPTI930:
2134 opti_write(mss, 1, 0x00 | basebits);
2135 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2136 opti_write(mss, 4, 0x52); /* Empty FIFO */
2137 opti_write(mss, 5, 0x3c); /* Mode 2 */
2138 opti_write(mss, 6, 0x02); /* Enable MSS */
2139 break;
2140 }
2141
2142 if (mss->bd_flags & BD_F_924PNP) {
2143 u_int32_t irq = isa_get_irq(dev);
2144 u_int32_t drq = isa_get_drq(dev);
2145 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2146 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2147 if (flags & DV_F_DUAL_DMA) {
2148 bus_set_resource(dev, SYS_RES_DRQ, 1,
2149 flags & DV_F_DRQ_MASK, 1);
2150 mss->drq2_rid = 1;
2151 }
2152 }
2153
2154 /* OPTixxx has I/DRQ registers */
2155
2156 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2157
2158 return 0;
2159 }
2160
2161 static void
2162 opti_write(struct mss_info *mss, u_char reg, u_char val)
2163 {
2164 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2165
2166 switch(mss->bd_id) {
2167 case MD_OPTI924:
2168 if (reg > 7) { /* Indirect register */
2169 port_wr(mss->conf_base, mss->passwdreg, reg);
2170 port_wr(mss->conf_base, mss->passwdreg,
2171 mss->password);
2172 port_wr(mss->conf_base, 9, val);
2173 return;
2174 }
2175 port_wr(mss->conf_base, reg, val);
2176 break;
2177
2178 case MD_OPTI930:
2179 port_wr(mss->indir, 0, reg);
2180 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2181 port_wr(mss->indir, 1, val);
2182 break;
2183 }
2184 }
2185
2186 #ifndef PC98
2187 u_char
2188 opti_read(struct mss_info *mss, u_char reg)
2189 {
2190 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2191
2192 switch(mss->bd_id) {
2193 case MD_OPTI924:
2194 if (reg > 7) { /* Indirect register */
2195 port_wr(mss->conf_base, mss->passwdreg, reg);
2196 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2197 return(port_rd(mss->conf_base, 9));
2198 }
2199 return(port_rd(mss->conf_base, reg));
2200 break;
2201
2202 case MD_OPTI930:
2203 port_wr(mss->indir, 0, reg);
2204 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2205 return port_rd(mss->indir, 1);
2206 break;
2207 }
2208 return -1;
2209 }
2210 #endif
2211
2212 static device_method_t pnpmss_methods[] = {
2213 /* Device interface */
2214 DEVMETHOD(device_probe, pnpmss_probe),
2215 DEVMETHOD(device_attach, pnpmss_attach),
2216 DEVMETHOD(device_detach, mss_detach),
2217 DEVMETHOD(device_suspend, mss_suspend),
2218 DEVMETHOD(device_resume, mss_resume),
2219
2220 { 0, 0 }
2221 };
2222
2223 static driver_t pnpmss_driver = {
2224 "pcm",
2225 pnpmss_methods,
2226 PCM_SOFTC_SIZE,
2227 };
2228
2229 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2230 DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
2231 MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2232 MODULE_VERSION(snd_pnpmss, 1);
2233
2234 static int
2235 guspcm_probe(device_t dev)
2236 {
2237 struct sndcard_func *func;
2238
2239 func = device_get_ivars(dev);
2240 if (func == NULL || func->func != SCF_PCM)
2241 return ENXIO;
2242
2243 device_set_desc(dev, "GUS CS4231");
2244 return 0;
2245 }
2246
2247 static int
2248 guspcm_attach(device_t dev)
2249 {
2250 device_t parent = device_get_parent(dev);
2251 struct mss_info *mss;
2252 int base, flags;
2253 unsigned char ctl;
2254
2255 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2256 if (mss == NULL)
2257 return ENOMEM;
2258
2259 mss->bd_flags = BD_F_MSS_OFFSET;
2260 mss->io_rid = 2;
2261 mss->conf_rid = 1;
2262 mss->irq_rid = 0;
2263 mss->drq1_rid = 1;
2264 mss->drq2_rid = -1;
2265
2266 if (isa_get_logicalid(parent) == 0)
2267 mss->bd_id = MD_GUSMAX;
2268 else {
2269 mss->bd_id = MD_GUSPNP;
2270 mss->drq2_rid = 0;
2271 goto skip_setup;
2272 }
2273
2274 flags = device_get_flags(parent);
2275 if (flags & DV_F_DUAL_DMA)
2276 mss->drq2_rid = 0;
2277
2278 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2279 0, ~0, 8, RF_ACTIVE);
2280
2281 if (mss->conf_base == NULL) {
2282 mss_release_resources(mss, dev);
2283 return ENXIO;
2284 }
2285
2286 base = isa_get_port(parent);
2287
2288 ctl = 0x40; /* CS4231 enable */
2289 if (isa_get_drq(dev) > 3)
2290 ctl |= 0x10; /* 16-bit dma channel 1 */
2291 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2292 ctl |= 0x20; /* 16-bit dma channel 2 */
2293 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2294 port_wr(mss->conf_base, 6, ctl);
2295
2296 skip_setup:
2297 return mss_doattach(dev, mss);
2298 }
2299
2300 static device_method_t guspcm_methods[] = {
2301 DEVMETHOD(device_probe, guspcm_probe),
2302 DEVMETHOD(device_attach, guspcm_attach),
2303 DEVMETHOD(device_detach, mss_detach),
2304
2305 { 0, 0 }
2306 };
2307
2308 static driver_t guspcm_driver = {
2309 "pcm",
2310 guspcm_methods,
2311 PCM_SOFTC_SIZE,
2312 };
2313
2314 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2315 MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2316 MODULE_VERSION(snd_guspcm, 1);
2317
2318
2319