1 /* $NetBSD: bereg.h,v 1.10 2021/12/12 13:05:14 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * BE Global registers 61 */ 62 #if 0 63 struct be_bregs { 64 uint32_t xif_cfg; /* XIF config */ 65 uint32_t _unused[63]; /* reserved */ 66 uint32_t stat; /* status, clear on read */ 67 uint32_t imask; /* interrupt mask */ 68 uint32_t _unused2[64]; /* reserved */ 69 uint32_t tx_swreset; /* tx software reset */ 70 uint32_t tx_cfg; /* tx config */ 71 uint32_t ipkt_gap1; /* inter-packet gap 1 */ 72 uint32_t ipkt_gap2; /* inter-packet gap 2 */ 73 uint32_t attempt_limit; /* tx attempt limit */ 74 uint32_t stime; /* tx slot time */ 75 uint32_t preamble_len; /* size of tx preamble */ 76 uint32_t preamble_pattern; /* pattern for tx preamble */ 77 uint32_t tx_sframe_delim; /* tx delimiter */ 78 uint32_t jsize; /* jam length */ 79 uint32_t tx_pkt_max; /* tx max pkt size */ 80 uint32_t tx_pkt_min; /* tx min pkt size */ 81 uint32_t peak_attempt; /* count of tx peak attempts */ 82 uint32_t dt_ctr; /* tx defer timer */ 83 uint32_t nc_ctr; /* tx normal collision cntr */ 84 uint32_t fc_ctr; /* tx first-collision cntr */ 85 uint32_t ex_ctr; /* tx excess-collision cntr */ 86 uint32_t lt_ctr; /* tx late-collision cntr */ 87 uint32_t rand_seed; /* tx random number seed */ 88 uint32_t tx_smachine; /* tx state machine */ 89 uint32_t _unused3[44]; /* reserved */ 90 uint32_t rx_swreset; /* rx software reset */ 91 uint32_t rx_cfg; /* rx config register */ 92 uint32_t rx_pkt_max; /* rx max pkt size */ 93 uint32_t rx_pkt_min; /* rx min pkt size */ 94 uint32_t mac_addr2; /* ethernet address 2 (MSB) */ 95 uint32_t mac_addr1; /* ethernet address 1 */ 96 uint32_t mac_addr0; /* ethernet address 0 (LSB) */ 97 uint32_t fr_ctr; /* rx frame receive cntr */ 98 uint32_t gle_ctr; /* rx giant-len error cntr */ 99 uint32_t unale_ctr; /* rx unaligned error cntr */ 100 uint32_t rcrce_ctr; /* rx CRC error cntr */ 101 uint32_t rx_smachine; /* rx state machine */ 102 uint32_t rx_cvalid; /* rx code violation */ 103 uint32_t _unused4; /* reserved */ 104 uint32_t htable3; /* hash table 3 */ 105 uint32_t htable2; /* hash table 2 */ 106 uint32_t htable1; /* hash table 1 */ 107 uint32_t htable0; /* hash table 0 */ 108 uint32_t afilter2; /* address filter 2 */ 109 uint32_t afilter1; /* address filter 1 */ 110 uint32_t afilter0; /* address filter 0 */ 111 uint32_t afilter_mask; /* address filter mask */ 112 }; 113 #endif 114 /* register indices: */ 115 #define BE_BRI_XIFCFG (0*4) 116 #define BE_BRI_STAT (64*4) 117 #define BE_BRI_IMASK (65*4) 118 #define BE_BRI_TXCFG (131*4) 119 #define BE_BRI_JSIZE (139*4) 120 #define BE_BRI_TXMAX (140*4) 121 #define BE_BRI_TXMIN (141*4) 122 #define BE_BRI_NCCNT (144*4) 123 #define BE_BRI_FCCNT (145*4) 124 #define BE_BRI_EXCNT (146*4) 125 #define BE_BRI_LTCNT (147*4) 126 #define BE_BRI_RANDSEED (148*4) 127 #define BE_BRI_RXCFG (195*4) 128 #define BE_BRI_RXMAX (196*4) 129 #define BE_BRI_RXMIN (197*4) 130 #define BE_BRI_MACADDR2 (198*4) 131 #define BE_BRI_MACADDR1 (199*4) 132 #define BE_BRI_MACADDR0 (200*4) 133 #define BE_BRI_HASHTAB3 (208*4) 134 #define BE_BRI_HASHTAB2 (209*4) 135 #define BE_BRI_HASHTAB1 (210*4) 136 #define BE_BRI_HASHTAB0 (211*4) 137 138 /* be_bregs.xif_cfg: XIF config. */ 139 #define BE_BR_XCFG_ODENABLE 0x00000001 /* output driver enable */ 140 #define BE_BR_XCFG_RESV 0x00000002 /* reserved, write as 1 */ 141 #define BE_BR_XCFG_MLBACK 0x00000004 /* loopback-mode mii enable */ 142 #define BE_BR_XCFG_SMODE 0x00000008 /* enable serial mode */ 143 144 /* be_bregs.stat: status, clear on read. */ 145 #define BE_BR_STAT_GOTFRAME 0x00000001 /* received a frame */ 146 #define BE_BR_STAT_RCNTEXP 0x00000002 /* rx frame cntr expired */ 147 #define BE_BR_STAT_ACNTEXP 0x00000004 /* align-error cntr expired */ 148 #define BE_BR_STAT_CCNTEXP 0x00000008 /* crc-error cntr expired */ 149 #define BE_BR_STAT_LCNTEXP 0x00000010 /* length-error cntr expired */ 150 #define BE_BR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 151 #define BE_BR_STAT_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 152 #define BE_BR_STAT_SENTFRAME 0x00000100 /* transmitted a frame */ 153 #define BE_BR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 154 #define BE_BR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 155 #define BE_BR_STAT_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 156 #define BE_BR_STAT_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 157 #define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 158 #define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */ 159 #define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */ 160 #define BE_BR_STAT_BITS "\177\020" \ 161 "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \ 162 "b\3CCNTEXP\0b\5LCNTEXP\0b\6RFIFOVF\0" \ 163 "b\7CVCNTEXP\0b\10SENTFRAME\0b\11TFIFO_UND\0" \ 164 "b\12MAXPKTERR\0b\13NCNTEXP\0b\14ECNTEXP\0" \ 165 "b\15LCCNTEXP\0b\16FCNTEXP\0b\17DTIMEXP\0\0" 166 167 /* be_bregs.imask: interrupt mask. */ 168 #define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */ 169 #define BE_BR_IMASK_RCNTEXP 0x00000002 /* rx frame cntr expired */ 170 #define BE_BR_IMASK_ACNTEXP 0x00000004 /* align-error cntr expired */ 171 #define BE_BR_IMASK_CCNTEXP 0x00000008 /* crc-error cntr expired */ 172 #define BE_BR_IMASK_LCNTEXP 0x00000010 /* length-error cntr expired */ 173 #define BE_BR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */ 174 #define BE_BR_IMASK_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 175 #define BE_BR_IMASK_SENTFRAME 0x00000100 /* transmitted a frame */ 176 #define BE_BR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */ 177 #define BE_BR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */ 178 #define BE_BR_IMASK_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 179 #define BE_BR_IMASK_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 180 #define BE_BR_IMASK_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 181 #define BE_BR_IMASK_FCNTEXP 0x00004000 /* first-collision cntr exp */ 182 #define BE_BR_IMASK_DTIMEXP 0x00008000 /* defer-timer expired */ 183 184 /* be_bregs.tx_cfg: tx config. */ 185 #define BE_BR_TXCFG_ENABLE 0x00000001 /* enable the transmitter */ 186 #define BE_BR_TXCFG_FIFO 0x00000010 /* default tx fthresh */ 187 #define BE_BR_TXCFG_SMODE 0x00000020 /* enable slow transmit mode */ 188 #define BE_BR_TXCFG_CIGN 0x00000040 /* ignore tx collisions */ 189 #define BE_BR_TXCFG_FCSOFF 0x00000080 /* do not emit fcs */ 190 #define BE_BR_TXCFG_DBACKOFF 0x00000100 /* disable backoff */ 191 #define BE_BR_TXCFG_FULLDPLX 0x00000200 /* enable full-duplex */ 192 193 /* be_bregs.rx_cfg: rx config. */ 194 #define BE_BR_RXCFG_ENABLE 0x00000001 /* enable the receiver */ 195 #define BE_BR_RXCFG_FIFO 0x0000000e /* default rx fthresh */ 196 #define BE_BR_RXCFG_PSTRIP 0x00000020 /* pad byte strip enable */ 197 #define BE_BR_RXCFG_PMISC 0x00000040 /* enable promiscuous mode */ 198 #define BE_BR_RXCFG_DERR 0x00000080 /* disable error checking */ 199 #define BE_BR_RXCFG_DCRCS 0x00000100 /* disable crc stripping */ 200 #define BE_BR_RXCFG_ME 0x00000200 /* receive packets for me */ 201 #define BE_BR_RXCFG_PGRP 0x00000400 /* enable promisc group mode */ 202 #define BE_BR_RXCFG_HENABLE 0x00000800 /* enable hash filter */ 203 #define BE_BR_RXCFG_AENABLE 0x00001000 /* enable address filter */ 204 205 /* 206 * BE Channel registers 207 */ 208 #if 0 209 struct be_cregs { 210 uint32_t ctrl; /* control */ 211 uint32_t stat; /* status */ 212 uint32_t rxds; /* rx descriptor ring ptr */ 213 uint32_t txds; /* tx descriptor ring ptr */ 214 uint32_t rimask; /* rx interrupt mask */ 215 uint32_t timask; /* tx interrupt mask */ 216 uint32_t qmask; /* qec error interrupt mask */ 217 uint32_t bmask; /* be error interrupt mask */ 218 uint32_t rxwbufptr; /* local memory rx write ptr */ 219 uint32_t rxrbufptr; /* local memory rx read ptr */ 220 uint32_t txwbufptr; /* local memory tx write ptr */ 221 uint32_t txrbufptr; /* local memory tx read ptr */ 222 uint32_t ccnt; /* collision counter */ 223 }; 224 #endif 225 /* register indices: */ 226 #define BE_CRI_CTRL (0*4) 227 #define BE_CRI_STAT (1*4) 228 #define BE_CRI_RXDS (2*4) 229 #define BE_CRI_TXDS (3*4) 230 #define BE_CRI_RIMASK (4*4) 231 #define BE_CRI_TIMASK (5*4) 232 #define BE_CRI_QMASK (6*4) 233 #define BE_CRI_BMASK (7*4) 234 #define BE_CRI_RXWBUF (8*4) 235 #define BE_CRI_RXRBUF (9*4) 236 #define BE_CRI_TXWBUF (10*4) 237 #define BE_CRI_TXRBUF (11*4) 238 #define BE_CRI_CCNT (12*4) 239 240 /* be_cregs.ctrl: control. */ 241 #define BE_CR_CTRL_TWAKEUP 0x00000001 /* tx DMA wakeup */ 242 243 /* be_cregs.stat: status. */ 244 #define BE_CR_STAT_BERROR 0x80000000 /* be error */ 245 #define BE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ 246 #define BE_CR_STAT_TXDERR 0x00080000 /* tx descriptor is bad */ 247 #define BE_CR_STAT_TXLERR 0x00040000 /* tx late error */ 248 #define BE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ 249 #define BE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ 250 #define BE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ 251 #define BE_CR_STAT_RXDROP 0x00000010 /* rx packet dropped */ 252 #define BE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ 253 #define BE_CR_STAT_RXLERR 0x00000004 /* rx late error */ 254 #define BE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ 255 #define BE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ 256 257 /* be_cregs.qmask: qec error interrupt mask. */ 258 #define BE_CR_QMASK_TXDERR 0x00080000 /* tx descriptor is bad */ 259 #define BE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ 260 #define BE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ 261 #define BE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ 262 #define BE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ 263 #define BE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ 264 #define BE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ 265 #define BE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ 266 #define BE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ 267 268 /* 269 * BE Transceiver registers 270 */ 271 #if 0 272 struct be_tregs { 273 uint32_t tcvr_pal; /* transceiver pal */ 274 uint32_t mgmt_pal; /* management pal */ 275 }; 276 #endif 277 /* register indices: */ 278 #define BE_TRI_TCVRPAL 0 279 #define BE_TRI_MGMTPAL 4 280 281 /* be_tregs.tcvr_pal: transceiver pal */ 282 #define TCVR_PAL_SERIAL 0x00000001 /* serial mode enable */ 283 #define TCVR_PAL_EXTLBACK 0x00000002 /* external loopback */ 284 #define TCVR_PAL_MSENSE 0x00000004 /* media sense */ 285 #define TCVR_PAL_LTENABLE 0x00000008 /* link test enable */ 286 #define TCVR_PAL_LTSTATUS 0x00000010 /* link test status: p1 only */ 287 #define TCVR_PAL_BITS "\177\020" \ 288 "b\0SERIAL\0b\1EXTLBACK\0b\2MSENSE\0" \ 289 "b\3LTENABLE\0\b4LTSTATUS\0\0" 290 291 /* be_tregs.mgmt_pal: management pal */ 292 #define MGMT_PAL_DCLOCK 0x00000001 /* data clock strobe */ 293 #define MGMT_PAL_OENAB 0x00000002 /* output enable */ 294 #define MGMT_PAL_MDIO 0x00000004 /* MDIO data/attached */ 295 #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO /* external mdio */ 296 #define MGMT_PAL_EXT_MDIO_SHIFT 2 /* position of ext mdio bit */ 297 #define MGMT_PAL_TIMEO 0x00000008 /* tx enable timeout error */ 298 #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO /* internal mdio */ 299 #define MGMT_PAL_INT_MDIO_SHIFT 3 /* position of int mdio bit */ 300 #define MGMT_PAL_BITS "\177\020" \ 301 "b\0DLCLOCK\0b\1OENAB\0b\2EXT_MDIO\0" \ 302 "b\3INT_MDIO\0\0" 303 304 /* Packet buffer size */ 305 #define BE_PKT_BUF_SZ 2048 306 307 #define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */ 308 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 309 310 /* PHY addresses */ 311 #define BE_PHY_EXTERNAL 0 312 #define BE_PHY_INTERNAL 1 313