1 /* $OpenBSD: bereg.h,v 1.2 2003/06/02 18:32:41 jason Exp $ */ 2 /* $NetBSD: bereg.h,v 1.4 2000/07/24 04:28:51 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * BE Global registers 67 */ 68 #if 0 69 struct be_bregs { 70 u_int32_t xif_cfg; /* XIF config */ 71 u_int32_t _unused[63]; /* reserved */ 72 u_int32_t stat; /* status, clear on read */ 73 u_int32_t imask; /* interrupt mask */ 74 u_int32_t _unused2[64]; /* reserved */ 75 u_int32_t tx_swreset; /* tx software reset */ 76 u_int32_t tx_cfg; /* tx config */ 77 u_int32_t ipkt_gap1; /* inter-packet gap 1 */ 78 u_int32_t ipkt_gap2; /* inter-packet gap 2 */ 79 u_int32_t attempt_limit; /* tx attempt limit */ 80 u_int32_t stime; /* tx slot time */ 81 u_int32_t preamble_len; /* size of tx preamble */ 82 u_int32_t preamble_pattern; /* pattern for tx preamble */ 83 u_int32_t tx_sframe_delim; /* tx delimiter */ 84 u_int32_t jsize; /* jam length */ 85 u_int32_t tx_pkt_max; /* tx max pkt size */ 86 u_int32_t tx_pkt_min; /* tx min pkt size */ 87 u_int32_t peak_attempt; /* count of tx peak attempts */ 88 u_int32_t dt_ctr; /* tx defer timer */ 89 u_int32_t nc_ctr; /* tx normal collision cntr */ 90 u_int32_t fc_ctr; /* tx first-collision cntr */ 91 u_int32_t ex_ctr; /* tx excess-collision cntr */ 92 u_int32_t lt_ctr; /* tx late-collision cntr */ 93 u_int32_t rand_seed; /* tx random number seed */ 94 u_int32_t tx_smachine; /* tx state machine */ 95 u_int32_t _unused3[44]; /* reserved */ 96 u_int32_t rx_swreset; /* rx software reset */ 97 u_int32_t rx_cfg; /* rx config register */ 98 u_int32_t rx_pkt_max; /* rx max pkt size */ 99 u_int32_t rx_pkt_min; /* rx min pkt size */ 100 u_int32_t mac_addr2; /* ethernet address 2 (MSB) */ 101 u_int32_t mac_addr1; /* ethernet address 1 */ 102 u_int32_t mac_addr0; /* ethernet address 0 (LSB) */ 103 u_int32_t fr_ctr; /* rx frame receive cntr */ 104 u_int32_t gle_ctr; /* rx giant-len error cntr */ 105 u_int32_t unale_ctr; /* rx unaligned error cntr */ 106 u_int32_t rcrce_ctr; /* rx CRC error cntr */ 107 u_int32_t rx_smachine; /* rx state machine */ 108 u_int32_t rx_cvalid; /* rx code violation */ 109 u_int32_t _unused4; /* reserved */ 110 u_int32_t htable3; /* hash table 3 */ 111 u_int32_t htable2; /* hash table 2 */ 112 u_int32_t htable1; /* hash table 1 */ 113 u_int32_t htable0; /* hash table 0 */ 114 u_int32_t afilter2; /* address filter 2 */ 115 u_int32_t afilter1; /* address filter 1 */ 116 u_int32_t afilter0; /* address filter 0 */ 117 u_int32_t afilter_mask; /* address filter mask */ 118 }; 119 #endif 120 /* register indices: */ 121 #define BE_BRI_XIFCFG (0*4) 122 #define BE_BRI_STAT (64*4) 123 #define BE_BRI_IMASK (65*4) 124 #define BE_BRI_TXCFG (131*4) 125 #define BE_BRI_JSIZE (139*4) 126 #define BE_BRI_NCCNT (144*4) 127 #define BE_BRI_FCCNT (145*4) 128 #define BE_BRI_EXCNT (146*4) 129 #define BE_BRI_LTCNT (147*4) 130 #define BE_BRI_RANDSEED (148*4) 131 #define BE_BRI_RXCFG (195*4) 132 #define BE_BRI_MACADDR2 (198*4) 133 #define BE_BRI_MACADDR1 (199*4) 134 #define BE_BRI_MACADDR0 (200*4) 135 #define BE_BRI_HASHTAB3 (208*4) 136 #define BE_BRI_HASHTAB2 (209*4) 137 #define BE_BRI_HASHTAB1 (210*4) 138 #define BE_BRI_HASHTAB0 (211*4) 139 140 /* be_bregs.xif_cfg: XIF config. */ 141 #define BE_BR_XCFG_ODENABLE 0x00000001 /* output driver enable */ 142 #define BE_BR_XCFG_RESV 0x00000002 /* reserved, write as 1 */ 143 #define BE_BR_XCFG_MLBACK 0x00000004 /* loopback-mode mii enable */ 144 #define BE_BR_XCFG_SMODE 0x00000008 /* enable serial mode */ 145 146 /* be_bregs.stat: status, clear on read. */ 147 #define BE_BR_STAT_GOTFRAME 0x00000001 /* received a frame */ 148 #define BE_BR_STAT_RCNTEXP 0x00000002 /* rx frame cntr expired */ 149 #define BE_BR_STAT_ACNTEXP 0x00000004 /* align-error cntr expired */ 150 #define BE_BR_STAT_CCNTEXP 0x00000008 /* crc-error cntr expired */ 151 #define BE_BR_STAT_LCNTEXP 0x00000010 /* length-error cntr expired */ 152 #define BE_BR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 153 #define BE_BR_STAT_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 154 #define BE_BR_STAT_SENTFRAME 0x00000100 /* transmitted a frame */ 155 #define BE_BR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 156 #define BE_BR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 157 #define BE_BR_STAT_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 158 #define BE_BR_STAT_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 159 #define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 160 #define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */ 161 #define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */ 162 #define BE_BR_STAT_BITS "\177\020" \ 163 "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \ 164 "b\3CCNTEXP\0b\5LCNTEXP\0b\6RFIFOVF\0" \ 165 "b\7CVCNTEXP\0b\10SENTFRAME\0b\11TFIFO_UND\0" \ 166 "b\12MAXPKTERR\0b\13NCNTEXP\0b\14ECNTEXP\0" \ 167 "b\15LCCNTEXP\0b\16FCNTEXP\0b\17DTIMEXP\0\0" 168 169 /* be_bregs.imask: interrupt mask. */ 170 #define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */ 171 #define BE_BR_IMASK_RCNTEXP 0x00000002 /* rx frame cntr expired */ 172 #define BE_BR_IMASK_ACNTEXP 0x00000004 /* align-error cntr expired */ 173 #define BE_BR_IMASK_CCNTEXP 0x00000008 /* crc-error cntr expired */ 174 #define BE_BR_IMASK_LCNTEXP 0x00000010 /* length-error cntr expired */ 175 #define BE_BR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */ 176 #define BE_BR_IMASK_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 177 #define BE_BR_IMASK_SENTFRAME 0x00000100 /* transmitted a frame */ 178 #define BE_BR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */ 179 #define BE_BR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */ 180 #define BE_BR_IMASK_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 181 #define BE_BR_IMASK_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 182 #define BE_BR_IMASK_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 183 #define BE_BR_IMASK_FCNTEXP 0x00004000 /* first-collision cntr exp */ 184 #define BE_BR_IMASK_DTIMEXP 0x00008000 /* defer-timer expired */ 185 186 /* be_bregs.tx_cfg: tx config. */ 187 #define BE_BR_TXCFG_ENABLE 0x00000001 /* enable the transmitter */ 188 #define BE_BR_TXCFG_FIFO 0x00000010 /* default tx fthresh */ 189 #define BE_BR_TXCFG_SMODE 0x00000020 /* enable slow transmit mode */ 190 #define BE_BR_TXCFG_CIGN 0x00000040 /* ignore tx collisions */ 191 #define BE_BR_TXCFG_FCSOFF 0x00000080 /* do not emit fcs */ 192 #define BE_BR_TXCFG_DBACKOFF 0x00000100 /* disable backoff */ 193 #define BE_BR_TXCFG_FULLDPLX 0x00000200 /* enable full-duplex */ 194 195 /* be_bregs.rx_cfg: rx config. */ 196 #define BE_BR_RXCFG_ENABLE 0x00000001 /* enable the receiver */ 197 #define BE_BR_RXCFG_FIFO 0x0000000e /* default rx fthresh */ 198 #define BE_BR_RXCFG_PSTRIP 0x00000020 /* pad byte strip enable */ 199 #define BE_BR_RXCFG_PMISC 0x00000040 /* enable promiscous mode */ 200 #define BE_BR_RXCFG_DERR 0x00000080 /* disable error checking */ 201 #define BE_BR_RXCFG_DCRCS 0x00000100 /* disable crc stripping */ 202 #define BE_BR_RXCFG_ME 0x00000200 /* receive packets for me */ 203 #define BE_BR_RXCFG_PGRP 0x00000400 /* enable promisc group mode */ 204 #define BE_BR_RXCFG_HENABLE 0x00000800 /* enable hash filter */ 205 #define BE_BR_RXCFG_AENABLE 0x00001000 /* enable address filter */ 206 207 /* 208 * BE Channel registers 209 */ 210 #if 0 211 struct be_cregs { 212 u_int32_t ctrl; /* control */ 213 u_int32_t stat; /* status */ 214 u_int32_t rxds; /* rx descriptor ring ptr */ 215 u_int32_t txds; /* tx descriptor ring ptr */ 216 u_int32_t rimask; /* rx interrupt mask */ 217 u_int32_t timask; /* tx interrupt mask */ 218 u_int32_t qmask; /* qec error interrupt mask */ 219 u_int32_t bmask; /* be error interrupt mask */ 220 u_int32_t rxwbufptr; /* local memory rx write ptr */ 221 u_int32_t rxrbufptr; /* local memory rx read ptr */ 222 u_int32_t txwbufptr; /* local memory tx write ptr */ 223 u_int32_t txrbufptr; /* local memory tx read ptr */ 224 u_int32_t ccnt; /* collision counter */ 225 }; 226 #endif 227 /* register indices: */ 228 #define BE_CRI_CTRL (0*4) 229 #define BE_CRI_STAT (1*4) 230 #define BE_CRI_RXDS (2*4) 231 #define BE_CRI_TXDS (3*4) 232 #define BE_CRI_RIMASK (4*4) 233 #define BE_CRI_TIMASK (5*4) 234 #define BE_CRI_QMASK (6*4) 235 #define BE_CRI_BMASK (7*4) 236 #define BE_CRI_RXWBUF (8*4) 237 #define BE_CRI_RXRBUF (9*4) 238 #define BE_CRI_TXWBUF (10*4) 239 #define BE_CRI_TXRBUF (11*4) 240 #define BE_CRI_CCNT (12*4) 241 242 /* be_cregs.ctrl: control. */ 243 #define BE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */ 244 245 /* be_cregs.stat: status. */ 246 #define BE_CR_STAT_BERROR 0x80000000 /* be error */ 247 #define BE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ 248 #define BE_CR_STAT_TXDERR 0x00080000 /* tx descriptor is bad */ 249 #define BE_CR_STAT_TXLERR 0x00040000 /* tx late error */ 250 #define BE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ 251 #define BE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ 252 #define BE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ 253 #define BE_CR_STAT_RXDROP 0x00000010 /* rx packet dropped */ 254 #define BE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ 255 #define BE_CR_STAT_RXLERR 0x00000004 /* rx late error */ 256 #define BE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ 257 #define BE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ 258 259 /* be_cregs.qmask: qec error interrupt mask. */ 260 #define BE_CR_QMASK_TXDERR 0x00080000 /* tx descriptor is bad */ 261 #define BE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ 262 #define BE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ 263 #define BE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ 264 #define BE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ 265 #define BE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ 266 #define BE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ 267 #define BE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ 268 #define BE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ 269 270 /* 271 * BE Transceiver registers 272 */ 273 #if 0 274 struct be_tregs { 275 u_int32_t tcvr_pal; /* transceiver pal */ 276 u_int32_t mgmt_pal; /* management pal */ 277 }; 278 #endif 279 /* register indices: */ 280 #define BE_TRI_TCVRPAL 0 281 #define BE_TRI_MGMTPAL 4 282 283 /* be_tregs.tcvr_pal: transceiver pal */ 284 #define TCVR_PAL_SERIAL 0x00000001 /* serial mode enable */ 285 #define TCVR_PAL_EXTLBACK 0x00000002 /* external loopback */ 286 #define TCVR_PAL_MSENSE 0x00000004 /* media sense */ 287 #define TCVR_PAL_LTENABLE 0x00000008 /* link test enable */ 288 #define TCVR_PAL_LTSTATUS 0x00000010 /* link test status: p1 only */ 289 #define TCVR_PAL_BITS "\177\020" \ 290 "b\0SERIAL\0b\1EXTLBACK\0b\2MSENSE\0" \ 291 "b\3LTENABLE\0\b4LTSTATUS\0\0" 292 293 /* be_tregs.mgmt_pal: management pal */ 294 #define MGMT_PAL_DCLOCK 0x00000001 /* data clock strobe */ 295 #define MGMT_PAL_OENAB 0x00000002 /* output enable */ 296 #define MGMT_PAL_MDIO 0x00000004 /* MDIO data/attached */ 297 #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO /* external mdio */ 298 #define MGMT_PAL_EXT_MDIO_SHIFT 2 /* position of ext mdio bit */ 299 #define MGMT_PAL_TIMEO 0x00000008 /* tx enable timeout error */ 300 #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO /* internal mdio */ 301 #define MGMT_PAL_INT_MDIO_SHIFT 3 /* position of int mdio bit */ 302 #define MGMT_PAL_BITS "\177\020" \ 303 "b\0DLCLOCK\0b\1OENAB\0b\2EXT_MDIO\0" \ 304 "b\3INT_MDIO\0\0" 305 306 /* Packet buffer size */ 307 #define BE_PKT_BUF_SZ 2048 308 309 #define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */ 310 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 311 312 /* PHY addresses */ 313 #define BE_PHY_EXTERNAL 0 314 #define BE_PHY_INTERNAL 1 315