1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
128
129 #include <net/if.h>
130 #include <net/if_var.h>
131 #include <net/if_arp.h>
132 #include <net/ethernet.h>
133 #include <net/if_dl.h>
134 #include <net/if_media.h>
135 #include <net/if_types.h>
136 #include <net/if_vlan_var.h>
137
138 #include <net/bpf.h>
139
140 #include <machine/bus.h>
141 #include <machine/resource.h>
142 #include <sys/bus.h>
143 #include <sys/rman.h>
144
145 #include <dev/mii/mii.h>
146 #include <dev/mii/miivar.h>
147
148 #include <dev/pci/pcireg.h>
149 #include <dev/pci/pcivar.h>
150
151 #include <dev/rl/if_rlreg.h>
152
153 MODULE_DEPEND(re, pci, 1, 1, 1);
154 MODULE_DEPEND(re, ether, 1, 1, 1);
155 MODULE_DEPEND(re, miibus, 1, 1, 1);
156
157 /* "device miibus" required. See GENERIC if you get errors here. */
158 #include "miibus_if.h"
159
160 /* Tunables. */
161 static int intr_filter = 0;
162 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
163 static int msi_disable = 0;
164 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
165 static int msix_disable = 0;
166 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
167 static int prefer_iomap = 0;
168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169
170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
171
172 /*
173 * Various supported device vendors/types and their names.
174 */
175 static const struct rl_type re_devs[] = {
176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
180 { RT_VENDORID, RT_DEVICEID_8139, 0,
181 "RealTek 8139C+ 10/100BaseTX" },
182 { RT_VENDORID, RT_DEVICEID_8101E, 0,
183 "RealTek 810xE PCIe 10/100baseTX" },
184 { RT_VENDORID, RT_DEVICEID_8168, 0,
185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
186 { RT_VENDORID, RT_DEVICEID_8169, 0,
187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
188 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
194 { USR_VENDORID, USR_DEVICEID_997902, 0,
195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
196 };
197
198 static const struct rl_hwrev re_hwrevs[] = {
199 { RL_HWREV_8139, RL_8139, "", RL_MTU },
200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
241 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K},
242 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
243 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
244 { 0, 0, NULL, 0 }
245 };
246
247 static int re_probe (device_t);
248 static int re_attach (device_t);
249 static int re_detach (device_t);
250
251 static int re_encap (struct rl_softc *, struct mbuf **);
252
253 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
254 static int re_allocmem (device_t, struct rl_softc *);
255 static __inline void re_discard_rxbuf
256 (struct rl_softc *, int);
257 static int re_newbuf (struct rl_softc *, int);
258 static int re_jumbo_newbuf (struct rl_softc *, int);
259 static int re_rx_list_init (struct rl_softc *);
260 static int re_jrx_list_init (struct rl_softc *);
261 static int re_tx_list_init (struct rl_softc *);
262 #ifdef RE_FIXUP_RX
263 static __inline void re_fixup_rx
264 (struct mbuf *);
265 #endif
266 static int re_rxeof (struct rl_softc *, int *);
267 static void re_txeof (struct rl_softc *);
268 #ifdef DEVICE_POLLING
269 static int re_poll (struct ifnet *, enum poll_cmd, int);
270 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
271 #endif
272 static int re_intr (void *);
273 static void re_intr_msi (void *);
274 static void re_tick (void *);
275 static void re_int_task (void *, int);
276 static void re_start (struct ifnet *);
277 static void re_start_locked (struct ifnet *);
278 static int re_ioctl (struct ifnet *, u_long, caddr_t);
279 static void re_init (void *);
280 static void re_init_locked (struct rl_softc *);
281 static void re_stop (struct rl_softc *);
282 static void re_watchdog (struct rl_softc *);
283 static int re_suspend (device_t);
284 static int re_resume (device_t);
285 static int re_shutdown (device_t);
286 static int re_ifmedia_upd (struct ifnet *);
287 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
288
289 static void re_eeprom_putbyte (struct rl_softc *, int);
290 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
291 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
292 static int re_gmii_readreg (device_t, int, int);
293 static int re_gmii_writereg (device_t, int, int, int);
294
295 static int re_miibus_readreg (device_t, int, int);
296 static int re_miibus_writereg (device_t, int, int, int);
297 static void re_miibus_statchg (device_t);
298
299 static void re_set_jumbo (struct rl_softc *, int);
300 static void re_set_rxmode (struct rl_softc *);
301 static void re_reset (struct rl_softc *);
302 static void re_setwol (struct rl_softc *);
303 static void re_clrwol (struct rl_softc *);
304 static void re_set_linkspeed (struct rl_softc *);
305
306 #ifdef DEV_NETMAP /* see ixgbe.c for details */
307 #include <dev/netmap/if_re_netmap.h>
308 MODULE_DEPEND(re, netmap, 1, 1, 1);
309 #endif /* !DEV_NETMAP */
310
311 #ifdef RE_DIAG
312 static int re_diag (struct rl_softc *);
313 #endif
314
315 static void re_add_sysctls (struct rl_softc *);
316 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
317 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
318 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
319
320 static device_method_t re_methods[] = {
321 /* Device interface */
322 DEVMETHOD(device_probe, re_probe),
323 DEVMETHOD(device_attach, re_attach),
324 DEVMETHOD(device_detach, re_detach),
325 DEVMETHOD(device_suspend, re_suspend),
326 DEVMETHOD(device_resume, re_resume),
327 DEVMETHOD(device_shutdown, re_shutdown),
328
329 /* MII interface */
330 DEVMETHOD(miibus_readreg, re_miibus_readreg),
331 DEVMETHOD(miibus_writereg, re_miibus_writereg),
332 DEVMETHOD(miibus_statchg, re_miibus_statchg),
333
334 DEVMETHOD_END
335 };
336
337 static driver_t re_driver = {
338 "re",
339 re_methods,
340 sizeof(struct rl_softc)
341 };
342
343 static devclass_t re_devclass;
344
345 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
346 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
347
348 #define EE_SET(x) \
349 CSR_WRITE_1(sc, RL_EECMD, \
350 CSR_READ_1(sc, RL_EECMD) | x)
351
352 #define EE_CLR(x) \
353 CSR_WRITE_1(sc, RL_EECMD, \
354 CSR_READ_1(sc, RL_EECMD) & ~x)
355
356 /*
357 * Send a read command and address to the EEPROM, check for ACK.
358 */
359 static void
re_eeprom_putbyte(struct rl_softc * sc,int addr)360 re_eeprom_putbyte(struct rl_softc *sc, int addr)
361 {
362 int d, i;
363
364 d = addr | (RL_9346_READ << sc->rl_eewidth);
365
366 /*
367 * Feed in each bit and strobe the clock.
368 */
369
370 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
371 if (d & i) {
372 EE_SET(RL_EE_DATAIN);
373 } else {
374 EE_CLR(RL_EE_DATAIN);
375 }
376 DELAY(100);
377 EE_SET(RL_EE_CLK);
378 DELAY(150);
379 EE_CLR(RL_EE_CLK);
380 DELAY(100);
381 }
382 }
383
384 /*
385 * Read a word of data stored in the EEPROM at address 'addr.'
386 */
387 static void
re_eeprom_getword(struct rl_softc * sc,int addr,u_int16_t * dest)388 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
389 {
390 int i;
391 u_int16_t word = 0;
392
393 /*
394 * Send address of word we want to read.
395 */
396 re_eeprom_putbyte(sc, addr);
397
398 /*
399 * Start reading bits from EEPROM.
400 */
401 for (i = 0x8000; i; i >>= 1) {
402 EE_SET(RL_EE_CLK);
403 DELAY(100);
404 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
405 word |= i;
406 EE_CLR(RL_EE_CLK);
407 DELAY(100);
408 }
409
410 *dest = word;
411 }
412
413 /*
414 * Read a sequence of words from the EEPROM.
415 */
416 static void
re_read_eeprom(struct rl_softc * sc,caddr_t dest,int off,int cnt)417 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
418 {
419 int i;
420 u_int16_t word = 0, *ptr;
421
422 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
423
424 DELAY(100);
425
426 for (i = 0; i < cnt; i++) {
427 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
428 re_eeprom_getword(sc, off + i, &word);
429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
430 ptr = (u_int16_t *)(dest + (i * 2));
431 *ptr = word;
432 }
433
434 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
435 }
436
437 static int
re_gmii_readreg(device_t dev,int phy,int reg)438 re_gmii_readreg(device_t dev, int phy, int reg)
439 {
440 struct rl_softc *sc;
441 u_int32_t rval;
442 int i;
443
444 sc = device_get_softc(dev);
445
446 /* Let the rgephy driver read the GMEDIASTAT register */
447
448 if (reg == RL_GMEDIASTAT) {
449 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
450 return (rval);
451 }
452
453 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
454
455 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
456 rval = CSR_READ_4(sc, RL_PHYAR);
457 if (rval & RL_PHYAR_BUSY)
458 break;
459 DELAY(25);
460 }
461
462 if (i == RL_PHY_TIMEOUT) {
463 device_printf(sc->rl_dev, "PHY read failed\n");
464 return (0);
465 }
466
467 /*
468 * Controller requires a 20us delay to process next MDIO request.
469 */
470 DELAY(20);
471
472 return (rval & RL_PHYAR_PHYDATA);
473 }
474
475 static int
re_gmii_writereg(device_t dev,int phy,int reg,int data)476 re_gmii_writereg(device_t dev, int phy, int reg, int data)
477 {
478 struct rl_softc *sc;
479 u_int32_t rval;
480 int i;
481
482 sc = device_get_softc(dev);
483
484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
486
487 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
488 rval = CSR_READ_4(sc, RL_PHYAR);
489 if (!(rval & RL_PHYAR_BUSY))
490 break;
491 DELAY(25);
492 }
493
494 if (i == RL_PHY_TIMEOUT) {
495 device_printf(sc->rl_dev, "PHY write failed\n");
496 return (0);
497 }
498
499 /*
500 * Controller requires a 20us delay to process next MDIO request.
501 */
502 DELAY(20);
503
504 return (0);
505 }
506
507 static int
re_miibus_readreg(device_t dev,int phy,int reg)508 re_miibus_readreg(device_t dev, int phy, int reg)
509 {
510 struct rl_softc *sc;
511 u_int16_t rval = 0;
512 u_int16_t re8139_reg = 0;
513
514 sc = device_get_softc(dev);
515
516 if (sc->rl_type == RL_8169) {
517 rval = re_gmii_readreg(dev, phy, reg);
518 return (rval);
519 }
520
521 switch (reg) {
522 case MII_BMCR:
523 re8139_reg = RL_BMCR;
524 break;
525 case MII_BMSR:
526 re8139_reg = RL_BMSR;
527 break;
528 case MII_ANAR:
529 re8139_reg = RL_ANAR;
530 break;
531 case MII_ANER:
532 re8139_reg = RL_ANER;
533 break;
534 case MII_ANLPAR:
535 re8139_reg = RL_LPAR;
536 break;
537 case MII_PHYIDR1:
538 case MII_PHYIDR2:
539 return (0);
540 /*
541 * Allow the rlphy driver to read the media status
542 * register. If we have a link partner which does not
543 * support NWAY, this is the register which will tell
544 * us the results of parallel detection.
545 */
546 case RL_MEDIASTAT:
547 rval = CSR_READ_1(sc, RL_MEDIASTAT);
548 return (rval);
549 default:
550 device_printf(sc->rl_dev, "bad phy register\n");
551 return (0);
552 }
553 rval = CSR_READ_2(sc, re8139_reg);
554 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
555 /* 8139C+ has different bit layout. */
556 rval &= ~(BMCR_LOOP | BMCR_ISO);
557 }
558 return (rval);
559 }
560
561 static int
re_miibus_writereg(device_t dev,int phy,int reg,int data)562 re_miibus_writereg(device_t dev, int phy, int reg, int data)
563 {
564 struct rl_softc *sc;
565 u_int16_t re8139_reg = 0;
566 int rval = 0;
567
568 sc = device_get_softc(dev);
569
570 if (sc->rl_type == RL_8169) {
571 rval = re_gmii_writereg(dev, phy, reg, data);
572 return (rval);
573 }
574
575 switch (reg) {
576 case MII_BMCR:
577 re8139_reg = RL_BMCR;
578 if (sc->rl_type == RL_8139CPLUS) {
579 /* 8139C+ has different bit layout. */
580 data &= ~(BMCR_LOOP | BMCR_ISO);
581 }
582 break;
583 case MII_BMSR:
584 re8139_reg = RL_BMSR;
585 break;
586 case MII_ANAR:
587 re8139_reg = RL_ANAR;
588 break;
589 case MII_ANER:
590 re8139_reg = RL_ANER;
591 break;
592 case MII_ANLPAR:
593 re8139_reg = RL_LPAR;
594 break;
595 case MII_PHYIDR1:
596 case MII_PHYIDR2:
597 return (0);
598 break;
599 default:
600 device_printf(sc->rl_dev, "bad phy register\n");
601 return (0);
602 }
603 CSR_WRITE_2(sc, re8139_reg, data);
604 return (0);
605 }
606
607 static void
re_miibus_statchg(device_t dev)608 re_miibus_statchg(device_t dev)
609 {
610 struct rl_softc *sc;
611 struct ifnet *ifp;
612 struct mii_data *mii;
613
614 sc = device_get_softc(dev);
615 mii = device_get_softc(sc->rl_miibus);
616 ifp = sc->rl_ifp;
617 if (mii == NULL || ifp == NULL ||
618 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
619 return;
620
621 sc->rl_flags &= ~RL_FLAG_LINK;
622 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
623 (IFM_ACTIVE | IFM_AVALID)) {
624 switch (IFM_SUBTYPE(mii->mii_media_active)) {
625 case IFM_10_T:
626 case IFM_100_TX:
627 sc->rl_flags |= RL_FLAG_LINK;
628 break;
629 case IFM_1000_T:
630 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
631 break;
632 sc->rl_flags |= RL_FLAG_LINK;
633 break;
634 default:
635 break;
636 }
637 }
638 /*
639 * RealTek controllers do not provide any interface to the RX/TX
640 * MACs for resolved speed, duplex and flow-control parameters.
641 */
642 }
643
644 /*
645 * Set the RX configuration and 64-bit multicast hash filter.
646 */
647 static void
re_set_rxmode(struct rl_softc * sc)648 re_set_rxmode(struct rl_softc *sc)
649 {
650 struct ifnet *ifp;
651 struct ifmultiaddr *ifma;
652 uint32_t hashes[2] = { 0, 0 };
653 uint32_t h, rxfilt;
654
655 RL_LOCK_ASSERT(sc);
656
657 ifp = sc->rl_ifp;
658
659 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
660 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
661 rxfilt |= RL_RXCFG_EARLYOFF;
662 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
663 rxfilt |= RL_RXCFG_EARLYOFFV2;
664
665 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
666 if (ifp->if_flags & IFF_PROMISC)
667 rxfilt |= RL_RXCFG_RX_ALLPHYS;
668 /*
669 * Unlike other hardwares, we have to explicitly set
670 * RL_RXCFG_RX_MULTI to receive multicast frames in
671 * promiscuous mode.
672 */
673 rxfilt |= RL_RXCFG_RX_MULTI;
674 hashes[0] = hashes[1] = 0xffffffff;
675 goto done;
676 }
677
678 if_maddr_rlock(ifp);
679 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
680 if (ifma->ifma_addr->sa_family != AF_LINK)
681 continue;
682 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
683 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
684 if (h < 32)
685 hashes[0] |= (1 << h);
686 else
687 hashes[1] |= (1 << (h - 32));
688 }
689 if_maddr_runlock(ifp);
690
691 if (hashes[0] != 0 || hashes[1] != 0) {
692 /*
693 * For some unfathomable reason, RealTek decided to
694 * reverse the order of the multicast hash registers
695 * in the PCI Express parts. This means we have to
696 * write the hash pattern in reverse order for those
697 * devices.
698 */
699 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
700 h = bswap32(hashes[0]);
701 hashes[0] = bswap32(hashes[1]);
702 hashes[1] = h;
703 }
704 rxfilt |= RL_RXCFG_RX_MULTI;
705 }
706
707 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
708 /* Disable multicast filtering due to silicon bug. */
709 hashes[0] = 0xffffffff;
710 hashes[1] = 0xffffffff;
711 }
712
713 done:
714 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
715 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
716 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
717 }
718
719 static void
re_reset(struct rl_softc * sc)720 re_reset(struct rl_softc *sc)
721 {
722 int i;
723
724 RL_LOCK_ASSERT(sc);
725
726 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
727
728 for (i = 0; i < RL_TIMEOUT; i++) {
729 DELAY(10);
730 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
731 break;
732 }
733 if (i == RL_TIMEOUT)
734 device_printf(sc->rl_dev, "reset never completed!\n");
735
736 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
737 CSR_WRITE_1(sc, 0x82, 1);
738 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
739 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
740 }
741
742 #ifdef RE_DIAG
743
744 /*
745 * The following routine is designed to test for a defect on some
746 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
747 * lines connected to the bus, however for a 32-bit only card, they
748 * should be pulled high. The result of this defect is that the
749 * NIC will not work right if you plug it into a 64-bit slot: DMA
750 * operations will be done with 64-bit transfers, which will fail
751 * because the 64-bit data lines aren't connected.
752 *
753 * There's no way to work around this (short of talking a soldering
754 * iron to the board), however we can detect it. The method we use
755 * here is to put the NIC into digital loopback mode, set the receiver
756 * to promiscuous mode, and then try to send a frame. We then compare
757 * the frame data we sent to what was received. If the data matches,
758 * then the NIC is working correctly, otherwise we know the user has
759 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
760 * slot. In the latter case, there's no way the NIC can work correctly,
761 * so we print out a message on the console and abort the device attach.
762 */
763
764 static int
re_diag(struct rl_softc * sc)765 re_diag(struct rl_softc *sc)
766 {
767 struct ifnet *ifp = sc->rl_ifp;
768 struct mbuf *m0;
769 struct ether_header *eh;
770 struct rl_desc *cur_rx;
771 u_int16_t status;
772 u_int32_t rxstat;
773 int total_len, i, error = 0, phyaddr;
774 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
775 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
776
777 /* Allocate a single mbuf */
778 MGETHDR(m0, M_NOWAIT, MT_DATA);
779 if (m0 == NULL)
780 return (ENOBUFS);
781
782 RL_LOCK(sc);
783
784 /*
785 * Initialize the NIC in test mode. This sets the chip up
786 * so that it can send and receive frames, but performs the
787 * following special functions:
788 * - Puts receiver in promiscuous mode
789 * - Enables digital loopback mode
790 * - Leaves interrupts turned off
791 */
792
793 ifp->if_flags |= IFF_PROMISC;
794 sc->rl_testmode = 1;
795 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
796 re_init_locked(sc);
797 sc->rl_flags |= RL_FLAG_LINK;
798 if (sc->rl_type == RL_8169)
799 phyaddr = 1;
800 else
801 phyaddr = 0;
802
803 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
804 for (i = 0; i < RL_TIMEOUT; i++) {
805 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
806 if (!(status & BMCR_RESET))
807 break;
808 }
809
810 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
811 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
812
813 DELAY(100000);
814
815 /* Put some data in the mbuf */
816
817 eh = mtod(m0, struct ether_header *);
818 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
819 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
820 eh->ether_type = htons(ETHERTYPE_IP);
821 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
822
823 /*
824 * Queue the packet, start transmission.
825 * Note: IF_HANDOFF() ultimately calls re_start() for us.
826 */
827
828 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
829 RL_UNLOCK(sc);
830 /* XXX: re_diag must not be called when in ALTQ mode */
831 IF_HANDOFF(&ifp->if_snd, m0, ifp);
832 RL_LOCK(sc);
833 m0 = NULL;
834
835 /* Wait for it to propagate through the chip */
836
837 DELAY(100000);
838 for (i = 0; i < RL_TIMEOUT; i++) {
839 status = CSR_READ_2(sc, RL_ISR);
840 CSR_WRITE_2(sc, RL_ISR, status);
841 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
842 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
843 break;
844 DELAY(10);
845 }
846
847 if (i == RL_TIMEOUT) {
848 device_printf(sc->rl_dev,
849 "diagnostic failed, failed to receive packet in"
850 " loopback mode\n");
851 error = EIO;
852 goto done;
853 }
854
855 /*
856 * The packet should have been dumped into the first
857 * entry in the RX DMA ring. Grab it from there.
858 */
859
860 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
861 sc->rl_ldata.rl_rx_list_map,
862 BUS_DMASYNC_POSTREAD);
863 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
864 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
865 BUS_DMASYNC_POSTREAD);
866 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
867 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
868
869 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
870 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
871 eh = mtod(m0, struct ether_header *);
872
873 cur_rx = &sc->rl_ldata.rl_rx_list[0];
874 total_len = RL_RXBYTES(cur_rx);
875 rxstat = le32toh(cur_rx->rl_cmdstat);
876
877 if (total_len != ETHER_MIN_LEN) {
878 device_printf(sc->rl_dev,
879 "diagnostic failed, received short packet\n");
880 error = EIO;
881 goto done;
882 }
883
884 /* Test that the received packet data matches what we sent. */
885
886 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
887 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
888 ntohs(eh->ether_type) != ETHERTYPE_IP) {
889 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
890 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
891 dst, ":", src, ":", ETHERTYPE_IP);
892 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
893 eh->ether_dhost, ":", eh->ether_shost, ":",
894 ntohs(eh->ether_type));
895 device_printf(sc->rl_dev, "You may have a defective 32-bit "
896 "NIC plugged into a 64-bit PCI slot.\n");
897 device_printf(sc->rl_dev, "Please re-install the NIC in a "
898 "32-bit slot for proper operation.\n");
899 device_printf(sc->rl_dev, "Read the re(4) man page for more "
900 "details.\n");
901 error = EIO;
902 }
903
904 done:
905 /* Turn interface off, release resources */
906
907 sc->rl_testmode = 0;
908 sc->rl_flags &= ~RL_FLAG_LINK;
909 ifp->if_flags &= ~IFF_PROMISC;
910 re_stop(sc);
911 if (m0 != NULL)
912 m_freem(m0);
913
914 RL_UNLOCK(sc);
915
916 return (error);
917 }
918
919 #endif
920
921 /*
922 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
923 * IDs against our list and return a device name if we find a match.
924 */
925 static int
re_probe(device_t dev)926 re_probe(device_t dev)
927 {
928 const struct rl_type *t;
929 uint16_t devid, vendor;
930 uint16_t revid, sdevid;
931 int i;
932
933 vendor = pci_get_vendor(dev);
934 devid = pci_get_device(dev);
935 revid = pci_get_revid(dev);
936 sdevid = pci_get_subdevice(dev);
937
938 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
939 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
940 /*
941 * Only attach to rev. 3 of the Linksys EG1032 adapter.
942 * Rev. 2 is supported by sk(4).
943 */
944 return (ENXIO);
945 }
946 }
947
948 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
949 if (revid != 0x20) {
950 /* 8139, let rl(4) take care of this device. */
951 return (ENXIO);
952 }
953 }
954
955 t = re_devs;
956 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
957 if (vendor == t->rl_vid && devid == t->rl_did) {
958 device_set_desc(dev, t->rl_name);
959 return (BUS_PROBE_DEFAULT);
960 }
961 }
962
963 return (ENXIO);
964 }
965
966 /*
967 * Map a single buffer address.
968 */
969
970 static void
re_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)971 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
972 {
973 bus_addr_t *addr;
974
975 if (error)
976 return;
977
978 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
979 addr = arg;
980 *addr = segs->ds_addr;
981 }
982
983 static int
re_allocmem(device_t dev,struct rl_softc * sc)984 re_allocmem(device_t dev, struct rl_softc *sc)
985 {
986 bus_addr_t lowaddr;
987 bus_size_t rx_list_size, tx_list_size;
988 int error;
989 int i;
990
991 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
992 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
993
994 /*
995 * Allocate the parent bus DMA tag appropriate for PCI.
996 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
997 * register should be set. However some RealTek chips are known
998 * to be buggy on DAC handling, therefore disable DAC by limiting
999 * DMA address space to 32bit. PCIe variants of RealTek chips
1000 * may not have the limitation.
1001 */
1002 lowaddr = BUS_SPACE_MAXADDR;
1003 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
1004 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1005 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1006 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
1007 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1008 NULL, NULL, &sc->rl_parent_tag);
1009 if (error) {
1010 device_printf(dev, "could not allocate parent DMA tag\n");
1011 return (error);
1012 }
1013
1014 /*
1015 * Allocate map for TX mbufs.
1016 */
1017 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1018 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1019 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1020 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1021 if (error) {
1022 device_printf(dev, "could not allocate TX DMA tag\n");
1023 return (error);
1024 }
1025
1026 /*
1027 * Allocate map for RX mbufs.
1028 */
1029
1030 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1031 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1032 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1033 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1034 &sc->rl_ldata.rl_jrx_mtag);
1035 if (error) {
1036 device_printf(dev,
1037 "could not allocate jumbo RX DMA tag\n");
1038 return (error);
1039 }
1040 }
1041 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1042 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1043 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1044 if (error) {
1045 device_printf(dev, "could not allocate RX DMA tag\n");
1046 return (error);
1047 }
1048
1049 /*
1050 * Allocate map for TX descriptor list.
1051 */
1052 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1053 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1054 NULL, tx_list_size, 1, tx_list_size, 0,
1055 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1056 if (error) {
1057 device_printf(dev, "could not allocate TX DMA ring tag\n");
1058 return (error);
1059 }
1060
1061 /* Allocate DMA'able memory for the TX ring */
1062
1063 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1064 (void **)&sc->rl_ldata.rl_tx_list,
1065 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1066 &sc->rl_ldata.rl_tx_list_map);
1067 if (error) {
1068 device_printf(dev, "could not allocate TX DMA ring\n");
1069 return (error);
1070 }
1071
1072 /* Load the map for the TX ring. */
1073
1074 sc->rl_ldata.rl_tx_list_addr = 0;
1075 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1076 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1077 tx_list_size, re_dma_map_addr,
1078 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1079 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1080 device_printf(dev, "could not load TX DMA ring\n");
1081 return (ENOMEM);
1082 }
1083
1084 /* Create DMA maps for TX buffers */
1085
1086 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1087 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1088 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1089 if (error) {
1090 device_printf(dev, "could not create DMA map for TX\n");
1091 return (error);
1092 }
1093 }
1094
1095 /*
1096 * Allocate map for RX descriptor list.
1097 */
1098 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1099 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1100 NULL, rx_list_size, 1, rx_list_size, 0,
1101 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1102 if (error) {
1103 device_printf(dev, "could not create RX DMA ring tag\n");
1104 return (error);
1105 }
1106
1107 /* Allocate DMA'able memory for the RX ring */
1108
1109 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1110 (void **)&sc->rl_ldata.rl_rx_list,
1111 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1112 &sc->rl_ldata.rl_rx_list_map);
1113 if (error) {
1114 device_printf(dev, "could not allocate RX DMA ring\n");
1115 return (error);
1116 }
1117
1118 /* Load the map for the RX ring. */
1119
1120 sc->rl_ldata.rl_rx_list_addr = 0;
1121 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1122 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1123 rx_list_size, re_dma_map_addr,
1124 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1125 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1126 device_printf(dev, "could not load RX DMA ring\n");
1127 return (ENOMEM);
1128 }
1129
1130 /* Create DMA maps for RX buffers */
1131
1132 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1133 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1134 &sc->rl_ldata.rl_jrx_sparemap);
1135 if (error) {
1136 device_printf(dev,
1137 "could not create spare DMA map for jumbo RX\n");
1138 return (error);
1139 }
1140 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1141 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1142 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1143 if (error) {
1144 device_printf(dev,
1145 "could not create DMA map for jumbo RX\n");
1146 return (error);
1147 }
1148 }
1149 }
1150 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1151 &sc->rl_ldata.rl_rx_sparemap);
1152 if (error) {
1153 device_printf(dev, "could not create spare DMA map for RX\n");
1154 return (error);
1155 }
1156 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1157 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1158 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1159 if (error) {
1160 device_printf(dev, "could not create DMA map for RX\n");
1161 return (error);
1162 }
1163 }
1164
1165 /* Create DMA map for statistics. */
1166 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1167 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1168 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1169 &sc->rl_ldata.rl_stag);
1170 if (error) {
1171 device_printf(dev, "could not create statistics DMA tag\n");
1172 return (error);
1173 }
1174 /* Allocate DMA'able memory for statistics. */
1175 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1176 (void **)&sc->rl_ldata.rl_stats,
1177 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1178 &sc->rl_ldata.rl_smap);
1179 if (error) {
1180 device_printf(dev,
1181 "could not allocate statistics DMA memory\n");
1182 return (error);
1183 }
1184 /* Load the map for statistics. */
1185 sc->rl_ldata.rl_stats_addr = 0;
1186 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1187 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1188 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1189 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1190 device_printf(dev, "could not load statistics DMA memory\n");
1191 return (ENOMEM);
1192 }
1193
1194 return (0);
1195 }
1196
1197 /*
1198 * Attach the interface. Allocate softc structures, do ifmedia
1199 * setup and ethernet/BPF attach.
1200 */
1201 static int
re_attach(device_t dev)1202 re_attach(device_t dev)
1203 {
1204 u_char eaddr[ETHER_ADDR_LEN];
1205 u_int16_t as[ETHER_ADDR_LEN / 2];
1206 struct rl_softc *sc;
1207 struct ifnet *ifp;
1208 const struct rl_hwrev *hw_rev;
1209 int capmask, error = 0, hwrev, i, msic, msixc,
1210 phy, reg, rid;
1211 u_int32_t cap, ctl;
1212 u_int16_t devid, re_did = 0;
1213 uint8_t cfg;
1214
1215 sc = device_get_softc(dev);
1216 sc->rl_dev = dev;
1217
1218 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1219 MTX_DEF);
1220 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1221
1222 /*
1223 * Map control/status registers.
1224 */
1225 pci_enable_busmaster(dev);
1226
1227 devid = pci_get_device(dev);
1228 /*
1229 * Prefer memory space register mapping over IO space.
1230 * Because RTL8169SC does not seem to work when memory mapping
1231 * is used always activate io mapping.
1232 */
1233 if (devid == RT_DEVICEID_8169SC)
1234 prefer_iomap = 1;
1235 if (prefer_iomap == 0) {
1236 sc->rl_res_id = PCIR_BAR(1);
1237 sc->rl_res_type = SYS_RES_MEMORY;
1238 /* RTL8168/8101E seems to use different BARs. */
1239 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1240 sc->rl_res_id = PCIR_BAR(2);
1241 } else {
1242 sc->rl_res_id = PCIR_BAR(0);
1243 sc->rl_res_type = SYS_RES_IOPORT;
1244 }
1245 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1246 &sc->rl_res_id, RF_ACTIVE);
1247 if (sc->rl_res == NULL && prefer_iomap == 0) {
1248 sc->rl_res_id = PCIR_BAR(0);
1249 sc->rl_res_type = SYS_RES_IOPORT;
1250 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1251 &sc->rl_res_id, RF_ACTIVE);
1252 }
1253 if (sc->rl_res == NULL) {
1254 device_printf(dev, "couldn't map ports/memory\n");
1255 error = ENXIO;
1256 goto fail;
1257 }
1258
1259 sc->rl_btag = rman_get_bustag(sc->rl_res);
1260 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1261
1262 msic = pci_msi_count(dev);
1263 msixc = pci_msix_count(dev);
1264 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1265 sc->rl_flags |= RL_FLAG_PCIE;
1266 sc->rl_expcap = reg;
1267 }
1268 if (bootverbose) {
1269 device_printf(dev, "MSI count : %d\n", msic);
1270 device_printf(dev, "MSI-X count : %d\n", msixc);
1271 }
1272 if (msix_disable > 0)
1273 msixc = 0;
1274 if (msi_disable > 0)
1275 msic = 0;
1276 /* Prefer MSI-X to MSI. */
1277 if (msixc > 0) {
1278 msixc = RL_MSI_MESSAGES;
1279 rid = PCIR_BAR(4);
1280 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1281 &rid, RF_ACTIVE);
1282 if (sc->rl_res_pba == NULL) {
1283 device_printf(sc->rl_dev,
1284 "could not allocate MSI-X PBA resource\n");
1285 }
1286 if (sc->rl_res_pba != NULL &&
1287 pci_alloc_msix(dev, &msixc) == 0) {
1288 if (msixc == RL_MSI_MESSAGES) {
1289 device_printf(dev, "Using %d MSI-X message\n",
1290 msixc);
1291 sc->rl_flags |= RL_FLAG_MSIX;
1292 } else
1293 pci_release_msi(dev);
1294 }
1295 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1296 if (sc->rl_res_pba != NULL)
1297 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1298 sc->rl_res_pba);
1299 sc->rl_res_pba = NULL;
1300 msixc = 0;
1301 }
1302 }
1303 /* Prefer MSI to INTx. */
1304 if (msixc == 0 && msic > 0) {
1305 msic = RL_MSI_MESSAGES;
1306 if (pci_alloc_msi(dev, &msic) == 0) {
1307 if (msic == RL_MSI_MESSAGES) {
1308 device_printf(dev, "Using %d MSI message\n",
1309 msic);
1310 sc->rl_flags |= RL_FLAG_MSI;
1311 /* Explicitly set MSI enable bit. */
1312 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1313 cfg = CSR_READ_1(sc, RL_CFG2);
1314 cfg |= RL_CFG2_MSI;
1315 CSR_WRITE_1(sc, RL_CFG2, cfg);
1316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1317 } else
1318 pci_release_msi(dev);
1319 }
1320 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1321 msic = 0;
1322 }
1323
1324 /* Allocate interrupt */
1325 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1326 rid = 0;
1327 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1328 RF_SHAREABLE | RF_ACTIVE);
1329 if (sc->rl_irq[0] == NULL) {
1330 device_printf(dev, "couldn't allocate IRQ resources\n");
1331 error = ENXIO;
1332 goto fail;
1333 }
1334 } else {
1335 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1336 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1337 SYS_RES_IRQ, &rid, RF_ACTIVE);
1338 if (sc->rl_irq[i] == NULL) {
1339 device_printf(dev,
1340 "couldn't allocate IRQ resources for "
1341 "message %d\n", rid);
1342 error = ENXIO;
1343 goto fail;
1344 }
1345 }
1346 }
1347
1348 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1349 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1350 cfg = CSR_READ_1(sc, RL_CFG2);
1351 if ((cfg & RL_CFG2_MSI) != 0) {
1352 device_printf(dev, "turning off MSI enable bit.\n");
1353 cfg &= ~RL_CFG2_MSI;
1354 CSR_WRITE_1(sc, RL_CFG2, cfg);
1355 }
1356 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1357 }
1358
1359 /* Disable ASPM L0S/L1. */
1360 if (sc->rl_expcap != 0) {
1361 cap = pci_read_config(dev, sc->rl_expcap +
1362 PCIER_LINK_CAP, 2);
1363 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1364 ctl = pci_read_config(dev, sc->rl_expcap +
1365 PCIER_LINK_CTL, 2);
1366 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
1367 ctl &= ~PCIEM_LINK_CTL_ASPMC;
1368 pci_write_config(dev, sc->rl_expcap +
1369 PCIER_LINK_CTL, ctl, 2);
1370 device_printf(dev, "ASPM disabled\n");
1371 }
1372 } else
1373 device_printf(dev, "no ASPM capability\n");
1374 }
1375
1376 hw_rev = re_hwrevs;
1377 hwrev = CSR_READ_4(sc, RL_TXCFG);
1378 switch (hwrev & 0x70000000) {
1379 case 0x00000000:
1380 case 0x10000000:
1381 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1382 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1383 break;
1384 default:
1385 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1386 sc->rl_macrev = hwrev & 0x00700000;
1387 hwrev &= RL_TXCFG_HWREV;
1388 break;
1389 }
1390 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1391 while (hw_rev->rl_desc != NULL) {
1392 if (hw_rev->rl_rev == hwrev) {
1393 sc->rl_type = hw_rev->rl_type;
1394 sc->rl_hwrev = hw_rev;
1395 break;
1396 }
1397 hw_rev++;
1398 }
1399 if (hw_rev->rl_desc == NULL) {
1400 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1401 error = ENXIO;
1402 goto fail;
1403 }
1404
1405 switch (hw_rev->rl_rev) {
1406 case RL_HWREV_8139CPLUS:
1407 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1408 break;
1409 case RL_HWREV_8100E:
1410 case RL_HWREV_8101E:
1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1412 break;
1413 case RL_HWREV_8102E:
1414 case RL_HWREV_8102EL:
1415 case RL_HWREV_8102EL_SPIN1:
1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1417 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1418 RL_FLAG_AUTOPAD;
1419 break;
1420 case RL_HWREV_8103E:
1421 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1422 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1423 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1424 break;
1425 case RL_HWREV_8401E:
1426 case RL_HWREV_8105E:
1427 case RL_HWREV_8105E_SPIN1:
1428 case RL_HWREV_8106E:
1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1430 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1431 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1432 break;
1433 case RL_HWREV_8402:
1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1435 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1436 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1437 RL_FLAG_CMDSTOP_WAIT_TXQ;
1438 break;
1439 case RL_HWREV_8168B_SPIN1:
1440 case RL_HWREV_8168B_SPIN2:
1441 sc->rl_flags |= RL_FLAG_WOLRXENB;
1442 /* FALLTHROUGH */
1443 case RL_HWREV_8168B_SPIN3:
1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1445 break;
1446 case RL_HWREV_8168C_SPIN2:
1447 sc->rl_flags |= RL_FLAG_MACSLEEP;
1448 /* FALLTHROUGH */
1449 case RL_HWREV_8168C:
1450 if (sc->rl_macrev == 0x00200000)
1451 sc->rl_flags |= RL_FLAG_MACSLEEP;
1452 /* FALLTHROUGH */
1453 case RL_HWREV_8168CP:
1454 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1455 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1456 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1457 break;
1458 case RL_HWREV_8168D:
1459 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1460 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1461 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1462 RL_FLAG_WOL_MANLINK;
1463 break;
1464 case RL_HWREV_8168DP:
1465 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1466 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1467 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1468 break;
1469 case RL_HWREV_8168E:
1470 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1471 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1472 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1473 RL_FLAG_WOL_MANLINK;
1474 break;
1475 case RL_HWREV_8168E_VL:
1476 case RL_HWREV_8168F:
1477 sc->rl_flags |= RL_FLAG_EARLYOFF;
1478 /* FALLTHROUGH */
1479 case RL_HWREV_8411:
1480 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1481 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1482 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1483 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1484 break;
1485 case RL_HWREV_8168EP:
1486 case RL_HWREV_8168G:
1487 case RL_HWREV_8411B:
1488 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1489 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1490 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1491 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
1492 RL_FLAG_8168G_PLUS;
1493 break;
1494 case RL_HWREV_8168GU:
1495 case RL_HWREV_8168H:
1496 if (pci_get_device(dev) == RT_DEVICEID_8101E) {
1497 /* RTL8106E(US), RTL8107E */
1498 sc->rl_flags |= RL_FLAG_FASTETHER;
1499 } else
1500 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1501
1502 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1503 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1504 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
1505 RL_FLAG_8168G_PLUS;
1506 break;
1507 case RL_HWREV_8169_8110SB:
1508 case RL_HWREV_8169_8110SBL:
1509 case RL_HWREV_8169_8110SC:
1510 case RL_HWREV_8169_8110SCE:
1511 sc->rl_flags |= RL_FLAG_PHYWAKE;
1512 /* FALLTHROUGH */
1513 case RL_HWREV_8169:
1514 case RL_HWREV_8169S:
1515 case RL_HWREV_8110S:
1516 sc->rl_flags |= RL_FLAG_MACRESET;
1517 break;
1518 default:
1519 break;
1520 }
1521
1522 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1523 sc->rl_cfg0 = RL_8139_CFG0;
1524 sc->rl_cfg1 = RL_8139_CFG1;
1525 sc->rl_cfg2 = 0;
1526 sc->rl_cfg3 = RL_8139_CFG3;
1527 sc->rl_cfg4 = RL_8139_CFG4;
1528 sc->rl_cfg5 = RL_8139_CFG5;
1529 } else {
1530 sc->rl_cfg0 = RL_CFG0;
1531 sc->rl_cfg1 = RL_CFG1;
1532 sc->rl_cfg2 = RL_CFG2;
1533 sc->rl_cfg3 = RL_CFG3;
1534 sc->rl_cfg4 = RL_CFG4;
1535 sc->rl_cfg5 = RL_CFG5;
1536 }
1537
1538 /* Reset the adapter. */
1539 RL_LOCK(sc);
1540 re_reset(sc);
1541 RL_UNLOCK(sc);
1542
1543 /* Enable PME. */
1544 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1545 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1546 cfg |= RL_CFG1_PME;
1547 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1548 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1549 cfg &= RL_CFG5_PME_STS;
1550 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1551 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1552
1553 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1554 /*
1555 * XXX Should have a better way to extract station
1556 * address from EEPROM.
1557 */
1558 for (i = 0; i < ETHER_ADDR_LEN; i++)
1559 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1560 } else {
1561 sc->rl_eewidth = RL_9356_ADDR_LEN;
1562 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1563 if (re_did != 0x8129)
1564 sc->rl_eewidth = RL_9346_ADDR_LEN;
1565
1566 /*
1567 * Get station address from the EEPROM.
1568 */
1569 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1570 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1571 as[i] = le16toh(as[i]);
1572 bcopy(as, eaddr, ETHER_ADDR_LEN);
1573 }
1574
1575 if (sc->rl_type == RL_8169) {
1576 /* Set RX length mask and number of descriptors. */
1577 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1578 sc->rl_txstart = RL_GTXSTART;
1579 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1580 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1581 } else {
1582 /* Set RX length mask and number of descriptors. */
1583 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1584 sc->rl_txstart = RL_TXSTART;
1585 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1586 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1587 }
1588
1589 error = re_allocmem(dev, sc);
1590 if (error)
1591 goto fail;
1592 re_add_sysctls(sc);
1593
1594 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1595 if (ifp == NULL) {
1596 device_printf(dev, "can not if_alloc()\n");
1597 error = ENOSPC;
1598 goto fail;
1599 }
1600
1601 /* Take controller out of deep sleep mode. */
1602 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1603 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1604 CSR_WRITE_1(sc, RL_GPIO,
1605 CSR_READ_1(sc, RL_GPIO) | 0x01);
1606 else
1607 CSR_WRITE_1(sc, RL_GPIO,
1608 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1609 }
1610
1611 /* Take PHY out of power down mode. */
1612 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1613 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1614 if (hw_rev->rl_rev == RL_HWREV_8401E)
1615 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1616 }
1617 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1618 re_gmii_writereg(dev, 1, 0x1f, 0);
1619 re_gmii_writereg(dev, 1, 0x0e, 0);
1620 }
1621
1622 ifp->if_softc = sc;
1623 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1624 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1625 ifp->if_ioctl = re_ioctl;
1626 ifp->if_start = re_start;
1627 /*
1628 * RTL8168/8111C generates wrong IP checksummed frame if the
1629 * packet has IP options so disable TX checksum offloading.
1630 */
1631 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1632 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1633 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
1634 ifp->if_hwassist = 0;
1635 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4;
1636 } else {
1637 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1638 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1639 }
1640 ifp->if_hwassist |= CSUM_TSO;
1641 ifp->if_capenable = ifp->if_capabilities;
1642 ifp->if_init = re_init;
1643 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1644 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1645 IFQ_SET_READY(&ifp->if_snd);
1646
1647 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1648
1649 #define RE_PHYAD_INTERNAL 0
1650
1651 /* Do MII setup. */
1652 phy = RE_PHYAD_INTERNAL;
1653 if (sc->rl_type == RL_8169)
1654 phy = 1;
1655 capmask = BMSR_DEFCAPMASK;
1656 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
1657 capmask &= ~BMSR_EXTSTAT;
1658 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1659 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1660 if (error != 0) {
1661 device_printf(dev, "attaching PHYs failed\n");
1662 goto fail;
1663 }
1664
1665 /*
1666 * Call MI attach routine.
1667 */
1668 ether_ifattach(ifp, eaddr);
1669
1670 /* VLAN capability setup */
1671 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1672 if (ifp->if_capabilities & IFCAP_HWCSUM)
1673 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1674 /* Enable WOL if PM is supported. */
1675 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1676 ifp->if_capabilities |= IFCAP_WOL;
1677 ifp->if_capenable = ifp->if_capabilities;
1678 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1679 /*
1680 * Don't enable TSO by default. It is known to generate
1681 * corrupted TCP segments(bad TCP options) under certain
1682 * circumstances.
1683 */
1684 ifp->if_hwassist &= ~CSUM_TSO;
1685 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1686 #ifdef DEVICE_POLLING
1687 ifp->if_capabilities |= IFCAP_POLLING;
1688 #endif
1689 /*
1690 * Tell the upper layer(s) we support long frames.
1691 * Must appear after the call to ether_ifattach() because
1692 * ether_ifattach() sets ifi_hdrlen to the default value.
1693 */
1694 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1695
1696 #ifdef DEV_NETMAP
1697 re_netmap_attach(sc);
1698 #endif /* DEV_NETMAP */
1699
1700 #ifdef RE_DIAG
1701 /*
1702 * Perform hardware diagnostic on the original RTL8169.
1703 * Some 32-bit cards were incorrectly wired and would
1704 * malfunction if plugged into a 64-bit slot.
1705 */
1706 if (hwrev == RL_HWREV_8169) {
1707 error = re_diag(sc);
1708 if (error) {
1709 device_printf(dev,
1710 "attach aborted due to hardware diag failure\n");
1711 ether_ifdetach(ifp);
1712 goto fail;
1713 }
1714 }
1715 #endif
1716
1717 #ifdef RE_TX_MODERATION
1718 intr_filter = 1;
1719 #endif
1720 /* Hook interrupt last to avoid having to lock softc */
1721 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1722 intr_filter == 0) {
1723 error = bus_setup_intr(dev, sc->rl_irq[0],
1724 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1725 &sc->rl_intrhand[0]);
1726 } else {
1727 error = bus_setup_intr(dev, sc->rl_irq[0],
1728 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1729 &sc->rl_intrhand[0]);
1730 }
1731 if (error) {
1732 device_printf(dev, "couldn't set up irq\n");
1733 ether_ifdetach(ifp);
1734 }
1735
1736 fail:
1737 if (error)
1738 re_detach(dev);
1739
1740 return (error);
1741 }
1742
1743 /*
1744 * Shutdown hardware and free up resources. This can be called any
1745 * time after the mutex has been initialized. It is called in both
1746 * the error case in attach and the normal detach case so it needs
1747 * to be careful about only freeing resources that have actually been
1748 * allocated.
1749 */
1750 static int
re_detach(device_t dev)1751 re_detach(device_t dev)
1752 {
1753 struct rl_softc *sc;
1754 struct ifnet *ifp;
1755 int i, rid;
1756
1757 sc = device_get_softc(dev);
1758 ifp = sc->rl_ifp;
1759 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1760
1761 /* These should only be active if attach succeeded */
1762 if (device_is_attached(dev)) {
1763 #ifdef DEVICE_POLLING
1764 if (ifp->if_capenable & IFCAP_POLLING)
1765 ether_poll_deregister(ifp);
1766 #endif
1767 RL_LOCK(sc);
1768 #if 0
1769 sc->suspended = 1;
1770 #endif
1771 re_stop(sc);
1772 RL_UNLOCK(sc);
1773 callout_drain(&sc->rl_stat_callout);
1774 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1775 /*
1776 * Force off the IFF_UP flag here, in case someone
1777 * still had a BPF descriptor attached to this
1778 * interface. If they do, ether_ifdetach() will cause
1779 * the BPF code to try and clear the promisc mode
1780 * flag, which will bubble down to re_ioctl(),
1781 * which will try to call re_init() again. This will
1782 * turn the NIC back on and restart the MII ticker,
1783 * which will panic the system when the kernel tries
1784 * to invoke the re_tick() function that isn't there
1785 * anymore.
1786 */
1787 ifp->if_flags &= ~IFF_UP;
1788 ether_ifdetach(ifp);
1789 }
1790 if (sc->rl_miibus)
1791 device_delete_child(dev, sc->rl_miibus);
1792 bus_generic_detach(dev);
1793
1794 /*
1795 * The rest is resource deallocation, so we should already be
1796 * stopped here.
1797 */
1798
1799 if (sc->rl_intrhand[0] != NULL) {
1800 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1801 sc->rl_intrhand[0] = NULL;
1802 }
1803 if (ifp != NULL) {
1804 #ifdef DEV_NETMAP
1805 netmap_detach(ifp);
1806 #endif /* DEV_NETMAP */
1807 if_free(ifp);
1808 }
1809 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1810 rid = 0;
1811 else
1812 rid = 1;
1813 if (sc->rl_irq[0] != NULL) {
1814 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1815 sc->rl_irq[0] = NULL;
1816 }
1817 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1818 pci_release_msi(dev);
1819 if (sc->rl_res_pba) {
1820 rid = PCIR_BAR(4);
1821 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1822 }
1823 if (sc->rl_res)
1824 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1825 sc->rl_res);
1826
1827 /* Unload and free the RX DMA ring memory and map */
1828
1829 if (sc->rl_ldata.rl_rx_list_tag) {
1830 if (sc->rl_ldata.rl_rx_list_addr)
1831 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1832 sc->rl_ldata.rl_rx_list_map);
1833 if (sc->rl_ldata.rl_rx_list)
1834 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1835 sc->rl_ldata.rl_rx_list,
1836 sc->rl_ldata.rl_rx_list_map);
1837 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1838 }
1839
1840 /* Unload and free the TX DMA ring memory and map */
1841
1842 if (sc->rl_ldata.rl_tx_list_tag) {
1843 if (sc->rl_ldata.rl_tx_list_addr)
1844 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1845 sc->rl_ldata.rl_tx_list_map);
1846 if (sc->rl_ldata.rl_tx_list)
1847 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1848 sc->rl_ldata.rl_tx_list,
1849 sc->rl_ldata.rl_tx_list_map);
1850 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1851 }
1852
1853 /* Destroy all the RX and TX buffer maps */
1854
1855 if (sc->rl_ldata.rl_tx_mtag) {
1856 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1857 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1858 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1859 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1860 }
1861 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1862 }
1863 if (sc->rl_ldata.rl_rx_mtag) {
1864 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1865 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1866 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1867 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1868 }
1869 if (sc->rl_ldata.rl_rx_sparemap)
1870 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1871 sc->rl_ldata.rl_rx_sparemap);
1872 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1873 }
1874 if (sc->rl_ldata.rl_jrx_mtag) {
1875 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1876 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1877 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1878 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1879 }
1880 if (sc->rl_ldata.rl_jrx_sparemap)
1881 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1882 sc->rl_ldata.rl_jrx_sparemap);
1883 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1884 }
1885 /* Unload and free the stats buffer and map */
1886
1887 if (sc->rl_ldata.rl_stag) {
1888 if (sc->rl_ldata.rl_stats_addr)
1889 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1890 sc->rl_ldata.rl_smap);
1891 if (sc->rl_ldata.rl_stats)
1892 bus_dmamem_free(sc->rl_ldata.rl_stag,
1893 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1894 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1895 }
1896
1897 if (sc->rl_parent_tag)
1898 bus_dma_tag_destroy(sc->rl_parent_tag);
1899
1900 mtx_destroy(&sc->rl_mtx);
1901
1902 return (0);
1903 }
1904
1905 static __inline void
re_discard_rxbuf(struct rl_softc * sc,int idx)1906 re_discard_rxbuf(struct rl_softc *sc, int idx)
1907 {
1908 struct rl_desc *desc;
1909 struct rl_rxdesc *rxd;
1910 uint32_t cmdstat;
1911
1912 if (sc->rl_ifp->if_mtu > RL_MTU &&
1913 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1914 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1915 else
1916 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1917 desc = &sc->rl_ldata.rl_rx_list[idx];
1918 desc->rl_vlanctl = 0;
1919 cmdstat = rxd->rx_size;
1920 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1921 cmdstat |= RL_RDESC_CMD_EOR;
1922 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1923 }
1924
1925 static int
re_newbuf(struct rl_softc * sc,int idx)1926 re_newbuf(struct rl_softc *sc, int idx)
1927 {
1928 struct mbuf *m;
1929 struct rl_rxdesc *rxd;
1930 bus_dma_segment_t segs[1];
1931 bus_dmamap_t map;
1932 struct rl_desc *desc;
1933 uint32_t cmdstat;
1934 int error, nsegs;
1935
1936 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1937 if (m == NULL)
1938 return (ENOBUFS);
1939
1940 m->m_len = m->m_pkthdr.len = MCLBYTES;
1941 #ifdef RE_FIXUP_RX
1942 /*
1943 * This is part of an evil trick to deal with non-x86 platforms.
1944 * The RealTek chip requires RX buffers to be aligned on 64-bit
1945 * boundaries, but that will hose non-x86 machines. To get around
1946 * this, we leave some empty space at the start of each buffer
1947 * and for non-x86 hosts, we copy the buffer back six bytes
1948 * to achieve word alignment. This is slightly more efficient
1949 * than allocating a new buffer, copying the contents, and
1950 * discarding the old buffer.
1951 */
1952 m_adj(m, RE_ETHER_ALIGN);
1953 #endif
1954 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1955 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1956 if (error != 0) {
1957 m_freem(m);
1958 return (ENOBUFS);
1959 }
1960 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1961
1962 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1963 if (rxd->rx_m != NULL) {
1964 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1965 BUS_DMASYNC_POSTREAD);
1966 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1967 }
1968
1969 rxd->rx_m = m;
1970 map = rxd->rx_dmamap;
1971 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1972 rxd->rx_size = segs[0].ds_len;
1973 sc->rl_ldata.rl_rx_sparemap = map;
1974 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1975 BUS_DMASYNC_PREREAD);
1976
1977 desc = &sc->rl_ldata.rl_rx_list[idx];
1978 desc->rl_vlanctl = 0;
1979 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1980 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1981 cmdstat = segs[0].ds_len;
1982 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1983 cmdstat |= RL_RDESC_CMD_EOR;
1984 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1985
1986 return (0);
1987 }
1988
1989 static int
re_jumbo_newbuf(struct rl_softc * sc,int idx)1990 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1991 {
1992 struct mbuf *m;
1993 struct rl_rxdesc *rxd;
1994 bus_dma_segment_t segs[1];
1995 bus_dmamap_t map;
1996 struct rl_desc *desc;
1997 uint32_t cmdstat;
1998 int error, nsegs;
1999
2000 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
2001 if (m == NULL)
2002 return (ENOBUFS);
2003 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
2004 #ifdef RE_FIXUP_RX
2005 m_adj(m, RE_ETHER_ALIGN);
2006 #endif
2007 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
2008 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
2009 if (error != 0) {
2010 m_freem(m);
2011 return (ENOBUFS);
2012 }
2013 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
2014
2015 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
2016 if (rxd->rx_m != NULL) {
2017 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2018 BUS_DMASYNC_POSTREAD);
2019 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
2020 }
2021
2022 rxd->rx_m = m;
2023 map = rxd->rx_dmamap;
2024 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
2025 rxd->rx_size = segs[0].ds_len;
2026 sc->rl_ldata.rl_jrx_sparemap = map;
2027 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2028 BUS_DMASYNC_PREREAD);
2029
2030 desc = &sc->rl_ldata.rl_rx_list[idx];
2031 desc->rl_vlanctl = 0;
2032 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
2033 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
2034 cmdstat = segs[0].ds_len;
2035 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
2036 cmdstat |= RL_RDESC_CMD_EOR;
2037 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2038
2039 return (0);
2040 }
2041
2042 #ifdef RE_FIXUP_RX
2043 static __inline void
re_fixup_rx(struct mbuf * m)2044 re_fixup_rx(struct mbuf *m)
2045 {
2046 int i;
2047 uint16_t *src, *dst;
2048
2049 src = mtod(m, uint16_t *);
2050 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2051
2052 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2053 *dst++ = *src++;
2054
2055 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2056 }
2057 #endif
2058
2059 static int
re_tx_list_init(struct rl_softc * sc)2060 re_tx_list_init(struct rl_softc *sc)
2061 {
2062 struct rl_desc *desc;
2063 int i;
2064
2065 RL_LOCK_ASSERT(sc);
2066
2067 bzero(sc->rl_ldata.rl_tx_list,
2068 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2070 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2071 #ifdef DEV_NETMAP
2072 re_netmap_tx_init(sc);
2073 #endif /* DEV_NETMAP */
2074 /* Set EOR. */
2075 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2076 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2077
2078 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2079 sc->rl_ldata.rl_tx_list_map,
2080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2081
2082 sc->rl_ldata.rl_tx_prodidx = 0;
2083 sc->rl_ldata.rl_tx_considx = 0;
2084 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2085
2086 return (0);
2087 }
2088
2089 static int
re_rx_list_init(struct rl_softc * sc)2090 re_rx_list_init(struct rl_softc *sc)
2091 {
2092 int error, i;
2093
2094 bzero(sc->rl_ldata.rl_rx_list,
2095 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2096 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2097 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2098 if ((error = re_newbuf(sc, i)) != 0)
2099 return (error);
2100 }
2101 #ifdef DEV_NETMAP
2102 re_netmap_rx_init(sc);
2103 #endif /* DEV_NETMAP */
2104
2105 /* Flush the RX descriptors */
2106
2107 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2108 sc->rl_ldata.rl_rx_list_map,
2109 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2110
2111 sc->rl_ldata.rl_rx_prodidx = 0;
2112 sc->rl_head = sc->rl_tail = NULL;
2113 sc->rl_int_rx_act = 0;
2114
2115 return (0);
2116 }
2117
2118 static int
re_jrx_list_init(struct rl_softc * sc)2119 re_jrx_list_init(struct rl_softc *sc)
2120 {
2121 int error, i;
2122
2123 bzero(sc->rl_ldata.rl_rx_list,
2124 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2125 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2126 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2127 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2128 return (error);
2129 }
2130
2131 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2132 sc->rl_ldata.rl_rx_list_map,
2133 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2134
2135 sc->rl_ldata.rl_rx_prodidx = 0;
2136 sc->rl_head = sc->rl_tail = NULL;
2137 sc->rl_int_rx_act = 0;
2138
2139 return (0);
2140 }
2141
2142 /*
2143 * RX handler for C+ and 8169. For the gigE chips, we support
2144 * the reception of jumbo frames that have been fragmented
2145 * across multiple 2K mbuf cluster buffers.
2146 */
2147 static int
re_rxeof(struct rl_softc * sc,int * rx_npktsp)2148 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2149 {
2150 struct mbuf *m;
2151 struct ifnet *ifp;
2152 int i, rxerr, total_len;
2153 struct rl_desc *cur_rx;
2154 u_int32_t rxstat, rxvlan;
2155 int jumbo, maxpkt = 16, rx_npkts = 0;
2156
2157 RL_LOCK_ASSERT(sc);
2158
2159 ifp = sc->rl_ifp;
2160 #ifdef DEV_NETMAP
2161 if (netmap_rx_irq(ifp, 0, &rx_npkts))
2162 return 0;
2163 #endif /* DEV_NETMAP */
2164 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2165 jumbo = 1;
2166 else
2167 jumbo = 0;
2168
2169 /* Invalidate the descriptor memory */
2170
2171 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2172 sc->rl_ldata.rl_rx_list_map,
2173 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2174
2175 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2176 i = RL_RX_DESC_NXT(sc, i)) {
2177 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2178 break;
2179 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2180 rxstat = le32toh(cur_rx->rl_cmdstat);
2181 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2182 break;
2183 total_len = rxstat & sc->rl_rxlenmask;
2184 rxvlan = le32toh(cur_rx->rl_vlanctl);
2185 if (jumbo != 0)
2186 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2187 else
2188 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2189
2190 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2191 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2192 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2193 /*
2194 * RTL8168C or later controllers do not
2195 * support multi-fragment packet.
2196 */
2197 re_discard_rxbuf(sc, i);
2198 continue;
2199 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2200 if (re_newbuf(sc, i) != 0) {
2201 /*
2202 * If this is part of a multi-fragment packet,
2203 * discard all the pieces.
2204 */
2205 if (sc->rl_head != NULL) {
2206 m_freem(sc->rl_head);
2207 sc->rl_head = sc->rl_tail = NULL;
2208 }
2209 re_discard_rxbuf(sc, i);
2210 continue;
2211 }
2212 m->m_len = RE_RX_DESC_BUFLEN;
2213 if (sc->rl_head == NULL)
2214 sc->rl_head = sc->rl_tail = m;
2215 else {
2216 m->m_flags &= ~M_PKTHDR;
2217 sc->rl_tail->m_next = m;
2218 sc->rl_tail = m;
2219 }
2220 continue;
2221 }
2222
2223 /*
2224 * NOTE: for the 8139C+, the frame length field
2225 * is always 12 bits in size, but for the gigE chips,
2226 * it is 13 bits (since the max RX frame length is 16K).
2227 * Unfortunately, all 32 bits in the status word
2228 * were already used, so to make room for the extra
2229 * length bit, RealTek took out the 'frame alignment
2230 * error' bit and shifted the other status bits
2231 * over one slot. The OWN, EOR, FS and LS bits are
2232 * still in the same places. We have already extracted
2233 * the frame length and checked the OWN bit, so rather
2234 * than using an alternate bit mapping, we shift the
2235 * status bits one space to the right so we can evaluate
2236 * them using the 8169 status as though it was in the
2237 * same format as that of the 8139C+.
2238 */
2239 if (sc->rl_type == RL_8169)
2240 rxstat >>= 1;
2241
2242 /*
2243 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2244 * set, but if CRC is clear, it will still be a valid frame.
2245 */
2246 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2247 rxerr = 1;
2248 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2249 total_len > 8191 &&
2250 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2251 rxerr = 0;
2252 if (rxerr != 0) {
2253 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2254 /*
2255 * If this is part of a multi-fragment packet,
2256 * discard all the pieces.
2257 */
2258 if (sc->rl_head != NULL) {
2259 m_freem(sc->rl_head);
2260 sc->rl_head = sc->rl_tail = NULL;
2261 }
2262 re_discard_rxbuf(sc, i);
2263 continue;
2264 }
2265 }
2266
2267 /*
2268 * If allocating a replacement mbuf fails,
2269 * reload the current one.
2270 */
2271 if (jumbo != 0)
2272 rxerr = re_jumbo_newbuf(sc, i);
2273 else
2274 rxerr = re_newbuf(sc, i);
2275 if (rxerr != 0) {
2276 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2277 if (sc->rl_head != NULL) {
2278 m_freem(sc->rl_head);
2279 sc->rl_head = sc->rl_tail = NULL;
2280 }
2281 re_discard_rxbuf(sc, i);
2282 continue;
2283 }
2284
2285 if (sc->rl_head != NULL) {
2286 if (jumbo != 0)
2287 m->m_len = total_len;
2288 else {
2289 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2290 if (m->m_len == 0)
2291 m->m_len = RE_RX_DESC_BUFLEN;
2292 }
2293 /*
2294 * Special case: if there's 4 bytes or less
2295 * in this buffer, the mbuf can be discarded:
2296 * the last 4 bytes is the CRC, which we don't
2297 * care about anyway.
2298 */
2299 if (m->m_len <= ETHER_CRC_LEN) {
2300 sc->rl_tail->m_len -=
2301 (ETHER_CRC_LEN - m->m_len);
2302 m_freem(m);
2303 } else {
2304 m->m_len -= ETHER_CRC_LEN;
2305 m->m_flags &= ~M_PKTHDR;
2306 sc->rl_tail->m_next = m;
2307 }
2308 m = sc->rl_head;
2309 sc->rl_head = sc->rl_tail = NULL;
2310 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2311 } else
2312 m->m_pkthdr.len = m->m_len =
2313 (total_len - ETHER_CRC_LEN);
2314
2315 #ifdef RE_FIXUP_RX
2316 re_fixup_rx(m);
2317 #endif
2318 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2319 m->m_pkthdr.rcvif = ifp;
2320
2321 /* Do RX checksumming if enabled */
2322
2323 if (ifp->if_capenable & IFCAP_RXCSUM) {
2324 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2325 /* Check IP header checksum */
2326 if (rxstat & RL_RDESC_STAT_PROTOID)
2327 m->m_pkthdr.csum_flags |=
2328 CSUM_IP_CHECKED;
2329 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2330 m->m_pkthdr.csum_flags |=
2331 CSUM_IP_VALID;
2332
2333 /* Check TCP/UDP checksum */
2334 if ((RL_TCPPKT(rxstat) &&
2335 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2336 (RL_UDPPKT(rxstat) &&
2337 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2338 m->m_pkthdr.csum_flags |=
2339 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2340 m->m_pkthdr.csum_data = 0xffff;
2341 }
2342 } else {
2343 /*
2344 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2345 */
2346 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2347 (rxvlan & RL_RDESC_IPV4))
2348 m->m_pkthdr.csum_flags |=
2349 CSUM_IP_CHECKED;
2350 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2351 (rxvlan & RL_RDESC_IPV4))
2352 m->m_pkthdr.csum_flags |=
2353 CSUM_IP_VALID;
2354 if (((rxstat & RL_RDESC_STAT_TCP) &&
2355 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2356 ((rxstat & RL_RDESC_STAT_UDP) &&
2357 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2358 m->m_pkthdr.csum_flags |=
2359 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2360 m->m_pkthdr.csum_data = 0xffff;
2361 }
2362 }
2363 }
2364 maxpkt--;
2365 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2366 m->m_pkthdr.ether_vtag =
2367 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2368 m->m_flags |= M_VLANTAG;
2369 }
2370 RL_UNLOCK(sc);
2371 (*ifp->if_input)(ifp, m);
2372 RL_LOCK(sc);
2373 rx_npkts++;
2374 }
2375
2376 /* Flush the RX DMA ring */
2377
2378 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2379 sc->rl_ldata.rl_rx_list_map,
2380 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2381
2382 sc->rl_ldata.rl_rx_prodidx = i;
2383
2384 if (rx_npktsp != NULL)
2385 *rx_npktsp = rx_npkts;
2386 if (maxpkt)
2387 return (EAGAIN);
2388
2389 return (0);
2390 }
2391
2392 static void
re_txeof(struct rl_softc * sc)2393 re_txeof(struct rl_softc *sc)
2394 {
2395 struct ifnet *ifp;
2396 struct rl_txdesc *txd;
2397 u_int32_t txstat;
2398 int cons;
2399
2400 cons = sc->rl_ldata.rl_tx_considx;
2401 if (cons == sc->rl_ldata.rl_tx_prodidx)
2402 return;
2403
2404 ifp = sc->rl_ifp;
2405 #ifdef DEV_NETMAP
2406 if (netmap_tx_irq(ifp, 0))
2407 return;
2408 #endif /* DEV_NETMAP */
2409 /* Invalidate the TX descriptor list */
2410 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2411 sc->rl_ldata.rl_tx_list_map,
2412 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2413
2414 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2415 cons = RL_TX_DESC_NXT(sc, cons)) {
2416 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2417 if (txstat & RL_TDESC_STAT_OWN)
2418 break;
2419 /*
2420 * We only stash mbufs in the last descriptor
2421 * in a fragment chain, which also happens to
2422 * be the only place where the TX status bits
2423 * are valid.
2424 */
2425 if (txstat & RL_TDESC_CMD_EOF) {
2426 txd = &sc->rl_ldata.rl_tx_desc[cons];
2427 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2428 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2429 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2430 txd->tx_dmamap);
2431 KASSERT(txd->tx_m != NULL,
2432 ("%s: freeing NULL mbufs!", __func__));
2433 m_freem(txd->tx_m);
2434 txd->tx_m = NULL;
2435 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2436 RL_TDESC_STAT_COLCNT))
2437 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2438 if (txstat & RL_TDESC_STAT_TXERRSUM)
2439 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2440 else
2441 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2442 }
2443 sc->rl_ldata.rl_tx_free++;
2444 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2445 }
2446 sc->rl_ldata.rl_tx_considx = cons;
2447
2448 /* No changes made to the TX ring, so no flush needed */
2449
2450 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2451 #ifdef RE_TX_MODERATION
2452 /*
2453 * If not all descriptors have been reaped yet, reload
2454 * the timer so that we will eventually get another
2455 * interrupt that will cause us to re-enter this routine.
2456 * This is done in case the transmitter has gone idle.
2457 */
2458 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2459 #endif
2460 } else
2461 sc->rl_watchdog_timer = 0;
2462 }
2463
2464 static void
re_tick(void * xsc)2465 re_tick(void *xsc)
2466 {
2467 struct rl_softc *sc;
2468 struct mii_data *mii;
2469
2470 sc = xsc;
2471
2472 RL_LOCK_ASSERT(sc);
2473
2474 mii = device_get_softc(sc->rl_miibus);
2475 mii_tick(mii);
2476 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2477 re_miibus_statchg(sc->rl_dev);
2478 /*
2479 * Reclaim transmitted frames here. Technically it is not
2480 * necessary to do here but it ensures periodic reclamation
2481 * regardless of Tx completion interrupt which seems to be
2482 * lost on PCIe based controllers under certain situations.
2483 */
2484 re_txeof(sc);
2485 re_watchdog(sc);
2486 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2487 }
2488
2489 #ifdef DEVICE_POLLING
2490 static int
re_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)2491 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2492 {
2493 struct rl_softc *sc = ifp->if_softc;
2494 int rx_npkts = 0;
2495
2496 RL_LOCK(sc);
2497 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2498 rx_npkts = re_poll_locked(ifp, cmd, count);
2499 RL_UNLOCK(sc);
2500 return (rx_npkts);
2501 }
2502
2503 static int
re_poll_locked(struct ifnet * ifp,enum poll_cmd cmd,int count)2504 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2505 {
2506 struct rl_softc *sc = ifp->if_softc;
2507 int rx_npkts;
2508
2509 RL_LOCK_ASSERT(sc);
2510
2511 sc->rxcycles = count;
2512 re_rxeof(sc, &rx_npkts);
2513 re_txeof(sc);
2514
2515 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2516 re_start_locked(ifp);
2517
2518 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2519 u_int16_t status;
2520
2521 status = CSR_READ_2(sc, RL_ISR);
2522 if (status == 0xffff)
2523 return (rx_npkts);
2524 if (status)
2525 CSR_WRITE_2(sc, RL_ISR, status);
2526 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2527 (sc->rl_flags & RL_FLAG_PCIE))
2528 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2529
2530 /*
2531 * XXX check behaviour on receiver stalls.
2532 */
2533
2534 if (status & RL_ISR_SYSTEM_ERR) {
2535 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2536 re_init_locked(sc);
2537 }
2538 }
2539 return (rx_npkts);
2540 }
2541 #endif /* DEVICE_POLLING */
2542
2543 static int
re_intr(void * arg)2544 re_intr(void *arg)
2545 {
2546 struct rl_softc *sc;
2547 uint16_t status;
2548
2549 sc = arg;
2550
2551 status = CSR_READ_2(sc, RL_ISR);
2552 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2553 return (FILTER_STRAY);
2554 CSR_WRITE_2(sc, RL_IMR, 0);
2555
2556 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2557
2558 return (FILTER_HANDLED);
2559 }
2560
2561 static void
re_int_task(void * arg,int npending)2562 re_int_task(void *arg, int npending)
2563 {
2564 struct rl_softc *sc;
2565 struct ifnet *ifp;
2566 u_int16_t status;
2567 int rval = 0;
2568
2569 sc = arg;
2570 ifp = sc->rl_ifp;
2571
2572 RL_LOCK(sc);
2573
2574 status = CSR_READ_2(sc, RL_ISR);
2575 CSR_WRITE_2(sc, RL_ISR, status);
2576
2577 if (sc->suspended ||
2578 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2579 RL_UNLOCK(sc);
2580 return;
2581 }
2582
2583 #ifdef DEVICE_POLLING
2584 if (ifp->if_capenable & IFCAP_POLLING) {
2585 RL_UNLOCK(sc);
2586 return;
2587 }
2588 #endif
2589
2590 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2591 rval = re_rxeof(sc, NULL);
2592
2593 /*
2594 * Some chips will ignore a second TX request issued
2595 * while an existing transmission is in progress. If
2596 * the transmitter goes idle but there are still
2597 * packets waiting to be sent, we need to restart the
2598 * channel here to flush them out. This only seems to
2599 * be required with the PCIe devices.
2600 */
2601 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2602 (sc->rl_flags & RL_FLAG_PCIE))
2603 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2604 if (status & (
2605 #ifdef RE_TX_MODERATION
2606 RL_ISR_TIMEOUT_EXPIRED|
2607 #else
2608 RL_ISR_TX_OK|
2609 #endif
2610 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2611 re_txeof(sc);
2612
2613 if (status & RL_ISR_SYSTEM_ERR) {
2614 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2615 re_init_locked(sc);
2616 }
2617
2618 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2619 re_start_locked(ifp);
2620
2621 RL_UNLOCK(sc);
2622
2623 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2624 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2625 return;
2626 }
2627
2628 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2629 }
2630
2631 static void
re_intr_msi(void * xsc)2632 re_intr_msi(void *xsc)
2633 {
2634 struct rl_softc *sc;
2635 struct ifnet *ifp;
2636 uint16_t intrs, status;
2637
2638 sc = xsc;
2639 RL_LOCK(sc);
2640
2641 ifp = sc->rl_ifp;
2642 #ifdef DEVICE_POLLING
2643 if (ifp->if_capenable & IFCAP_POLLING) {
2644 RL_UNLOCK(sc);
2645 return;
2646 }
2647 #endif
2648 /* Disable interrupts. */
2649 CSR_WRITE_2(sc, RL_IMR, 0);
2650 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2651 RL_UNLOCK(sc);
2652 return;
2653 }
2654
2655 intrs = RL_INTRS_CPLUS;
2656 status = CSR_READ_2(sc, RL_ISR);
2657 CSR_WRITE_2(sc, RL_ISR, status);
2658 if (sc->rl_int_rx_act > 0) {
2659 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2660 RL_ISR_RX_OVERRUN);
2661 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2662 RL_ISR_RX_OVERRUN);
2663 }
2664
2665 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2666 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2667 re_rxeof(sc, NULL);
2668 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2669 if (sc->rl_int_rx_mod != 0 &&
2670 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2671 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2672 /* Rearm one-shot timer. */
2673 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2674 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2675 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2676 sc->rl_int_rx_act = 1;
2677 } else {
2678 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2679 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2680 sc->rl_int_rx_act = 0;
2681 }
2682 }
2683 }
2684
2685 /*
2686 * Some chips will ignore a second TX request issued
2687 * while an existing transmission is in progress. If
2688 * the transmitter goes idle but there are still
2689 * packets waiting to be sent, we need to restart the
2690 * channel here to flush them out. This only seems to
2691 * be required with the PCIe devices.
2692 */
2693 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2694 (sc->rl_flags & RL_FLAG_PCIE))
2695 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2696 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2697 re_txeof(sc);
2698
2699 if (status & RL_ISR_SYSTEM_ERR) {
2700 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2701 re_init_locked(sc);
2702 }
2703
2704 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2705 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2706 re_start_locked(ifp);
2707 CSR_WRITE_2(sc, RL_IMR, intrs);
2708 }
2709 RL_UNLOCK(sc);
2710 }
2711
2712 static int
re_encap(struct rl_softc * sc,struct mbuf ** m_head)2713 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2714 {
2715 struct rl_txdesc *txd, *txd_last;
2716 bus_dma_segment_t segs[RL_NTXSEGS];
2717 bus_dmamap_t map;
2718 struct mbuf *m_new;
2719 struct rl_desc *desc;
2720 int nsegs, prod;
2721 int i, error, ei, si;
2722 int padlen;
2723 uint32_t cmdstat, csum_flags, vlanctl;
2724
2725 RL_LOCK_ASSERT(sc);
2726 M_ASSERTPKTHDR((*m_head));
2727
2728 /*
2729 * With some of the RealTek chips, using the checksum offload
2730 * support in conjunction with the autopadding feature results
2731 * in the transmission of corrupt frames. For example, if we
2732 * need to send a really small IP fragment that's less than 60
2733 * bytes in size, and IP header checksumming is enabled, the
2734 * resulting ethernet frame that appears on the wire will
2735 * have garbled payload. To work around this, if TX IP checksum
2736 * offload is enabled, we always manually pad short frames out
2737 * to the minimum ethernet frame size.
2738 */
2739 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2740 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2741 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2742 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2743 if (M_WRITABLE(*m_head) == 0) {
2744 /* Get a writable copy. */
2745 m_new = m_dup(*m_head, M_NOWAIT);
2746 m_freem(*m_head);
2747 if (m_new == NULL) {
2748 *m_head = NULL;
2749 return (ENOBUFS);
2750 }
2751 *m_head = m_new;
2752 }
2753 if ((*m_head)->m_next != NULL ||
2754 M_TRAILINGSPACE(*m_head) < padlen) {
2755 m_new = m_defrag(*m_head, M_NOWAIT);
2756 if (m_new == NULL) {
2757 m_freem(*m_head);
2758 *m_head = NULL;
2759 return (ENOBUFS);
2760 }
2761 } else
2762 m_new = *m_head;
2763
2764 /*
2765 * Manually pad short frames, and zero the pad space
2766 * to avoid leaking data.
2767 */
2768 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2769 m_new->m_pkthdr.len += padlen;
2770 m_new->m_len = m_new->m_pkthdr.len;
2771 *m_head = m_new;
2772 }
2773
2774 prod = sc->rl_ldata.rl_tx_prodidx;
2775 txd = &sc->rl_ldata.rl_tx_desc[prod];
2776 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2777 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2778 if (error == EFBIG) {
2779 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2780 if (m_new == NULL) {
2781 m_freem(*m_head);
2782 *m_head = NULL;
2783 return (ENOBUFS);
2784 }
2785 *m_head = m_new;
2786 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2787 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2788 if (error != 0) {
2789 m_freem(*m_head);
2790 *m_head = NULL;
2791 return (error);
2792 }
2793 } else if (error != 0)
2794 return (error);
2795 if (nsegs == 0) {
2796 m_freem(*m_head);
2797 *m_head = NULL;
2798 return (EIO);
2799 }
2800
2801 /* Check for number of available descriptors. */
2802 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2803 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2804 return (ENOBUFS);
2805 }
2806
2807 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2808 BUS_DMASYNC_PREWRITE);
2809
2810 /*
2811 * Set up checksum offload. Note: checksum offload bits must
2812 * appear in all descriptors of a multi-descriptor transmit
2813 * attempt. This is according to testing done with an 8169
2814 * chip. This is a requirement.
2815 */
2816 vlanctl = 0;
2817 csum_flags = 0;
2818 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2819 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2820 csum_flags |= RL_TDESC_CMD_LGSEND;
2821 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2822 RL_TDESC_CMD_MSSVALV2_SHIFT);
2823 } else {
2824 csum_flags |= RL_TDESC_CMD_LGSEND |
2825 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2826 RL_TDESC_CMD_MSSVAL_SHIFT);
2827 }
2828 } else {
2829 /*
2830 * Unconditionally enable IP checksum if TCP or UDP
2831 * checksum is required. Otherwise, TCP/UDP checksum
2832 * doesn't make effects.
2833 */
2834 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2835 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2836 csum_flags |= RL_TDESC_CMD_IPCSUM;
2837 if (((*m_head)->m_pkthdr.csum_flags &
2838 CSUM_TCP) != 0)
2839 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2840 if (((*m_head)->m_pkthdr.csum_flags &
2841 CSUM_UDP) != 0)
2842 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2843 } else {
2844 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2845 if (((*m_head)->m_pkthdr.csum_flags &
2846 CSUM_TCP) != 0)
2847 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2848 if (((*m_head)->m_pkthdr.csum_flags &
2849 CSUM_UDP) != 0)
2850 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2851 }
2852 }
2853 }
2854
2855 /*
2856 * Set up hardware VLAN tagging. Note: vlan tag info must
2857 * appear in all descriptors of a multi-descriptor
2858 * transmission attempt.
2859 */
2860 if ((*m_head)->m_flags & M_VLANTAG)
2861 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2862 RL_TDESC_VLANCTL_TAG;
2863
2864 si = prod;
2865 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2866 desc = &sc->rl_ldata.rl_tx_list[prod];
2867 desc->rl_vlanctl = htole32(vlanctl);
2868 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2869 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2870 cmdstat = segs[i].ds_len;
2871 if (i != 0)
2872 cmdstat |= RL_TDESC_CMD_OWN;
2873 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2874 cmdstat |= RL_TDESC_CMD_EOR;
2875 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2876 sc->rl_ldata.rl_tx_free--;
2877 }
2878 /* Update producer index. */
2879 sc->rl_ldata.rl_tx_prodidx = prod;
2880
2881 /* Set EOF on the last descriptor. */
2882 ei = RL_TX_DESC_PRV(sc, prod);
2883 desc = &sc->rl_ldata.rl_tx_list[ei];
2884 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2885
2886 desc = &sc->rl_ldata.rl_tx_list[si];
2887 /* Set SOF and transfer ownership of packet to the chip. */
2888 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2889
2890 /*
2891 * Insure that the map for this transmission
2892 * is placed at the array index of the last descriptor
2893 * in this chain. (Swap last and first dmamaps.)
2894 */
2895 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2896 map = txd->tx_dmamap;
2897 txd->tx_dmamap = txd_last->tx_dmamap;
2898 txd_last->tx_dmamap = map;
2899 txd_last->tx_m = *m_head;
2900
2901 return (0);
2902 }
2903
2904 static void
re_start(struct ifnet * ifp)2905 re_start(struct ifnet *ifp)
2906 {
2907 struct rl_softc *sc;
2908
2909 sc = ifp->if_softc;
2910 RL_LOCK(sc);
2911 re_start_locked(ifp);
2912 RL_UNLOCK(sc);
2913 }
2914
2915 /*
2916 * Main transmit routine for C+ and gigE NICs.
2917 */
2918 static void
re_start_locked(struct ifnet * ifp)2919 re_start_locked(struct ifnet *ifp)
2920 {
2921 struct rl_softc *sc;
2922 struct mbuf *m_head;
2923 int queued;
2924
2925 sc = ifp->if_softc;
2926
2927 #ifdef DEV_NETMAP
2928 /* XXX is this necessary ? */
2929 if (ifp->if_capenable & IFCAP_NETMAP) {
2930 struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2931 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2932 /* kick the tx unit */
2933 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2934 #ifdef RE_TX_MODERATION
2935 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2936 #endif
2937 sc->rl_watchdog_timer = 5;
2938 }
2939 return;
2940 }
2941 #endif /* DEV_NETMAP */
2942
2943 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2944 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2945 return;
2946
2947 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2948 sc->rl_ldata.rl_tx_free > 1;) {
2949 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2950 if (m_head == NULL)
2951 break;
2952
2953 if (re_encap(sc, &m_head) != 0) {
2954 if (m_head == NULL)
2955 break;
2956 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2957 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2958 break;
2959 }
2960
2961 /*
2962 * If there's a BPF listener, bounce a copy of this frame
2963 * to him.
2964 */
2965 ETHER_BPF_MTAP(ifp, m_head);
2966
2967 queued++;
2968 }
2969
2970 if (queued == 0) {
2971 #ifdef RE_TX_MODERATION
2972 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2973 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2974 #endif
2975 return;
2976 }
2977
2978 /* Flush the TX descriptors */
2979
2980 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2981 sc->rl_ldata.rl_tx_list_map,
2982 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2983
2984 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2985
2986 #ifdef RE_TX_MODERATION
2987 /*
2988 * Use the countdown timer for interrupt moderation.
2989 * 'TX done' interrupts are disabled. Instead, we reset the
2990 * countdown timer, which will begin counting until it hits
2991 * the value in the TIMERINT register, and then trigger an
2992 * interrupt. Each time we write to the TIMERCNT register,
2993 * the timer count is reset to 0.
2994 */
2995 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2996 #endif
2997
2998 /*
2999 * Set a timeout in case the chip goes out to lunch.
3000 */
3001 sc->rl_watchdog_timer = 5;
3002 }
3003
3004 static void
re_set_jumbo(struct rl_softc * sc,int jumbo)3005 re_set_jumbo(struct rl_softc *sc, int jumbo)
3006 {
3007
3008 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
3009 pci_set_max_read_req(sc->rl_dev, 4096);
3010 return;
3011 }
3012
3013 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3014 if (jumbo != 0) {
3015 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
3016 RL_CFG3_JUMBO_EN0);
3017 switch (sc->rl_hwrev->rl_rev) {
3018 case RL_HWREV_8168DP:
3019 break;
3020 case RL_HWREV_8168E:
3021 CSR_WRITE_1(sc, sc->rl_cfg4,
3022 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
3023 break;
3024 default:
3025 CSR_WRITE_1(sc, sc->rl_cfg4,
3026 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
3027 }
3028 } else {
3029 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
3030 ~RL_CFG3_JUMBO_EN0);
3031 switch (sc->rl_hwrev->rl_rev) {
3032 case RL_HWREV_8168DP:
3033 break;
3034 case RL_HWREV_8168E:
3035 CSR_WRITE_1(sc, sc->rl_cfg4,
3036 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
3037 break;
3038 default:
3039 CSR_WRITE_1(sc, sc->rl_cfg4,
3040 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3041 }
3042 }
3043 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3044
3045 switch (sc->rl_hwrev->rl_rev) {
3046 case RL_HWREV_8168DP:
3047 pci_set_max_read_req(sc->rl_dev, 4096);
3048 break;
3049 default:
3050 if (jumbo != 0)
3051 pci_set_max_read_req(sc->rl_dev, 512);
3052 else
3053 pci_set_max_read_req(sc->rl_dev, 4096);
3054 }
3055 }
3056
3057 static void
re_init(void * xsc)3058 re_init(void *xsc)
3059 {
3060 struct rl_softc *sc = xsc;
3061
3062 RL_LOCK(sc);
3063 re_init_locked(sc);
3064 RL_UNLOCK(sc);
3065 }
3066
3067 static void
re_init_locked(struct rl_softc * sc)3068 re_init_locked(struct rl_softc *sc)
3069 {
3070 struct ifnet *ifp = sc->rl_ifp;
3071 struct mii_data *mii;
3072 uint32_t reg;
3073 uint16_t cfg;
3074 union {
3075 uint32_t align_dummy;
3076 u_char eaddr[ETHER_ADDR_LEN];
3077 } eaddr;
3078
3079 RL_LOCK_ASSERT(sc);
3080
3081 mii = device_get_softc(sc->rl_miibus);
3082
3083 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3084 return;
3085
3086 /*
3087 * Cancel pending I/O and free all RX/TX buffers.
3088 */
3089 re_stop(sc);
3090
3091 /* Put controller into known state. */
3092 re_reset(sc);
3093
3094 /*
3095 * For C+ mode, initialize the RX descriptors and mbufs.
3096 */
3097 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3098 if (ifp->if_mtu > RL_MTU) {
3099 if (re_jrx_list_init(sc) != 0) {
3100 device_printf(sc->rl_dev,
3101 "no memory for jumbo RX buffers\n");
3102 re_stop(sc);
3103 return;
3104 }
3105 /* Disable checksum offloading for jumbo frames. */
3106 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3107 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3108 } else {
3109 if (re_rx_list_init(sc) != 0) {
3110 device_printf(sc->rl_dev,
3111 "no memory for RX buffers\n");
3112 re_stop(sc);
3113 return;
3114 }
3115 }
3116 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3117 } else {
3118 if (re_rx_list_init(sc) != 0) {
3119 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3120 re_stop(sc);
3121 return;
3122 }
3123 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3124 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3125 if (ifp->if_mtu > RL_MTU)
3126 pci_set_max_read_req(sc->rl_dev, 512);
3127 else
3128 pci_set_max_read_req(sc->rl_dev, 4096);
3129 }
3130 }
3131 re_tx_list_init(sc);
3132
3133 /*
3134 * Enable C+ RX and TX mode, as well as VLAN stripping and
3135 * RX checksum offload. We must configure the C+ register
3136 * before all others.
3137 */
3138 cfg = RL_CPLUSCMD_PCI_MRW;
3139 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3140 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3141 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3142 cfg |= RL_CPLUSCMD_VLANSTRIP;
3143 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3144 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3145 /* XXX magic. */
3146 cfg |= 0x0001;
3147 } else
3148 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3149 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3150 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3151 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3152 reg = 0x000fff00;
3153 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3154 reg |= 0x000000ff;
3155 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3156 reg |= 0x00f00000;
3157 CSR_WRITE_4(sc, 0x7c, reg);
3158 /* Disable interrupt mitigation. */
3159 CSR_WRITE_2(sc, 0xe2, 0);
3160 }
3161 /*
3162 * Disable TSO if interface MTU size is greater than MSS
3163 * allowed in controller.
3164 */
3165 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3166 ifp->if_capenable &= ~IFCAP_TSO4;
3167 ifp->if_hwassist &= ~CSUM_TSO;
3168 }
3169
3170 /*
3171 * Init our MAC address. Even though the chipset
3172 * documentation doesn't mention it, we need to enter "Config
3173 * register write enable" mode to modify the ID registers.
3174 */
3175 /* Copy MAC address on stack to align. */
3176 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3177 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3178 CSR_WRITE_4(sc, RL_IDR0,
3179 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3180 CSR_WRITE_4(sc, RL_IDR4,
3181 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3182 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3183
3184 /*
3185 * Load the addresses of the RX and TX lists into the chip.
3186 */
3187
3188 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3189 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3190 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3191 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3192
3193 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3194 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3195 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3196 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3197
3198 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3199 /* Disable RXDV gate. */
3200 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3201 ~0x00080000);
3202 }
3203
3204 /*
3205 * Enable transmit and receive for pre-RTL8168G controllers.
3206 * RX/TX MACs should be enabled before RX/TX configuration.
3207 */
3208 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0)
3209 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3210
3211 /*
3212 * Set the initial TX configuration.
3213 */
3214 if (sc->rl_testmode) {
3215 if (sc->rl_type == RL_8169)
3216 CSR_WRITE_4(sc, RL_TXCFG,
3217 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3218 else
3219 CSR_WRITE_4(sc, RL_TXCFG,
3220 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3221 } else
3222 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3223
3224 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3225
3226 /*
3227 * Set the initial RX configuration.
3228 */
3229 re_set_rxmode(sc);
3230
3231 /* Configure interrupt moderation. */
3232 if (sc->rl_type == RL_8169) {
3233 /* Magic from vendor. */
3234 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3235 }
3236
3237 /*
3238 * Enable transmit and receive for RTL8168G and later controllers.
3239 * RX/TX MACs should be enabled after RX/TX configuration.
3240 */
3241 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
3242 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3243
3244 #ifdef DEVICE_POLLING
3245 /*
3246 * Disable interrupts if we are polling.
3247 */
3248 if (ifp->if_capenable & IFCAP_POLLING)
3249 CSR_WRITE_2(sc, RL_IMR, 0);
3250 else /* otherwise ... */
3251 #endif
3252
3253 /*
3254 * Enable interrupts.
3255 */
3256 if (sc->rl_testmode)
3257 CSR_WRITE_2(sc, RL_IMR, 0);
3258 else
3259 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3260 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3261
3262 /* Set initial TX threshold */
3263 sc->rl_txthresh = RL_TX_THRESH_INIT;
3264
3265 /* Start RX/TX process. */
3266 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3267
3268 /*
3269 * Initialize the timer interrupt register so that
3270 * a timer interrupt will be generated once the timer
3271 * reaches a certain number of ticks. The timer is
3272 * reloaded on each transmit.
3273 */
3274 #ifdef RE_TX_MODERATION
3275 /*
3276 * Use timer interrupt register to moderate TX interrupt
3277 * moderation, which dramatically improves TX frame rate.
3278 */
3279 if (sc->rl_type == RL_8169)
3280 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3281 else
3282 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3283 #else
3284 /*
3285 * Use timer interrupt register to moderate RX interrupt
3286 * moderation.
3287 */
3288 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3289 intr_filter == 0) {
3290 if (sc->rl_type == RL_8169)
3291 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3292 RL_USECS(sc->rl_int_rx_mod));
3293 } else {
3294 if (sc->rl_type == RL_8169)
3295 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3296 }
3297 #endif
3298
3299 /*
3300 * For 8169 gigE NICs, set the max allowed RX packet
3301 * size so we can receive jumbo frames.
3302 */
3303 if (sc->rl_type == RL_8169) {
3304 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3305 /*
3306 * For controllers that use new jumbo frame scheme,
3307 * set maximum size of jumbo frame depending on
3308 * controller revisions.
3309 */
3310 if (ifp->if_mtu > RL_MTU)
3311 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3312 sc->rl_hwrev->rl_max_mtu +
3313 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3314 ETHER_CRC_LEN);
3315 else
3316 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3317 RE_RX_DESC_BUFLEN);
3318 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3319 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3320 /* RTL810x has no jumbo frame support. */
3321 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3322 } else
3323 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3324 }
3325
3326 if (sc->rl_testmode)
3327 return;
3328
3329 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3330 RL_CFG1_DRVLOAD);
3331
3332 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3333 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3334
3335 sc->rl_flags &= ~RL_FLAG_LINK;
3336 mii_mediachg(mii);
3337
3338 sc->rl_watchdog_timer = 0;
3339 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3340 }
3341
3342 /*
3343 * Set media options.
3344 */
3345 static int
re_ifmedia_upd(struct ifnet * ifp)3346 re_ifmedia_upd(struct ifnet *ifp)
3347 {
3348 struct rl_softc *sc;
3349 struct mii_data *mii;
3350 int error;
3351
3352 sc = ifp->if_softc;
3353 mii = device_get_softc(sc->rl_miibus);
3354 RL_LOCK(sc);
3355 error = mii_mediachg(mii);
3356 RL_UNLOCK(sc);
3357
3358 return (error);
3359 }
3360
3361 /*
3362 * Report current media status.
3363 */
3364 static void
re_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)3365 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3366 {
3367 struct rl_softc *sc;
3368 struct mii_data *mii;
3369
3370 sc = ifp->if_softc;
3371 mii = device_get_softc(sc->rl_miibus);
3372
3373 RL_LOCK(sc);
3374 mii_pollstat(mii);
3375 ifmr->ifm_active = mii->mii_media_active;
3376 ifmr->ifm_status = mii->mii_media_status;
3377 RL_UNLOCK(sc);
3378 }
3379
3380 static int
re_ioctl(struct ifnet * ifp,u_long command,caddr_t data)3381 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3382 {
3383 struct rl_softc *sc = ifp->if_softc;
3384 struct ifreq *ifr = (struct ifreq *) data;
3385 struct mii_data *mii;
3386 int error = 0;
3387
3388 switch (command) {
3389 case SIOCSIFMTU:
3390 if (ifr->ifr_mtu < ETHERMIN ||
3391 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
3392 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
3393 ifr->ifr_mtu > RL_MTU)) {
3394 error = EINVAL;
3395 break;
3396 }
3397 RL_LOCK(sc);
3398 if (ifp->if_mtu != ifr->ifr_mtu) {
3399 ifp->if_mtu = ifr->ifr_mtu;
3400 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3401 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3402 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3403 re_init_locked(sc);
3404 }
3405 if (ifp->if_mtu > RL_TSO_MTU &&
3406 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3407 ifp->if_capenable &= ~(IFCAP_TSO4 |
3408 IFCAP_VLAN_HWTSO);
3409 ifp->if_hwassist &= ~CSUM_TSO;
3410 }
3411 VLAN_CAPABILITIES(ifp);
3412 }
3413 RL_UNLOCK(sc);
3414 break;
3415 case SIOCSIFFLAGS:
3416 RL_LOCK(sc);
3417 if ((ifp->if_flags & IFF_UP) != 0) {
3418 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3419 if (((ifp->if_flags ^ sc->rl_if_flags)
3420 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3421 re_set_rxmode(sc);
3422 } else
3423 re_init_locked(sc);
3424 } else {
3425 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3426 re_stop(sc);
3427 }
3428 sc->rl_if_flags = ifp->if_flags;
3429 RL_UNLOCK(sc);
3430 break;
3431 case SIOCADDMULTI:
3432 case SIOCDELMULTI:
3433 RL_LOCK(sc);
3434 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3435 re_set_rxmode(sc);
3436 RL_UNLOCK(sc);
3437 break;
3438 case SIOCGIFMEDIA:
3439 case SIOCSIFMEDIA:
3440 mii = device_get_softc(sc->rl_miibus);
3441 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3442 break;
3443 case SIOCSIFCAP:
3444 {
3445 int mask, reinit;
3446
3447 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3448 reinit = 0;
3449 #ifdef DEVICE_POLLING
3450 if (mask & IFCAP_POLLING) {
3451 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3452 error = ether_poll_register(re_poll, ifp);
3453 if (error)
3454 return (error);
3455 RL_LOCK(sc);
3456 /* Disable interrupts */
3457 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3458 ifp->if_capenable |= IFCAP_POLLING;
3459 RL_UNLOCK(sc);
3460 } else {
3461 error = ether_poll_deregister(ifp);
3462 /* Enable interrupts. */
3463 RL_LOCK(sc);
3464 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3465 ifp->if_capenable &= ~IFCAP_POLLING;
3466 RL_UNLOCK(sc);
3467 }
3468 }
3469 #endif /* DEVICE_POLLING */
3470 RL_LOCK(sc);
3471 if ((mask & IFCAP_TXCSUM) != 0 &&
3472 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3473 ifp->if_capenable ^= IFCAP_TXCSUM;
3474 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3475 ifp->if_hwassist |= RE_CSUM_FEATURES;
3476 else
3477 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3478 reinit = 1;
3479 }
3480 if ((mask & IFCAP_RXCSUM) != 0 &&
3481 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3482 ifp->if_capenable ^= IFCAP_RXCSUM;
3483 reinit = 1;
3484 }
3485 if ((mask & IFCAP_TSO4) != 0 &&
3486 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3487 ifp->if_capenable ^= IFCAP_TSO4;
3488 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3489 ifp->if_hwassist |= CSUM_TSO;
3490 else
3491 ifp->if_hwassist &= ~CSUM_TSO;
3492 if (ifp->if_mtu > RL_TSO_MTU &&
3493 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3494 ifp->if_capenable &= ~IFCAP_TSO4;
3495 ifp->if_hwassist &= ~CSUM_TSO;
3496 }
3497 }
3498 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3499 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3500 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3501 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3502 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3503 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3504 /* TSO over VLAN requires VLAN hardware tagging. */
3505 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3506 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3507 reinit = 1;
3508 }
3509 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3510 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3511 IFCAP_VLAN_HWTSO)) != 0)
3512 reinit = 1;
3513 if ((mask & IFCAP_WOL) != 0 &&
3514 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3515 if ((mask & IFCAP_WOL_UCAST) != 0)
3516 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3517 if ((mask & IFCAP_WOL_MCAST) != 0)
3518 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3519 if ((mask & IFCAP_WOL_MAGIC) != 0)
3520 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3521 }
3522 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3523 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3524 re_init_locked(sc);
3525 }
3526 RL_UNLOCK(sc);
3527 VLAN_CAPABILITIES(ifp);
3528 }
3529 break;
3530 default:
3531 error = ether_ioctl(ifp, command, data);
3532 break;
3533 }
3534
3535 return (error);
3536 }
3537
3538 static void
re_watchdog(struct rl_softc * sc)3539 re_watchdog(struct rl_softc *sc)
3540 {
3541 struct ifnet *ifp;
3542
3543 RL_LOCK_ASSERT(sc);
3544
3545 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3546 return;
3547
3548 ifp = sc->rl_ifp;
3549 re_txeof(sc);
3550 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3551 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3552 "-- recovering\n");
3553 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3554 re_start_locked(ifp);
3555 return;
3556 }
3557
3558 if_printf(ifp, "watchdog timeout\n");
3559 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3560
3561 re_rxeof(sc, NULL);
3562 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3563 re_init_locked(sc);
3564 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3565 re_start_locked(ifp);
3566 }
3567
3568 /*
3569 * Stop the adapter and free any mbufs allocated to the
3570 * RX and TX lists.
3571 */
3572 static void
re_stop(struct rl_softc * sc)3573 re_stop(struct rl_softc *sc)
3574 {
3575 int i;
3576 struct ifnet *ifp;
3577 struct rl_txdesc *txd;
3578 struct rl_rxdesc *rxd;
3579
3580 RL_LOCK_ASSERT(sc);
3581
3582 ifp = sc->rl_ifp;
3583
3584 sc->rl_watchdog_timer = 0;
3585 callout_stop(&sc->rl_stat_callout);
3586 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3587
3588 /*
3589 * Disable accepting frames to put RX MAC into idle state.
3590 * Otherwise it's possible to get frames while stop command
3591 * execution is in progress and controller can DMA the frame
3592 * to already freed RX buffer during that period.
3593 */
3594 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3595 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3596 RL_RXCFG_RX_BROAD));
3597
3598 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3599 /* Enable RXDV gate. */
3600 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) |
3601 0x00080000);
3602 }
3603
3604 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3605 for (i = RL_TIMEOUT; i > 0; i--) {
3606 if ((CSR_READ_1(sc, sc->rl_txstart) &
3607 RL_TXSTART_START) == 0)
3608 break;
3609 DELAY(20);
3610 }
3611 if (i == 0)
3612 device_printf(sc->rl_dev,
3613 "stopping TX poll timed out!\n");
3614 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3615 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3616 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3617 RL_CMD_RX_ENB);
3618 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3619 for (i = RL_TIMEOUT; i > 0; i--) {
3620 if ((CSR_READ_4(sc, RL_TXCFG) &
3621 RL_TXCFG_QUEUE_EMPTY) != 0)
3622 break;
3623 DELAY(100);
3624 }
3625 if (i == 0)
3626 device_printf(sc->rl_dev,
3627 "stopping TXQ timed out!\n");
3628 }
3629 } else
3630 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3631 DELAY(1000);
3632 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3633 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3634
3635 if (sc->rl_head != NULL) {
3636 m_freem(sc->rl_head);
3637 sc->rl_head = sc->rl_tail = NULL;
3638 }
3639
3640 /* Free the TX list buffers. */
3641 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3642 txd = &sc->rl_ldata.rl_tx_desc[i];
3643 if (txd->tx_m != NULL) {
3644 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3645 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3646 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3647 txd->tx_dmamap);
3648 m_freem(txd->tx_m);
3649 txd->tx_m = NULL;
3650 }
3651 }
3652
3653 /* Free the RX list buffers. */
3654 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3655 rxd = &sc->rl_ldata.rl_rx_desc[i];
3656 if (rxd->rx_m != NULL) {
3657 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3658 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3659 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3660 rxd->rx_dmamap);
3661 m_freem(rxd->rx_m);
3662 rxd->rx_m = NULL;
3663 }
3664 }
3665
3666 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3667 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3668 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3669 if (rxd->rx_m != NULL) {
3670 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3671 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3672 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3673 rxd->rx_dmamap);
3674 m_freem(rxd->rx_m);
3675 rxd->rx_m = NULL;
3676 }
3677 }
3678 }
3679 }
3680
3681 /*
3682 * Device suspend routine. Stop the interface and save some PCI
3683 * settings in case the BIOS doesn't restore them properly on
3684 * resume.
3685 */
3686 static int
re_suspend(device_t dev)3687 re_suspend(device_t dev)
3688 {
3689 struct rl_softc *sc;
3690
3691 sc = device_get_softc(dev);
3692
3693 RL_LOCK(sc);
3694 re_stop(sc);
3695 re_setwol(sc);
3696 sc->suspended = 1;
3697 RL_UNLOCK(sc);
3698
3699 return (0);
3700 }
3701
3702 /*
3703 * Device resume routine. Restore some PCI settings in case the BIOS
3704 * doesn't, re-enable busmastering, and restart the interface if
3705 * appropriate.
3706 */
3707 static int
re_resume(device_t dev)3708 re_resume(device_t dev)
3709 {
3710 struct rl_softc *sc;
3711 struct ifnet *ifp;
3712
3713 sc = device_get_softc(dev);
3714
3715 RL_LOCK(sc);
3716
3717 ifp = sc->rl_ifp;
3718 /* Take controller out of sleep mode. */
3719 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3720 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3721 CSR_WRITE_1(sc, RL_GPIO,
3722 CSR_READ_1(sc, RL_GPIO) | 0x01);
3723 }
3724
3725 /*
3726 * Clear WOL matching such that normal Rx filtering
3727 * wouldn't interfere with WOL patterns.
3728 */
3729 re_clrwol(sc);
3730
3731 /* reinitialize interface if necessary */
3732 if (ifp->if_flags & IFF_UP)
3733 re_init_locked(sc);
3734
3735 sc->suspended = 0;
3736 RL_UNLOCK(sc);
3737
3738 return (0);
3739 }
3740
3741 /*
3742 * Stop all chip I/O so that the kernel's probe routines don't
3743 * get confused by errant DMAs when rebooting.
3744 */
3745 static int
re_shutdown(device_t dev)3746 re_shutdown(device_t dev)
3747 {
3748 struct rl_softc *sc;
3749
3750 sc = device_get_softc(dev);
3751
3752 RL_LOCK(sc);
3753 re_stop(sc);
3754 /*
3755 * Mark interface as down since otherwise we will panic if
3756 * interrupt comes in later on, which can happen in some
3757 * cases.
3758 */
3759 sc->rl_ifp->if_flags &= ~IFF_UP;
3760 re_setwol(sc);
3761 RL_UNLOCK(sc);
3762
3763 return (0);
3764 }
3765
3766 static void
re_set_linkspeed(struct rl_softc * sc)3767 re_set_linkspeed(struct rl_softc *sc)
3768 {
3769 struct mii_softc *miisc;
3770 struct mii_data *mii;
3771 int aneg, i, phyno;
3772
3773 RL_LOCK_ASSERT(sc);
3774
3775 mii = device_get_softc(sc->rl_miibus);
3776 mii_pollstat(mii);
3777 aneg = 0;
3778 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3779 (IFM_ACTIVE | IFM_AVALID)) {
3780 switch IFM_SUBTYPE(mii->mii_media_active) {
3781 case IFM_10_T:
3782 case IFM_100_TX:
3783 return;
3784 case IFM_1000_T:
3785 aneg++;
3786 break;
3787 default:
3788 break;
3789 }
3790 }
3791 miisc = LIST_FIRST(&mii->mii_phys);
3792 phyno = miisc->mii_phy;
3793 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3794 PHY_RESET(miisc);
3795 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3796 re_miibus_writereg(sc->rl_dev, phyno,
3797 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3798 re_miibus_writereg(sc->rl_dev, phyno,
3799 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3800 DELAY(1000);
3801 if (aneg != 0) {
3802 /*
3803 * Poll link state until re(4) get a 10/100Mbps link.
3804 */
3805 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3806 mii_pollstat(mii);
3807 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3808 == (IFM_ACTIVE | IFM_AVALID)) {
3809 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3810 case IFM_10_T:
3811 case IFM_100_TX:
3812 return;
3813 default:
3814 break;
3815 }
3816 }
3817 RL_UNLOCK(sc);
3818 pause("relnk", hz);
3819 RL_LOCK(sc);
3820 }
3821 if (i == MII_ANEGTICKS_GIGE)
3822 device_printf(sc->rl_dev,
3823 "establishing a link failed, WOL may not work!");
3824 }
3825 /*
3826 * No link, force MAC to have 100Mbps, full-duplex link.
3827 * MAC does not require reprogramming on resolved speed/duplex,
3828 * so this is just for completeness.
3829 */
3830 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3831 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3832 }
3833
3834 static void
re_setwol(struct rl_softc * sc)3835 re_setwol(struct rl_softc *sc)
3836 {
3837 struct ifnet *ifp;
3838 int pmc;
3839 uint16_t pmstat;
3840 uint8_t v;
3841
3842 RL_LOCK_ASSERT(sc);
3843
3844 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3845 return;
3846
3847 ifp = sc->rl_ifp;
3848 /* Put controller into sleep mode. */
3849 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3850 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3851 CSR_WRITE_1(sc, RL_GPIO,
3852 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3853 }
3854 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3855 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3856 /* Disable RXDV gate. */
3857 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3858 ~0x00080000);
3859 }
3860 re_set_rxmode(sc);
3861 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3862 re_set_linkspeed(sc);
3863 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3864 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3865 }
3866 /* Enable config register write. */
3867 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3868
3869 /* Enable PME. */
3870 v = CSR_READ_1(sc, sc->rl_cfg1);
3871 v &= ~RL_CFG1_PME;
3872 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3873 v |= RL_CFG1_PME;
3874 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3875
3876 v = CSR_READ_1(sc, sc->rl_cfg3);
3877 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3878 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3879 v |= RL_CFG3_WOL_MAGIC;
3880 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3881
3882 v = CSR_READ_1(sc, sc->rl_cfg5);
3883 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3884 RL_CFG5_WOL_LANWAKE);
3885 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3886 v |= RL_CFG5_WOL_UCAST;
3887 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3888 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3889 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3890 v |= RL_CFG5_WOL_LANWAKE;
3891 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3892
3893 /* Config register write done. */
3894 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3895
3896 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3897 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3898 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3899 /*
3900 * It seems that hardware resets its link speed to 100Mbps in
3901 * power down mode so switching to 100Mbps in driver is not
3902 * needed.
3903 */
3904
3905 /* Request PME if WOL is requested. */
3906 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3907 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3908 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3909 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3910 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3911 }
3912
3913 static void
re_clrwol(struct rl_softc * sc)3914 re_clrwol(struct rl_softc *sc)
3915 {
3916 int pmc;
3917 uint8_t v;
3918
3919 RL_LOCK_ASSERT(sc);
3920
3921 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3922 return;
3923
3924 /* Enable config register write. */
3925 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3926
3927 v = CSR_READ_1(sc, sc->rl_cfg3);
3928 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3929 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3930
3931 /* Config register write done. */
3932 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3933
3934 v = CSR_READ_1(sc, sc->rl_cfg5);
3935 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3936 v &= ~RL_CFG5_WOL_LANWAKE;
3937 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3938 }
3939
3940 static void
re_add_sysctls(struct rl_softc * sc)3941 re_add_sysctls(struct rl_softc *sc)
3942 {
3943 struct sysctl_ctx_list *ctx;
3944 struct sysctl_oid_list *children;
3945 int error;
3946
3947 ctx = device_get_sysctl_ctx(sc->rl_dev);
3948 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3949
3950 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3951 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3952 "Statistics Information");
3953 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3954 return;
3955
3956 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3957 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3958 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3959 /* Pull in device tunables. */
3960 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3961 error = resource_int_value(device_get_name(sc->rl_dev),
3962 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3963 if (error == 0) {
3964 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3965 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3966 device_printf(sc->rl_dev, "int_rx_mod value out of "
3967 "range; using default: %d\n",
3968 RL_TIMER_DEFAULT);
3969 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3970 }
3971 }
3972 }
3973
3974 static int
re_sysctl_stats(SYSCTL_HANDLER_ARGS)3975 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3976 {
3977 struct rl_softc *sc;
3978 struct rl_stats *stats;
3979 int error, i, result;
3980
3981 result = -1;
3982 error = sysctl_handle_int(oidp, &result, 0, req);
3983 if (error || req->newptr == NULL)
3984 return (error);
3985
3986 if (result == 1) {
3987 sc = (struct rl_softc *)arg1;
3988 RL_LOCK(sc);
3989 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3990 RL_UNLOCK(sc);
3991 goto done;
3992 }
3993 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3994 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3995 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3996 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3997 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3998 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3999 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
4000 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
4001 RL_DUMPSTATS_START));
4002 for (i = RL_TIMEOUT; i > 0; i--) {
4003 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
4004 RL_DUMPSTATS_START) == 0)
4005 break;
4006 DELAY(1000);
4007 }
4008 bus_dmamap_sync(sc->rl_ldata.rl_stag,
4009 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
4010 RL_UNLOCK(sc);
4011 if (i == 0) {
4012 device_printf(sc->rl_dev,
4013 "DUMP statistics request timed out\n");
4014 return (ETIMEDOUT);
4015 }
4016 done:
4017 stats = sc->rl_ldata.rl_stats;
4018 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
4019 printf("Tx frames : %ju\n",
4020 (uintmax_t)le64toh(stats->rl_tx_pkts));
4021 printf("Rx frames : %ju\n",
4022 (uintmax_t)le64toh(stats->rl_rx_pkts));
4023 printf("Tx errors : %ju\n",
4024 (uintmax_t)le64toh(stats->rl_tx_errs));
4025 printf("Rx errors : %u\n",
4026 le32toh(stats->rl_rx_errs));
4027 printf("Rx missed frames : %u\n",
4028 (uint32_t)le16toh(stats->rl_missed_pkts));
4029 printf("Rx frame alignment errs : %u\n",
4030 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
4031 printf("Tx single collisions : %u\n",
4032 le32toh(stats->rl_tx_onecoll));
4033 printf("Tx multiple collisions : %u\n",
4034 le32toh(stats->rl_tx_multicolls));
4035 printf("Rx unicast frames : %ju\n",
4036 (uintmax_t)le64toh(stats->rl_rx_ucasts));
4037 printf("Rx broadcast frames : %ju\n",
4038 (uintmax_t)le64toh(stats->rl_rx_bcasts));
4039 printf("Rx multicast frames : %u\n",
4040 le32toh(stats->rl_rx_mcasts));
4041 printf("Tx aborts : %u\n",
4042 (uint32_t)le16toh(stats->rl_tx_aborts));
4043 printf("Tx underruns : %u\n",
4044 (uint32_t)le16toh(stats->rl_rx_underruns));
4045 }
4046
4047 return (error);
4048 }
4049
4050 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)4051 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4052 {
4053 int error, value;
4054
4055 if (arg1 == NULL)
4056 return (EINVAL);
4057 value = *(int *)arg1;
4058 error = sysctl_handle_int(oidp, &value, 0, req);
4059 if (error || req->newptr == NULL)
4060 return (error);
4061 if (value < low || value > high)
4062 return (EINVAL);
4063 *(int *)arg1 = value;
4064
4065 return (0);
4066 }
4067
4068 static int
sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)4069 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4070 {
4071
4072 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,
4073 RL_TIMER_MAX));
4074 }
4075