1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $
18 */
19
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
22
23 /*-
24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver
25 * http://www.ralinktech.com/
26 */
27
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
31 #include <sys/mbuf.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
39 #include <sys/bus.h>
40 #include <sys/endian.h>
41 #include <sys/firmware.h>
42
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <sys/rman.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55
56 #include <net80211/ieee80211_var.h>
57 #include <net80211/ieee80211_radiotap.h>
58 #include <net80211/ieee80211_regdomain.h>
59 #include <net80211/ieee80211_ratectl.h>
60
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_ether.h>
66
67 #include <dev/ral/rt2860reg.h>
68 #include <dev/ral/rt2860var.h>
69
70 #define RAL_DEBUG
71 #ifdef RAL_DEBUG
72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
74 #else
75 #define DPRINTF(x)
76 #define DPRINTFN(n, x)
77 #endif
78
79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *,
80 const char [IFNAMSIZ], int, enum ieee80211_opmode,
81 int, const uint8_t [IEEE80211_ADDR_LEN],
82 const uint8_t [IEEE80211_ADDR_LEN]);
83 static void rt2860_vap_delete(struct ieee80211vap *);
84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int);
85 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
86 struct rt2860_tx_ring *);
87 static void rt2860_reset_tx_ring(struct rt2860_softc *,
88 struct rt2860_tx_ring *);
89 static void rt2860_free_tx_ring(struct rt2860_softc *,
90 struct rt2860_tx_ring *);
91 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
92 static void rt2860_free_tx_pool(struct rt2860_softc *);
93 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
94 struct rt2860_rx_ring *);
95 static void rt2860_reset_rx_ring(struct rt2860_softc *,
96 struct rt2860_rx_ring *);
97 static void rt2860_free_rx_ring(struct rt2860_softc *,
98 struct rt2860_rx_ring *);
99 static void rt2860_updatestats(struct rt2860_softc *);
100 static void rt2860_newassoc(struct ieee80211_node *, int);
101 static void rt2860_node_free(struct ieee80211_node *);
102 #ifdef IEEE80211_HT
103 static int rt2860_ampdu_rx_start(struct ieee80211com *,
104 struct ieee80211_node *, uint8_t);
105 static void rt2860_ampdu_rx_stop(struct ieee80211com *,
106 struct ieee80211_node *, uint8_t);
107 #endif
108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state,
109 int);
110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
112 static void rt2860_intr_coherent(struct rt2860_softc *);
113 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
114 static void rt2860_tx_intr(struct rt2860_softc *, int);
115 static void rt2860_rx_intr(struct rt2860_softc *);
116 static void rt2860_tbtt_intr(struct rt2860_softc *);
117 static void rt2860_gp_intr(struct rt2860_softc *);
118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *,
119 struct ieee80211_node *);
120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *,
121 const struct ieee80211_bpf_params *);
122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *,
123 struct ieee80211_node *,
124 const struct ieee80211_bpf_params *params);
125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *);
126 static void rt2860_start(struct rt2860_softc *);
127 static void rt2860_watchdog(void *);
128 static void rt2860_parent(struct ieee80211com *);
129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
135 static void rt2860_enable_mrr(struct rt2860_softc *);
136 static void rt2860_set_txpreamble(struct rt2860_softc *);
137 static void rt2860_set_basicrates(struct rt2860_softc *,
138 const struct ieee80211_rateset *);
139 static void rt2860_scan_start(struct ieee80211com *);
140 static void rt2860_scan_end(struct ieee80211com *);
141 static void rt2860_getradiocaps(struct ieee80211com *, int, int *,
142 struct ieee80211_channel[]);
143 static void rt2860_set_channel(struct ieee80211com *);
144 static void rt2860_select_chan_group(struct rt2860_softc *, int);
145 static void rt2860_set_chan(struct rt2860_softc *, u_int);
146 static void rt3090_set_chan(struct rt2860_softc *, u_int);
147 static void rt5390_set_chan(struct rt2860_softc *, u_int);
148 static int rt3090_rf_init(struct rt2860_softc *);
149 static void rt5390_rf_init(struct rt2860_softc *);
150 static void rt3090_rf_wakeup(struct rt2860_softc *);
151 static void rt5390_rf_wakeup(struct rt2860_softc *);
152 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
153 uint8_t *);
154 static void rt3090_rf_setup(struct rt2860_softc *);
155 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
156 static void rt2860_set_gp_timer(struct rt2860_softc *, int);
157 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
158 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
159 static void rt2860_update_promisc(struct ieee80211com *);
160 static void rt2860_updateslot(struct ieee80211com *);
161 static void rt2860_updateprot(struct rt2860_softc *);
162 static int rt2860_updateedca(struct ieee80211com *);
163 #ifdef HW_CRYPTO
164 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
165 struct ieee80211_key *);
166 static void rt2860_delete_key(struct ieee80211com *,
167 struct ieee80211_node *, struct ieee80211_key *);
168 #endif
169 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
170 static const char *rt2860_get_rf(uint16_t);
171 static int rt2860_read_eeprom(struct rt2860_softc *,
172 uint8_t macaddr[IEEE80211_ADDR_LEN]);
173 static int rt2860_bbp_init(struct rt2860_softc *);
174 static void rt5390_bbp_init(struct rt2860_softc *);
175 static int rt2860_txrx_enable(struct rt2860_softc *);
176 static void rt2860_init(void *);
177 static void rt2860_init_locked(struct rt2860_softc *);
178 static void rt2860_stop(void *);
179 static void rt2860_stop_locked(struct rt2860_softc *);
180 static int rt2860_load_microcode(struct rt2860_softc *);
181 #ifdef NOT_YET
182 static void rt2860_calib(struct rt2860_softc *);
183 #endif
184 static void rt3090_set_rx_antenna(struct rt2860_softc *, int);
185 static void rt2860_switch_chan(struct rt2860_softc *,
186 struct ieee80211_channel *);
187 static int rt2860_setup_beacon(struct rt2860_softc *,
188 struct ieee80211vap *);
189 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
190
191 static const struct {
192 uint32_t reg;
193 uint32_t val;
194 } rt2860_def_mac[] = {
195 RT2860_DEF_MAC
196 };
197
198 static const struct {
199 uint8_t reg;
200 uint8_t val;
201 } rt2860_def_bbp[] = {
202 RT2860_DEF_BBP
203 }, rt5390_def_bbp[] = {
204 RT5390_DEF_BBP
205 };
206
207 static const struct rfprog {
208 uint8_t chan;
209 uint32_t r1, r2, r3, r4;
210 } rt2860_rf2850[] = {
211 RT2860_RF2850
212 };
213
214 struct {
215 uint8_t n, r, k;
216 } rt3090_freqs[] = {
217 RT3070_RF3052
218 };
219
220 static const struct {
221 uint8_t reg;
222 uint8_t val;
223 } rt3090_def_rf[] = {
224 RT3070_DEF_RF
225 }, rt5390_def_rf[] = {
226 RT5390_DEF_RF
227 }, rt5392_def_rf[] = {
228 RT5392_DEF_RF
229 };
230
231 static const uint8_t rt2860_chan_5ghz[] =
232 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104,
233 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140,
234 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 };
235
236 int
rt2860_attach(device_t dev,int id)237 rt2860_attach(device_t dev, int id)
238 {
239 struct rt2860_softc *sc = device_get_softc(dev);
240 struct ieee80211com *ic = &sc->sc_ic;
241 uint32_t tmp;
242 int error, ntries, qid;
243
244 sc->sc_dev = dev;
245 sc->sc_debug = 0;
246
247 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
248 MTX_DEF | MTX_RECURSE);
249
250 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
251 mbufq_init(&sc->sc_snd, ifqmaxlen);
252
253 /* wait for NIC to initialize */
254 for (ntries = 0; ntries < 100; ntries++) {
255 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
256 if (tmp != 0 && tmp != 0xffffffff)
257 break;
258 DELAY(10);
259 }
260 if (ntries == 100) {
261 device_printf(sc->sc_dev,
262 "timeout waiting for NIC to initialize\n");
263 error = EIO;
264 goto fail1;
265 }
266 sc->mac_ver = tmp >> 16;
267 sc->mac_rev = tmp & 0xffff;
268
269 if (sc->mac_ver != 0x2860 &&
270 (id == 0x0681 || id == 0x0781 || id == 0x1059))
271 sc->sc_flags |= RT2860_ADVANCED_PS;
272
273 /* retrieve RF rev. no and various other things from EEPROM */
274 rt2860_read_eeprom(sc, ic->ic_macaddr);
275 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
276 "RF %s (MIMO %dT%dR), address %6D\n",
277 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
278 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":");
279
280 /*
281 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
282 */
283 for (qid = 0; qid < 6; qid++) {
284 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
285 device_printf(sc->sc_dev,
286 "could not allocate Tx ring %d\n", qid);
287 goto fail2;
288 }
289 }
290
291 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
292 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
293 goto fail2;
294 }
295
296 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
297 device_printf(sc->sc_dev, "could not allocate Tx pool\n");
298 goto fail3;
299 }
300
301 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
302 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
303 WME_AC_VO : 5;
304
305 ic->ic_softc = sc;
306 ic->ic_name = device_get_nameunit(dev);
307 ic->ic_opmode = IEEE80211_M_STA;
308 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
309
310 /* set device capabilities */
311 ic->ic_caps =
312 IEEE80211_C_STA /* station mode */
313 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
314 | IEEE80211_C_HOSTAP /* hostap mode */
315 | IEEE80211_C_MONITOR /* monitor mode */
316 | IEEE80211_C_AHDEMO /* adhoc demo mode */
317 | IEEE80211_C_WDS /* 4-address traffic works */
318 | IEEE80211_C_MBSS /* mesh point link mode */
319 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
320 | IEEE80211_C_SHSLOT /* short slot time supported */
321 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
322 #if 0
323 | IEEE80211_C_BGSCAN /* capable of bg scanning */
324 #endif
325 | IEEE80211_C_WME /* 802.11e */
326 ;
327
328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
329 ic->ic_channels);
330
331 ieee80211_ifattach(ic);
332
333 ic->ic_wme.wme_update = rt2860_updateedca;
334 ic->ic_scan_start = rt2860_scan_start;
335 ic->ic_scan_end = rt2860_scan_end;
336 ic->ic_getradiocaps = rt2860_getradiocaps;
337 ic->ic_set_channel = rt2860_set_channel;
338 ic->ic_updateslot = rt2860_updateslot;
339 ic->ic_update_promisc = rt2860_update_promisc;
340 ic->ic_raw_xmit = rt2860_raw_xmit;
341 sc->sc_node_free = ic->ic_node_free;
342 ic->ic_node_free = rt2860_node_free;
343 ic->ic_newassoc = rt2860_newassoc;
344 ic->ic_transmit = rt2860_transmit;
345 ic->ic_parent = rt2860_parent;
346 ic->ic_vap_create = rt2860_vap_create;
347 ic->ic_vap_delete = rt2860_vap_delete;
348
349 ieee80211_radiotap_attach(ic,
350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
351 RT2860_TX_RADIOTAP_PRESENT,
352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
353 RT2860_RX_RADIOTAP_PRESENT);
354
355 #ifdef RAL_DEBUG
356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
359 #endif
360 if (bootverbose)
361 ieee80211_announce(ic);
362
363 return 0;
364
365 fail3: rt2860_free_rx_ring(sc, &sc->rxq);
366 fail2: while (--qid >= 0)
367 rt2860_free_tx_ring(sc, &sc->txq[qid]);
368 fail1: mtx_destroy(&sc->sc_mtx);
369 return error;
370 }
371
372 int
rt2860_detach(void * xsc)373 rt2860_detach(void *xsc)
374 {
375 struct rt2860_softc *sc = xsc;
376 struct ieee80211com *ic = &sc->sc_ic;
377 int qid;
378
379 RAL_LOCK(sc);
380 rt2860_stop_locked(sc);
381 RAL_UNLOCK(sc);
382
383 ieee80211_ifdetach(ic);
384 mbufq_drain(&sc->sc_snd);
385 for (qid = 0; qid < 6; qid++)
386 rt2860_free_tx_ring(sc, &sc->txq[qid]);
387 rt2860_free_rx_ring(sc, &sc->rxq);
388 rt2860_free_tx_pool(sc);
389
390 mtx_destroy(&sc->sc_mtx);
391
392 return 0;
393 }
394
395 void
rt2860_shutdown(void * xsc)396 rt2860_shutdown(void *xsc)
397 {
398 struct rt2860_softc *sc = xsc;
399
400 rt2860_stop(sc);
401 }
402
403 void
rt2860_suspend(void * xsc)404 rt2860_suspend(void *xsc)
405 {
406 struct rt2860_softc *sc = xsc;
407
408 rt2860_stop(sc);
409 }
410
411 void
rt2860_resume(void * xsc)412 rt2860_resume(void *xsc)
413 {
414 struct rt2860_softc *sc = xsc;
415
416 if (sc->sc_ic.ic_nrunning > 0)
417 rt2860_init(sc);
418 }
419
420 static struct ieee80211vap *
rt2860_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])421 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
422 enum ieee80211_opmode opmode, int flags,
423 const uint8_t bssid[IEEE80211_ADDR_LEN],
424 const uint8_t mac[IEEE80211_ADDR_LEN])
425 {
426 struct rt2860_softc *sc = ic->ic_softc;
427 struct rt2860_vap *rvp;
428 struct ieee80211vap *vap;
429
430 switch (opmode) {
431 case IEEE80211_M_STA:
432 case IEEE80211_M_IBSS:
433 case IEEE80211_M_AHDEMO:
434 case IEEE80211_M_MONITOR:
435 case IEEE80211_M_HOSTAP:
436 case IEEE80211_M_MBSS:
437 /* XXXRP: TBD */
438 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
439 device_printf(sc->sc_dev, "only 1 vap supported\n");
440 return NULL;
441 }
442 if (opmode == IEEE80211_M_STA)
443 flags |= IEEE80211_CLONE_NOBEACONS;
444 break;
445 case IEEE80211_M_WDS:
446 if (TAILQ_EMPTY(&ic->ic_vaps) ||
447 ic->ic_opmode != IEEE80211_M_HOSTAP) {
448 device_printf(sc->sc_dev,
449 "wds only supported in ap mode\n");
450 return NULL;
451 }
452 /*
453 * Silently remove any request for a unique
454 * bssid; WDS vap's always share the local
455 * mac address.
456 */
457 flags &= ~IEEE80211_CLONE_BSSID;
458 break;
459 default:
460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
461 return NULL;
462 }
463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO);
464 vap = &rvp->ral_vap;
465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
466
467 /* override state transition machine */
468 rvp->ral_newstate = vap->iv_newstate;
469 vap->iv_newstate = rt2860_newstate;
470 #if 0
471 vap->iv_update_beacon = rt2860_beacon_update;
472 #endif
473
474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
476
477 ieee80211_ratectl_init(vap);
478 /* complete setup */
479 ieee80211_vap_attach(vap, ieee80211_media_change,
480 ieee80211_media_status, mac);
481 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
482 ic->ic_opmode = opmode;
483 return vap;
484 }
485
486 static void
rt2860_vap_delete(struct ieee80211vap * vap)487 rt2860_vap_delete(struct ieee80211vap *vap)
488 {
489 struct rt2860_vap *rvp = RT2860_VAP(vap);
490
491 ieee80211_ratectl_deinit(vap);
492 ieee80211_vap_detach(vap);
493 free(rvp, M_80211_VAP);
494 }
495
496 static void
rt2860_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)497 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
498 {
499 if (error != 0)
500 return;
501
502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
503
504 *(bus_addr_t *)arg = segs[0].ds_addr;
505 }
506
507
508 static int
rt2860_alloc_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)509 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
510 {
511 int size, error;
512
513 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
514
515 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
516 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
517 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
518 if (error != 0) {
519 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
520 goto fail;
521 }
522
523 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd,
524 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
525 if (error != 0) {
526 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
527 goto fail;
528 }
529
530 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd,
531 size, rt2860_dma_map_addr, &ring->paddr, 0);
532 if (error != 0) {
533 device_printf(sc->sc_dev, "could not load desc DMA map\n");
534 goto fail;
535 }
536
537 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
538
539 return 0;
540
541 fail: rt2860_free_tx_ring(sc, ring);
542 return error;
543 }
544
545 void
rt2860_reset_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)546 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
547 {
548 struct rt2860_tx_data *data;
549 int i;
550
551 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
552 if ((data = ring->data[i]) == NULL)
553 continue; /* nothing mapped in this slot */
554
555 if (data->m != NULL) {
556 bus_dmamap_sync(sc->txwi_dmat, data->map,
557 BUS_DMASYNC_POSTWRITE);
558 bus_dmamap_unload(sc->txwi_dmat, data->map);
559 m_freem(data->m);
560 data->m = NULL;
561 }
562 if (data->ni != NULL) {
563 ieee80211_free_node(data->ni);
564 data->ni = NULL;
565 }
566
567 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
568 ring->data[i] = NULL;
569 }
570
571 ring->queued = 0;
572 ring->cur = ring->next = 0;
573 }
574
575 void
rt2860_free_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)576 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
577 {
578 struct rt2860_tx_data *data;
579 int i;
580
581 if (ring->txd != NULL) {
582 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
583 BUS_DMASYNC_POSTWRITE);
584 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
585 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map);
586 }
587 if (ring->desc_dmat != NULL)
588 bus_dma_tag_destroy(ring->desc_dmat);
589
590 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
591 if ((data = ring->data[i]) == NULL)
592 continue; /* nothing mapped in this slot */
593
594 if (data->m != NULL) {
595 bus_dmamap_sync(sc->txwi_dmat, data->map,
596 BUS_DMASYNC_POSTWRITE);
597 bus_dmamap_unload(sc->txwi_dmat, data->map);
598 m_freem(data->m);
599 }
600 if (data->ni != NULL)
601 ieee80211_free_node(data->ni);
602
603 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
604 }
605 }
606
607 /*
608 * Allocate a pool of TX Wireless Information blocks.
609 */
610 int
rt2860_alloc_tx_pool(struct rt2860_softc * sc)611 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
612 {
613 caddr_t vaddr;
614 bus_addr_t paddr;
615 int i, size, error;
616
617 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ;
618
619 /* init data_pool early in case of failure.. */
620 SLIST_INIT(&sc->data_pool);
621
622 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
623 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
624 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat);
625 if (error != 0) {
626 device_printf(sc->sc_dev, "could not create txwi DMA tag\n");
627 goto fail;
628 }
629
630 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr,
631 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map);
632 if (error != 0) {
633 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
634 goto fail;
635 }
636
637 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map,
638 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0);
639 if (error != 0) {
640 device_printf(sc->sc_dev, "could not load txwi DMA map\n");
641 goto fail;
642 }
643
644 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
645
646 vaddr = sc->txwi_vaddr;
647 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
648 struct rt2860_tx_data *data = &sc->data[i];
649
650 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map);
651 if (error != 0) {
652 device_printf(sc->sc_dev, "could not create DMA map\n");
653 goto fail;
654 }
655 data->txwi = (struct rt2860_txwi *)vaddr;
656 data->paddr = paddr;
657 vaddr += RT2860_TXWI_DMASZ;
658 paddr += RT2860_TXWI_DMASZ;
659
660 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
661 }
662
663 return 0;
664
665 fail: rt2860_free_tx_pool(sc);
666 return error;
667 }
668
669 void
rt2860_free_tx_pool(struct rt2860_softc * sc)670 rt2860_free_tx_pool(struct rt2860_softc *sc)
671 {
672 if (sc->txwi_vaddr != NULL) {
673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map,
674 BUS_DMASYNC_POSTWRITE);
675 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map);
676 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map);
677 }
678 if (sc->txwi_dmat != NULL)
679 bus_dma_tag_destroy(sc->txwi_dmat);
680
681 while (!SLIST_EMPTY(&sc->data_pool)) {
682 struct rt2860_tx_data *data;
683 data = SLIST_FIRST(&sc->data_pool);
684 bus_dmamap_destroy(sc->txwi_dmat, data->map);
685 SLIST_REMOVE_HEAD(&sc->data_pool, next);
686 }
687 }
688
689 int
rt2860_alloc_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)690 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
691 {
692 bus_addr_t physaddr;
693 int i, size, error;
694
695 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
696
697 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
698 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
699 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
700 if (error != 0) {
701 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
702 goto fail;
703 }
704
705 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd,
706 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
707 if (error != 0) {
708 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
709 goto fail;
710 }
711
712 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd,
713 size, rt2860_dma_map_addr, &ring->paddr, 0);
714 if (error != 0) {
715 device_printf(sc->sc_dev, "could not load desc DMA map\n");
716 goto fail;
717 }
718
719 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
720 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
721 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
722 if (error != 0) {
723 device_printf(sc->sc_dev, "could not create data DMA tag\n");
724 goto fail;
725 }
726
727 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
728 struct rt2860_rx_data *data = &ring->data[i];
729 struct rt2860_rxd *rxd = &ring->rxd[i];
730
731 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
732 if (error != 0) {
733 device_printf(sc->sc_dev, "could not create DMA map\n");
734 goto fail;
735 }
736
737 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
738 if (data->m == NULL) {
739 device_printf(sc->sc_dev,
740 "could not allocate rx mbuf\n");
741 error = ENOMEM;
742 goto fail;
743 }
744
745 error = bus_dmamap_load(ring->data_dmat, data->map,
746 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr,
747 &physaddr, 0);
748 if (error != 0) {
749 device_printf(sc->sc_dev,
750 "could not load rx buf DMA map");
751 goto fail;
752 }
753
754 rxd->sdp0 = htole32(physaddr);
755 rxd->sdl0 = htole16(MCLBYTES);
756 }
757
758 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
759
760 return 0;
761
762 fail: rt2860_free_rx_ring(sc, ring);
763 return error;
764 }
765
766 void
rt2860_reset_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)767 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
768 {
769 int i;
770
771 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
772 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
773
774 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
775
776 ring->cur = 0;
777 }
778
779 void
rt2860_free_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)780 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
781 {
782 int i;
783
784 if (ring->rxd != NULL) {
785 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
786 BUS_DMASYNC_POSTWRITE);
787 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
788 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map);
789 }
790 if (ring->desc_dmat != NULL)
791 bus_dma_tag_destroy(ring->desc_dmat);
792
793 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
794 struct rt2860_rx_data *data = &ring->data[i];
795
796 if (data->m != NULL) {
797 bus_dmamap_sync(ring->data_dmat, data->map,
798 BUS_DMASYNC_POSTREAD);
799 bus_dmamap_unload(ring->data_dmat, data->map);
800 m_freem(data->m);
801 }
802 if (data->map != NULL)
803 bus_dmamap_destroy(ring->data_dmat, data->map);
804 }
805 if (ring->data_dmat != NULL)
806 bus_dma_tag_destroy(ring->data_dmat);
807 }
808
809 static void
rt2860_updatestats(struct rt2860_softc * sc)810 rt2860_updatestats(struct rt2860_softc *sc)
811 {
812 struct ieee80211com *ic = &sc->sc_ic;
813
814 /*
815 * In IBSS or HostAP modes (when the hardware sends beacons), the
816 * MAC can run into a livelock and start sending CTS-to-self frames
817 * like crazy if protection is enabled. Fortunately, we can detect
818 * when such a situation occurs and reset the MAC.
819 */
820 if (ic->ic_curmode != IEEE80211_M_STA) {
821 /* check if we're in a livelock situation.. */
822 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
823 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
824 /* ..and reset MAC/BBP for a while.. */
825 DPRINTF(("CTS-to-self livelock detected\n"));
826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST);
827 RAL_BARRIER_WRITE(sc);
828 DELAY(1);
829 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
830 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
831 }
832 }
833 }
834
835 static void
rt2860_newassoc(struct ieee80211_node * ni,int isnew)836 rt2860_newassoc(struct ieee80211_node *ni, int isnew)
837 {
838 struct ieee80211com *ic = ni->ni_ic;
839 struct rt2860_softc *sc = ic->ic_softc;
840 uint8_t wcid;
841
842 wcid = IEEE80211_AID(ni->ni_associd);
843 if (isnew && ni->ni_associd != 0) {
844 sc->wcid2ni[wcid] = ni;
845
846 /* init WCID table entry */
847 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),
848 ni->ni_macaddr, IEEE80211_ADDR_LEN);
849 }
850 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
851 isnew, ether_sprintf(ni->ni_macaddr), wcid));
852 }
853
854 static void
rt2860_node_free(struct ieee80211_node * ni)855 rt2860_node_free(struct ieee80211_node *ni)
856 {
857 struct ieee80211com *ic = ni->ni_ic;
858 struct rt2860_softc *sc = ic->ic_softc;
859 uint8_t wcid;
860
861 if (ni->ni_associd != 0) {
862 wcid = IEEE80211_AID(ni->ni_associd);
863
864 /* clear Rx WCID search table entry */
865 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2);
866 }
867 sc->sc_node_free(ni);
868 }
869
870 #ifdef IEEE80211_HT
871 static int
rt2860_ampdu_rx_start(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)872 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
873 uint8_t tid)
874 {
875 struct rt2860_softc *sc = ic->ic_softc;
876 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
877 uint32_t tmp;
878
879 /* update BA session mask */
880 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
881 tmp |= (1 << tid) << 16;
882 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
883 return 0;
884 }
885
886 static void
rt2860_ampdu_rx_stop(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)887 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
888 uint8_t tid)
889 {
890 struct rt2860_softc *sc = ic->ic_softc;
891 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
892 uint32_t tmp;
893
894 /* update BA session mask */
895 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
896 tmp &= ~((1 << tid) << 16);
897 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
898 }
899 #endif
900
901 static int
rt2860_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)902 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
903 {
904 struct rt2860_vap *rvp = RT2860_VAP(vap);
905 struct ieee80211com *ic = vap->iv_ic;
906 struct rt2860_softc *sc = ic->ic_softc;
907 uint32_t tmp;
908 int error;
909
910 if (vap->iv_state == IEEE80211_S_RUN) {
911 /* turn link LED off */
912 rt2860_set_leds(sc, RT2860_LED_RADIO);
913 }
914
915 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
916 /* abort TSF synchronization */
917 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
918 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
919 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
920 RT2860_TBTT_TIMER_EN));
921 }
922
923 rt2860_set_gp_timer(sc, 0);
924
925 error = rvp->ral_newstate(vap, nstate, arg);
926 if (error != 0)
927 return (error);
928
929 if (nstate == IEEE80211_S_RUN) {
930 struct ieee80211_node *ni = vap->iv_bss;
931
932 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
933 rt2860_enable_mrr(sc);
934 rt2860_set_txpreamble(sc);
935 rt2860_set_basicrates(sc, &ni->ni_rates);
936 rt2860_set_bssid(sc, ni->ni_bssid);
937 }
938
939 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
940 vap->iv_opmode == IEEE80211_M_IBSS ||
941 vap->iv_opmode == IEEE80211_M_MBSS) {
942 error = rt2860_setup_beacon(sc, vap);
943 if (error != 0)
944 return error;
945 }
946
947 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
948 rt2860_enable_tsf_sync(sc);
949 rt2860_set_gp_timer(sc, 500);
950 }
951
952 /* turn link LED on */
953 rt2860_set_leds(sc, RT2860_LED_RADIO |
954 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ?
955 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
956 }
957 return error;
958 }
959
960 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
961 static uint16_t
rt3090_efuse_read_2(struct rt2860_softc * sc,uint16_t addr)962 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
963 {
964 uint32_t tmp;
965 uint16_t reg;
966 int ntries;
967
968 addr *= 2;
969 /*-
970 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
971 * DATA0: F E D C
972 * DATA1: B A 9 8
973 * DATA2: 7 6 5 4
974 * DATA3: 3 2 1 0
975 */
976 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
977 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
978 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
979 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
980 for (ntries = 0; ntries < 500; ntries++) {
981 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
982 if (!(tmp & RT3070_EFSROM_KICK))
983 break;
984 DELAY(2);
985 }
986 if (ntries == 500)
987 return 0xffff;
988
989 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
990 return 0xffff; /* address not found */
991
992 /* determine to which 32-bit register our 16-bit word belongs */
993 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
994 tmp = RAL_READ(sc, reg);
995
996 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
997 }
998
999 /*
1000 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1001 * 93C66 or 93C86).
1002 */
1003 static uint16_t
rt2860_eeprom_read_2(struct rt2860_softc * sc,uint16_t addr)1004 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1005 {
1006 uint32_t tmp;
1007 uint16_t val;
1008 int n;
1009
1010 /* clock C once before the first command */
1011 RT2860_EEPROM_CTL(sc, 0);
1012
1013 RT2860_EEPROM_CTL(sc, RT2860_S);
1014 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1015 RT2860_EEPROM_CTL(sc, RT2860_S);
1016
1017 /* write start bit (1) */
1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1020
1021 /* write READ opcode (10) */
1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1023 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1024 RT2860_EEPROM_CTL(sc, RT2860_S);
1025 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1026
1027 /* write address (A5-A0 or A7-A0) */
1028 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1029 for (; n >= 0; n--) {
1030 RT2860_EEPROM_CTL(sc, RT2860_S |
1031 (((addr >> n) & 1) << RT2860_SHIFT_D));
1032 RT2860_EEPROM_CTL(sc, RT2860_S |
1033 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
1034 }
1035
1036 RT2860_EEPROM_CTL(sc, RT2860_S);
1037
1038 /* read data Q15-Q0 */
1039 val = 0;
1040 for (n = 15; n >= 0; n--) {
1041 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1042 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
1043 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
1044 RT2860_EEPROM_CTL(sc, RT2860_S);
1045 }
1046
1047 RT2860_EEPROM_CTL(sc, 0);
1048
1049 /* clear Chip Select and clock C */
1050 RT2860_EEPROM_CTL(sc, RT2860_S);
1051 RT2860_EEPROM_CTL(sc, 0);
1052 RT2860_EEPROM_CTL(sc, RT2860_C);
1053
1054 return val;
1055 }
1056
1057 static __inline uint16_t
rt2860_srom_read(struct rt2860_softc * sc,uint8_t addr)1058 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1059 {
1060 /* either eFUSE ROM or EEPROM */
1061 return sc->sc_srom_read(sc, addr);
1062 }
1063
1064 static void
rt2860_intr_coherent(struct rt2860_softc * sc)1065 rt2860_intr_coherent(struct rt2860_softc *sc)
1066 {
1067 uint32_t tmp;
1068
1069 /* DMA finds data coherent event when checking the DDONE bit */
1070
1071 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1072
1073 /* restart DMA engine */
1074 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
1075 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
1076 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
1077
1078 (void)rt2860_txrx_enable(sc);
1079 }
1080
1081 static void
rt2860_drain_stats_fifo(struct rt2860_softc * sc)1082 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1083 {
1084 struct ieee80211_node *ni;
1085 uint32_t stat;
1086 int retrycnt;
1087 uint8_t wcid, mcs, pid;
1088
1089 /* drain Tx status FIFO (maxsize = 16) */
1090 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1091 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1092
1093 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff;
1094 if (wcid > RT2860_WCID_MAX)
1095 continue;
1096 ni = sc->wcid2ni[wcid];
1097
1098 /* if no ACK was requested, no feedback is available */
1099 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL)
1100 continue;
1101
1102 /* update per-STA AMRR stats */
1103 if (stat & RT2860_TXQ_OK) {
1104 /*
1105 * Check if there were retries, ie if the Tx success
1106 * rate is different from the requested rate. Note
1107 * that it works only because we do not allow rate
1108 * fallback from OFDM to CCK.
1109 */
1110 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1111 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1112 if (mcs + 1 != pid)
1113 retrycnt = 1;
1114 else
1115 retrycnt = 0;
1116 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1117 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL);
1118 } else {
1119 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1120 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL);
1121 if_inc_counter(ni->ni_vap->iv_ifp,
1122 IFCOUNTER_OERRORS, 1);
1123 }
1124 }
1125 }
1126
1127 static void
rt2860_tx_intr(struct rt2860_softc * sc,int qid)1128 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1129 {
1130 struct rt2860_tx_ring *ring = &sc->txq[qid];
1131 uint32_t hw;
1132
1133 rt2860_drain_stats_fifo(sc);
1134
1135 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid));
1136 while (ring->next != hw) {
1137 struct rt2860_tx_data *data = ring->data[ring->next];
1138
1139 if (data != NULL) {
1140 bus_dmamap_sync(sc->txwi_dmat, data->map,
1141 BUS_DMASYNC_POSTWRITE);
1142 bus_dmamap_unload(sc->txwi_dmat, data->map);
1143 ieee80211_tx_complete(data->ni, data->m, 0);
1144 data->ni = NULL;
1145 data->m = NULL;
1146 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1147 ring->data[ring->next] = NULL;
1148 }
1149 ring->queued--;
1150 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1151 }
1152
1153 sc->sc_tx_timer = 0;
1154 if (ring->queued < RT2860_TX_RING_COUNT)
1155 sc->qfullmsk &= ~(1 << qid);
1156 rt2860_start(sc);
1157 }
1158
1159 /*
1160 * Return the Rx chain with the highest RSSI for a given frame.
1161 */
1162 static __inline uint8_t
rt2860_maxrssi_chain(struct rt2860_softc * sc,const struct rt2860_rxwi * rxwi)1163 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1164 {
1165 uint8_t rxchain = 0;
1166
1167 if (sc->nrxchains > 1) {
1168 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1169 rxchain = 1;
1170 if (sc->nrxchains > 2)
1171 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1172 rxchain = 2;
1173 }
1174 return rxchain;
1175 }
1176
1177 static void
rt2860_rx_intr(struct rt2860_softc * sc)1178 rt2860_rx_intr(struct rt2860_softc *sc)
1179 {
1180 struct rt2860_rx_radiotap_header *tap;
1181 struct ieee80211com *ic = &sc->sc_ic;
1182 struct ieee80211_frame *wh;
1183 struct ieee80211_node *ni;
1184 struct mbuf *m, *m1;
1185 bus_addr_t physaddr;
1186 uint32_t hw;
1187 uint16_t phy;
1188 uint8_t ant;
1189 int8_t rssi, nf;
1190 int error;
1191
1192 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff;
1193 while (sc->rxq.cur != hw) {
1194 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1195 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1196 struct rt2860_rxwi *rxwi;
1197
1198 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1199 BUS_DMASYNC_POSTREAD);
1200
1201 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1202 DPRINTF(("RXD DDONE bit not set!\n"));
1203 break; /* should not happen */
1204 }
1205
1206 if (__predict_false(rxd->flags &
1207 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) {
1208 counter_u64_add(ic->ic_ierrors, 1);
1209 goto skip;
1210 }
1211
1212 #ifdef HW_CRYPTO
1213 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1214 /* report MIC failures to net80211 for TKIP */
1215 ic->ic_stats.is_rx_locmicfail++;
1216 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1217 counter_u64_add(ic->ic_ierrors, 1);
1218 goto skip;
1219 }
1220 #endif
1221
1222 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1223 if (__predict_false(m1 == NULL)) {
1224 counter_u64_add(ic->ic_ierrors, 1);
1225 goto skip;
1226 }
1227
1228 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1229 BUS_DMASYNC_POSTREAD);
1230 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1231
1232 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1233 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr,
1234 &physaddr, 0);
1235 if (__predict_false(error != 0)) {
1236 m_freem(m1);
1237
1238 /* try to reload the old mbuf */
1239 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1240 mtod(data->m, void *), MCLBYTES,
1241 rt2860_dma_map_addr, &physaddr, 0);
1242 if (__predict_false(error != 0)) {
1243 panic("%s: could not load old rx mbuf",
1244 device_get_name(sc->sc_dev));
1245 }
1246 /* physical address may have changed */
1247 rxd->sdp0 = htole32(physaddr);
1248 counter_u64_add(ic->ic_ierrors, 1);
1249 goto skip;
1250 }
1251
1252 /*
1253 * New mbuf successfully loaded, update Rx ring and continue
1254 * processing.
1255 */
1256 m = data->m;
1257 data->m = m1;
1258 rxd->sdp0 = htole32(physaddr);
1259
1260 rxwi = mtod(m, struct rt2860_rxwi *);
1261
1262 /* finalize mbuf */
1263 m->m_data = (caddr_t)(rxwi + 1);
1264 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff;
1265
1266 wh = mtod(m, struct ieee80211_frame *);
1267 #ifdef HW_CRYPTO
1268 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1269 /* frame is decrypted by hardware */
1270 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1271 }
1272 #endif
1273
1274 /* HW may insert 2 padding bytes after 802.11 header */
1275 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1276 u_int hdrlen = ieee80211_hdrsize(wh);
1277 ovbcopy(wh, (caddr_t)wh + 2, hdrlen);
1278 m->m_data += 2;
1279 wh = mtod(m, struct ieee80211_frame *);
1280 }
1281
1282 ant = rt2860_maxrssi_chain(sc, rxwi);
1283 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant);
1284 nf = RT2860_NOISE_FLOOR;
1285
1286 if (ieee80211_radiotap_active(ic)) {
1287 tap = &sc->sc_rxtap;
1288 tap->wr_flags = 0;
1289 tap->wr_antenna = ant;
1290 tap->wr_antsignal = nf + rssi;
1291 tap->wr_antnoise = nf;
1292 /* in case it can't be found below */
1293 tap->wr_rate = 2;
1294 phy = le16toh(rxwi->phy);
1295 switch (phy & RT2860_PHY_MODE) {
1296 case RT2860_PHY_CCK:
1297 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
1298 case 0: tap->wr_rate = 2; break;
1299 case 1: tap->wr_rate = 4; break;
1300 case 2: tap->wr_rate = 11; break;
1301 case 3: tap->wr_rate = 22; break;
1302 }
1303 if (phy & RT2860_PHY_SHPRE)
1304 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1305 break;
1306 case RT2860_PHY_OFDM:
1307 switch (phy & RT2860_PHY_MCS) {
1308 case 0: tap->wr_rate = 12; break;
1309 case 1: tap->wr_rate = 18; break;
1310 case 2: tap->wr_rate = 24; break;
1311 case 3: tap->wr_rate = 36; break;
1312 case 4: tap->wr_rate = 48; break;
1313 case 5: tap->wr_rate = 72; break;
1314 case 6: tap->wr_rate = 96; break;
1315 case 7: tap->wr_rate = 108; break;
1316 }
1317 break;
1318 }
1319 }
1320
1321 RAL_UNLOCK(sc);
1322 wh = mtod(m, struct ieee80211_frame *);
1323
1324 /* send the frame to the 802.11 layer */
1325 ni = ieee80211_find_rxnode(ic,
1326 (struct ieee80211_frame_min *)wh);
1327 if (ni != NULL) {
1328 (void)ieee80211_input(ni, m, rssi - nf, nf);
1329 ieee80211_free_node(ni);
1330 } else
1331 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
1332
1333 RAL_LOCK(sc);
1334
1335 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1336
1337 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1338 BUS_DMASYNC_PREWRITE);
1339
1340 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1341 }
1342
1343 /* tell HW what we have processed */
1344 RAL_WRITE(sc, RT2860_RX_CALC_IDX,
1345 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1346 }
1347
1348 static void
rt2860_tbtt_intr(struct rt2860_softc * sc)1349 rt2860_tbtt_intr(struct rt2860_softc *sc)
1350 {
1351 #if 0
1352 struct ieee80211com *ic = &sc->sc_ic;
1353
1354 #ifndef IEEE80211_STA_ONLY
1355 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1356 /* one less beacon until next DTIM */
1357 if (ic->ic_dtim_count == 0)
1358 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1359 else
1360 ic->ic_dtim_count--;
1361
1362 /* update dynamic parts of beacon */
1363 rt2860_setup_beacon(sc);
1364
1365 /* flush buffered multicast frames */
1366 if (ic->ic_dtim_count == 0)
1367 ieee80211_notify_dtim(ic);
1368 }
1369 #endif
1370 /* check if protection mode has changed */
1371 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1372 rt2860_updateprot(sc);
1373 sc->sc_ic_flags = ic->ic_flags;
1374 }
1375 #endif
1376 }
1377
1378 static void
rt2860_gp_intr(struct rt2860_softc * sc)1379 rt2860_gp_intr(struct rt2860_softc *sc)
1380 {
1381 struct ieee80211com *ic = &sc->sc_ic;
1382 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1383
1384 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state));
1385
1386 if (vap->iv_state == IEEE80211_S_RUN)
1387 rt2860_updatestats(sc);
1388 }
1389
1390 void
rt2860_intr(void * arg)1391 rt2860_intr(void *arg)
1392 {
1393 struct rt2860_softc *sc = arg;
1394 uint32_t r;
1395
1396 RAL_LOCK(sc);
1397
1398 r = RAL_READ(sc, RT2860_INT_STATUS);
1399 if (__predict_false(r == 0xffffffff)) {
1400 RAL_UNLOCK(sc);
1401 return; /* device likely went away */
1402 }
1403 if (r == 0) {
1404 RAL_UNLOCK(sc);
1405 return; /* not for us */
1406 }
1407
1408 /* acknowledge interrupts */
1409 RAL_WRITE(sc, RT2860_INT_STATUS, r);
1410
1411 if (r & RT2860_TX_RX_COHERENT)
1412 rt2860_intr_coherent(sc);
1413
1414 if (r & RT2860_MAC_INT_2) /* TX status */
1415 rt2860_drain_stats_fifo(sc);
1416
1417 if (r & RT2860_TX_DONE_INT5)
1418 rt2860_tx_intr(sc, 5);
1419
1420 if (r & RT2860_RX_DONE_INT)
1421 rt2860_rx_intr(sc);
1422
1423 if (r & RT2860_TX_DONE_INT4)
1424 rt2860_tx_intr(sc, 4);
1425
1426 if (r & RT2860_TX_DONE_INT3)
1427 rt2860_tx_intr(sc, 3);
1428
1429 if (r & RT2860_TX_DONE_INT2)
1430 rt2860_tx_intr(sc, 2);
1431
1432 if (r & RT2860_TX_DONE_INT1)
1433 rt2860_tx_intr(sc, 1);
1434
1435 if (r & RT2860_TX_DONE_INT0)
1436 rt2860_tx_intr(sc, 0);
1437
1438 if (r & RT2860_MAC_INT_0) /* TBTT */
1439 rt2860_tbtt_intr(sc);
1440
1441 if (r & RT2860_MAC_INT_3) /* Auto wakeup */
1442 /* TBD wakeup */;
1443
1444 if (r & RT2860_MAC_INT_4) /* GP timer */
1445 rt2860_gp_intr(sc);
1446
1447 RAL_UNLOCK(sc);
1448 }
1449
1450 static int
rt2860_tx(struct rt2860_softc * sc,struct mbuf * m,struct ieee80211_node * ni)1451 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1452 {
1453 struct ieee80211com *ic = &sc->sc_ic;
1454 struct ieee80211vap *vap = ni->ni_vap;
1455 struct rt2860_tx_ring *ring;
1456 struct rt2860_tx_data *data;
1457 struct rt2860_txd *txd;
1458 struct rt2860_txwi *txwi;
1459 struct ieee80211_frame *wh;
1460 const struct ieee80211_txparam *tp;
1461 struct ieee80211_key *k;
1462 struct mbuf *m1;
1463 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1464 bus_dma_segment_t *seg;
1465 u_int hdrlen;
1466 uint16_t qos, dur;
1467 uint8_t type, qsel, mcs, pid, tid, qid;
1468 int i, nsegs, ntxds, pad, rate, ridx, error;
1469
1470 /* the data pool contains at least one element, pick the first */
1471 data = SLIST_FIRST(&sc->data_pool);
1472
1473 wh = mtod(m, struct ieee80211_frame *);
1474
1475 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1476 k = ieee80211_crypto_encap(ni, m);
1477 if (k == NULL) {
1478 m_freem(m);
1479 return ENOBUFS;
1480 }
1481
1482 /* packet header may have moved, reset our local pointer */
1483 wh = mtod(m, struct ieee80211_frame *);
1484 }
1485
1486 hdrlen = ieee80211_anyhdrsize(wh);
1487 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1488
1489 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1490 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1491 rate = tp->mcastrate;
1492 } else if (m->m_flags & M_EAPOL) {
1493 rate = tp->mgmtrate;
1494 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1495 rate = tp->ucastrate;
1496 } else {
1497 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1498 rate = ni->ni_txrate;
1499 }
1500 rate &= IEEE80211_RATE_VAL;
1501
1502 qid = M_WME_GETAC(m);
1503 if (IEEE80211_QOS_HAS_SEQ(wh)) {
1504 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1505 tid = qos & IEEE80211_QOS_TID;
1506 } else {
1507 qos = 0;
1508 tid = 0;
1509 }
1510 ring = &sc->txq[qid];
1511 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate);
1512
1513 /* get MCS code from rate index */
1514 mcs = rt2860_rates[ridx].mcs;
1515
1516 /* setup TX Wireless Information */
1517 txwi = data->txwi;
1518 txwi->flags = 0;
1519 /* let HW generate seq numbers for non-QoS frames */
1520 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ;
1521 if (type == IEEE80211_FC0_TYPE_DATA)
1522 txwi->wcid = IEEE80211_AID(ni->ni_associd);
1523 else
1524 txwi->wcid = 0xff;
1525 txwi->len = htole16(m->m_pkthdr.len);
1526 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1527 txwi->phy = htole16(RT2860_PHY_CCK);
1528 if (ridx != RT2860_RIDX_CCK1 &&
1529 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1530 mcs |= RT2860_PHY_SHPRE;
1531 } else
1532 txwi->phy = htole16(RT2860_PHY_OFDM);
1533 txwi->phy |= htole16(mcs);
1534
1535 /*
1536 * We store the MCS code into the driver-private PacketID field.
1537 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1538 * that we know at which initial rate the frame was transmitted.
1539 * We add 1 to the MCS code because setting the PacketID field to
1540 * 0 means that we don't want feedback in TX_STAT_FIFO.
1541 */
1542 pid = (mcs + 1) & 0xf;
1543 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1544
1545 /* check if RTS/CTS or CTS-to-self protection is required */
1546 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1547 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold ||
1548 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1549 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1550 txwi->txop = RT2860_TX_TXOP_HT;
1551 else
1552 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1553
1554 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1555 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
1556 IEEE80211_QOS_ACKPOLICY_NOACK)) {
1557 txwi->xflags |= RT2860_TX_ACK;
1558
1559 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1560 dur = rt2860_rates[ridx].sp_ack_dur;
1561 else
1562 dur = rt2860_rates[ridx].lp_ack_dur;
1563 *(uint16_t *)wh->i_dur = htole16(dur);
1564 }
1565 /* ask MAC to insert timestamp into probe responses */
1566 if ((wh->i_fc[0] &
1567 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1568 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1569 /* NOTE: beacons do not pass through tx_data() */
1570 txwi->flags |= RT2860_TX_TS;
1571
1572 if (ieee80211_radiotap_active_vap(vap)) {
1573 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1574
1575 tap->wt_flags = 0;
1576 tap->wt_rate = rate;
1577 if (mcs & RT2860_PHY_SHPRE)
1578 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1579
1580 ieee80211_radiotap_tx(vap, m);
1581 }
1582
1583 pad = (hdrlen + 3) & ~3;
1584
1585 /* copy and trim 802.11 header */
1586 memcpy(txwi + 1, wh, hdrlen);
1587 m_adj(m, hdrlen);
1588
1589 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1590 &nsegs, 0);
1591 if (__predict_false(error != 0 && error != EFBIG)) {
1592 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1593 error);
1594 m_freem(m);
1595 return error;
1596 }
1597 if (__predict_true(error == 0)) {
1598 /* determine how many TXDs are required */
1599 ntxds = 1 + (nsegs / 2);
1600
1601 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1602 /* not enough free TXDs, force mbuf defrag */
1603 bus_dmamap_unload(sc->txwi_dmat, data->map);
1604 error = EFBIG;
1605 }
1606 }
1607 if (__predict_false(error != 0)) {
1608 m1 = m_defrag(m, M_NOWAIT);
1609 if (m1 == NULL) {
1610 device_printf(sc->sc_dev,
1611 "could not defragment mbuf\n");
1612 m_freem(m);
1613 return ENOBUFS;
1614 }
1615 m = m1;
1616
1617 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1618 segs, &nsegs, 0);
1619 if (__predict_false(error != 0)) {
1620 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1621 error);
1622 m_freem(m);
1623 return error;
1624 }
1625
1626 /* determine how many TXDs are now required */
1627 ntxds = 1 + (nsegs / 2);
1628
1629 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1630 /* this is a hopeless case, drop the mbuf! */
1631 bus_dmamap_unload(sc->txwi_dmat, data->map);
1632 m_freem(m);
1633 return ENOBUFS;
1634 }
1635 }
1636
1637 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1638
1639 /* first segment is TXWI + 802.11 header */
1640 txd = &ring->txd[ring->cur];
1641 txd->sdp0 = htole32(data->paddr);
1642 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1643 txd->flags = qsel;
1644
1645 /* setup payload segments */
1646 seg = &segs[0];
1647 for (i = nsegs; i >= 2; i -= 2) {
1648 txd->sdp1 = htole32(seg->ds_addr);
1649 txd->sdl1 = htole16(seg->ds_len);
1650 seg++;
1651 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1652 /* grab a new Tx descriptor */
1653 txd = &ring->txd[ring->cur];
1654 txd->sdp0 = htole32(seg->ds_addr);
1655 txd->sdl0 = htole16(seg->ds_len);
1656 txd->flags = qsel;
1657 seg++;
1658 }
1659 /* finalize last segment */
1660 if (i > 0) {
1661 txd->sdp1 = htole32(seg->ds_addr);
1662 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1663 } else {
1664 txd->sdl0 |= htole16(RT2860_TX_LS0);
1665 txd->sdl1 = 0;
1666 }
1667
1668 /* remove from the free pool and link it into the SW Tx slot */
1669 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1670 data->m = m;
1671 data->ni = ni;
1672 ring->data[ring->cur] = data;
1673
1674 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1675 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1676 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1677
1678 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1679 qid, txwi->wcid, nsegs, ridx));
1680
1681 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1682 ring->queued += ntxds;
1683 if (ring->queued >= RT2860_TX_RING_COUNT)
1684 sc->qfullmsk |= 1 << qid;
1685
1686 /* kick Tx */
1687 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1688
1689 return 0;
1690 }
1691
1692 static int
rt2860_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1693 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1694 const struct ieee80211_bpf_params *params)
1695 {
1696 struct ieee80211com *ic = ni->ni_ic;
1697 struct rt2860_softc *sc = ic->ic_softc;
1698 int error;
1699
1700 RAL_LOCK(sc);
1701
1702 /* prevent management frames from being sent if we're not ready */
1703 if (!(sc->sc_flags & RT2860_RUNNING)) {
1704 RAL_UNLOCK(sc);
1705 m_freem(m);
1706 return ENETDOWN;
1707 }
1708 if (params == NULL) {
1709 /*
1710 * Legacy path; interpret frame contents to decide
1711 * precisely how to send the frame.
1712 */
1713 error = rt2860_tx(sc, m, ni);
1714 } else {
1715 /*
1716 * Caller supplied explicit parameters to use in
1717 * sending the frame.
1718 */
1719 error = rt2860_tx_raw(sc, m, ni, params);
1720 }
1721 sc->sc_tx_timer = 5;
1722 RAL_UNLOCK(sc);
1723 return error;
1724 }
1725
1726 static int
rt2860_tx_raw(struct rt2860_softc * sc,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)1727 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m,
1728 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
1729 {
1730 struct ieee80211com *ic = &sc->sc_ic;
1731 struct ieee80211vap *vap = ni->ni_vap;
1732 struct rt2860_tx_ring *ring;
1733 struct rt2860_tx_data *data;
1734 struct rt2860_txd *txd;
1735 struct rt2860_txwi *txwi;
1736 struct ieee80211_frame *wh;
1737 struct mbuf *m1;
1738 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1739 bus_dma_segment_t *seg;
1740 u_int hdrlen;
1741 uint16_t dur;
1742 uint8_t type, qsel, mcs, pid, tid, qid;
1743 int i, nsegs, ntxds, pad, rate, ridx, error;
1744
1745 /* the data pool contains at least one element, pick the first */
1746 data = SLIST_FIRST(&sc->data_pool);
1747
1748 wh = mtod(m, struct ieee80211_frame *);
1749 hdrlen = ieee80211_hdrsize(wh);
1750 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1751
1752 /* Choose a TX rate index. */
1753 rate = params->ibp_rate0;
1754 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
1755 rate & IEEE80211_RATE_VAL);
1756 if (ridx == (uint8_t)-1) {
1757 /* XXX fall back to mcast/mgmt rate? */
1758 m_freem(m);
1759 return EINVAL;
1760 }
1761
1762 qid = params->ibp_pri & 3;
1763 tid = 0;
1764 ring = &sc->txq[qid];
1765
1766 /* get MCS code from rate index */
1767 mcs = rt2860_rates[ridx].mcs;
1768
1769 /* setup TX Wireless Information */
1770 txwi = data->txwi;
1771 txwi->flags = 0;
1772 /* let HW generate seq numbers for non-QoS frames */
1773 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ;
1774 txwi->wcid = 0xff;
1775 txwi->len = htole16(m->m_pkthdr.len);
1776 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1777 txwi->phy = htole16(RT2860_PHY_CCK);
1778 if (ridx != RT2860_RIDX_CCK1 &&
1779 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1780 mcs |= RT2860_PHY_SHPRE;
1781 } else
1782 txwi->phy = htole16(RT2860_PHY_OFDM);
1783 txwi->phy |= htole16(mcs);
1784
1785 /*
1786 * We store the MCS code into the driver-private PacketID field.
1787 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1788 * that we know at which initial rate the frame was transmitted.
1789 * We add 1 to the MCS code because setting the PacketID field to
1790 * 0 means that we don't want feedback in TX_STAT_FIFO.
1791 */
1792 pid = (mcs + 1) & 0xf;
1793 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1794
1795 /* check if RTS/CTS or CTS-to-self protection is required */
1796 if (params->ibp_flags & IEEE80211_BPF_RTS ||
1797 params->ibp_flags & IEEE80211_BPF_CTS)
1798 txwi->txop = RT2860_TX_TXOP_HT;
1799 else
1800 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1801 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
1802 txwi->xflags |= RT2860_TX_ACK;
1803
1804 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1805 dur = rt2860_rates[ridx].sp_ack_dur;
1806 else
1807 dur = rt2860_rates[ridx].lp_ack_dur;
1808 *(uint16_t *)wh->i_dur = htole16(dur);
1809 }
1810 /* ask MAC to insert timestamp into probe responses */
1811 if ((wh->i_fc[0] &
1812 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1813 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1814 /* NOTE: beacons do not pass through tx_data() */
1815 txwi->flags |= RT2860_TX_TS;
1816
1817 if (ieee80211_radiotap_active_vap(vap)) {
1818 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1819
1820 tap->wt_flags = 0;
1821 tap->wt_rate = rate;
1822 if (mcs & RT2860_PHY_SHPRE)
1823 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1824
1825 ieee80211_radiotap_tx(vap, m);
1826 }
1827
1828 pad = (hdrlen + 3) & ~3;
1829
1830 /* copy and trim 802.11 header */
1831 memcpy(txwi + 1, wh, hdrlen);
1832 m_adj(m, hdrlen);
1833
1834 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1835 &nsegs, 0);
1836 if (__predict_false(error != 0 && error != EFBIG)) {
1837 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1838 error);
1839 m_freem(m);
1840 return error;
1841 }
1842 if (__predict_true(error == 0)) {
1843 /* determine how many TXDs are required */
1844 ntxds = 1 + (nsegs / 2);
1845
1846 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1847 /* not enough free TXDs, force mbuf defrag */
1848 bus_dmamap_unload(sc->txwi_dmat, data->map);
1849 error = EFBIG;
1850 }
1851 }
1852 if (__predict_false(error != 0)) {
1853 m1 = m_defrag(m, M_NOWAIT);
1854 if (m1 == NULL) {
1855 device_printf(sc->sc_dev,
1856 "could not defragment mbuf\n");
1857 m_freem(m);
1858 return ENOBUFS;
1859 }
1860 m = m1;
1861
1862 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1863 segs, &nsegs, 0);
1864 if (__predict_false(error != 0)) {
1865 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1866 error);
1867 m_freem(m);
1868 return error;
1869 }
1870
1871 /* determine how many TXDs are now required */
1872 ntxds = 1 + (nsegs / 2);
1873
1874 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1875 /* this is a hopeless case, drop the mbuf! */
1876 bus_dmamap_unload(sc->txwi_dmat, data->map);
1877 m_freem(m);
1878 return ENOBUFS;
1879 }
1880 }
1881
1882 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1883
1884 /* first segment is TXWI + 802.11 header */
1885 txd = &ring->txd[ring->cur];
1886 txd->sdp0 = htole32(data->paddr);
1887 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1888 txd->flags = qsel;
1889
1890 /* setup payload segments */
1891 seg = &segs[0];
1892 for (i = nsegs; i >= 2; i -= 2) {
1893 txd->sdp1 = htole32(seg->ds_addr);
1894 txd->sdl1 = htole16(seg->ds_len);
1895 seg++;
1896 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1897 /* grab a new Tx descriptor */
1898 txd = &ring->txd[ring->cur];
1899 txd->sdp0 = htole32(seg->ds_addr);
1900 txd->sdl0 = htole16(seg->ds_len);
1901 txd->flags = qsel;
1902 seg++;
1903 }
1904 /* finalize last segment */
1905 if (i > 0) {
1906 txd->sdp1 = htole32(seg->ds_addr);
1907 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1908 } else {
1909 txd->sdl0 |= htole16(RT2860_TX_LS0);
1910 txd->sdl1 = 0;
1911 }
1912
1913 /* remove from the free pool and link it into the SW Tx slot */
1914 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1915 data->m = m;
1916 data->ni = ni;
1917 ring->data[ring->cur] = data;
1918
1919 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1920 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1921 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1922
1923 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1924 qid, txwi->wcid, nsegs, ridx));
1925
1926 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1927 ring->queued += ntxds;
1928 if (ring->queued >= RT2860_TX_RING_COUNT)
1929 sc->qfullmsk |= 1 << qid;
1930
1931 /* kick Tx */
1932 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1933
1934 return 0;
1935 }
1936
1937 static int
rt2860_transmit(struct ieee80211com * ic,struct mbuf * m)1938 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m)
1939 {
1940 struct rt2860_softc *sc = ic->ic_softc;
1941 int error;
1942
1943 RAL_LOCK(sc);
1944 if ((sc->sc_flags & RT2860_RUNNING) == 0) {
1945 RAL_UNLOCK(sc);
1946 return (ENXIO);
1947 }
1948 error = mbufq_enqueue(&sc->sc_snd, m);
1949 if (error) {
1950 RAL_UNLOCK(sc);
1951 return (error);
1952 }
1953 rt2860_start(sc);
1954 RAL_UNLOCK(sc);
1955
1956 return (0);
1957 }
1958
1959 static void
rt2860_start(struct rt2860_softc * sc)1960 rt2860_start(struct rt2860_softc *sc)
1961 {
1962 struct ieee80211_node *ni;
1963 struct mbuf *m;
1964
1965 RAL_LOCK_ASSERT(sc);
1966
1967 if ((sc->sc_flags & RT2860_RUNNING) == 0)
1968 return;
1969
1970 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 &&
1971 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1972 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1973 if (rt2860_tx(sc, m, ni) != 0) {
1974 if_inc_counter(ni->ni_vap->iv_ifp,
1975 IFCOUNTER_OERRORS, 1);
1976 ieee80211_free_node(ni);
1977 continue;
1978 }
1979 sc->sc_tx_timer = 5;
1980 }
1981 }
1982
1983 static void
rt2860_watchdog(void * arg)1984 rt2860_watchdog(void *arg)
1985 {
1986 struct rt2860_softc *sc = arg;
1987
1988 RAL_LOCK_ASSERT(sc);
1989
1990 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running"));
1991
1992 if (sc->sc_invalid) /* card ejected */
1993 return;
1994
1995 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1996 device_printf(sc->sc_dev, "device timeout\n");
1997 rt2860_stop_locked(sc);
1998 rt2860_init_locked(sc);
1999 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2000 return;
2001 }
2002 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
2003 }
2004
2005 static void
rt2860_parent(struct ieee80211com * ic)2006 rt2860_parent(struct ieee80211com *ic)
2007 {
2008 struct rt2860_softc *sc = ic->ic_softc;
2009 int startall = 0;
2010
2011 RAL_LOCK(sc);
2012 if (ic->ic_nrunning> 0) {
2013 if (!(sc->sc_flags & RT2860_RUNNING)) {
2014 rt2860_init_locked(sc);
2015 startall = 1;
2016 } else
2017 rt2860_update_promisc(ic);
2018 } else if (sc->sc_flags & RT2860_RUNNING)
2019 rt2860_stop_locked(sc);
2020 RAL_UNLOCK(sc);
2021 if (startall)
2022 ieee80211_start_all(ic);
2023 }
2024
2025 /*
2026 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2027 * We access the BBP through the 8051 microcontroller unit which means that
2028 * the microcode must be loaded first.
2029 */
2030 void
rt2860_mcu_bbp_write(struct rt2860_softc * sc,uint8_t reg,uint8_t val)2031 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2032 {
2033 int ntries;
2034
2035 for (ntries = 0; ntries < 100; ntries++) {
2036 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2037 break;
2038 DELAY(1);
2039 }
2040 if (ntries == 100) {
2041 device_printf(sc->sc_dev,
2042 "could not write to BBP through MCU\n");
2043 return;
2044 }
2045
2046 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2047 RT2860_BBP_CSR_KICK | reg << 8 | val);
2048 RAL_BARRIER_WRITE(sc);
2049
2050 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2051 DELAY(1000);
2052 }
2053
2054 uint8_t
rt2860_mcu_bbp_read(struct rt2860_softc * sc,uint8_t reg)2055 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2056 {
2057 uint32_t val;
2058 int ntries;
2059
2060 for (ntries = 0; ntries < 100; ntries++) {
2061 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2062 break;
2063 DELAY(1);
2064 }
2065 if (ntries == 100) {
2066 device_printf(sc->sc_dev,
2067 "could not read from BBP through MCU\n");
2068 return 0;
2069 }
2070
2071 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2072 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2073 RAL_BARRIER_WRITE(sc);
2074
2075 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2076 DELAY(1000);
2077
2078 for (ntries = 0; ntries < 100; ntries++) {
2079 val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
2080 if (!(val & RT2860_BBP_CSR_KICK))
2081 return val & 0xff;
2082 DELAY(1);
2083 }
2084 device_printf(sc->sc_dev, "could not read from BBP through MCU\n");
2085
2086 return 0;
2087 }
2088
2089 /*
2090 * Write to one of the 4 programmable 24-bit RF registers.
2091 */
2092 static void
rt2860_rf_write(struct rt2860_softc * sc,uint8_t reg,uint32_t val)2093 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2094 {
2095 uint32_t tmp;
2096 int ntries;
2097
2098 for (ntries = 0; ntries < 100; ntries++) {
2099 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2100 break;
2101 DELAY(1);
2102 }
2103 if (ntries == 100) {
2104 device_printf(sc->sc_dev, "could not write to RF\n");
2105 return;
2106 }
2107
2108 /* RF registers are 24-bit on the RT2860 */
2109 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2110 (val & 0x3fffff) << 2 | (reg & 3);
2111 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2112 }
2113
2114 static uint8_t
rt3090_rf_read(struct rt2860_softc * sc,uint8_t reg)2115 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
2116 {
2117 uint32_t tmp;
2118 int ntries;
2119
2120 for (ntries = 0; ntries < 100; ntries++) {
2121 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2122 break;
2123 DELAY(1);
2124 }
2125 if (ntries == 100) {
2126 device_printf(sc->sc_dev, "could not read RF register\n");
2127 return 0xff;
2128 }
2129 tmp = RT3070_RF_KICK | reg << 8;
2130 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2131
2132 for (ntries = 0; ntries < 100; ntries++) {
2133 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
2134 if (!(tmp & RT3070_RF_KICK))
2135 break;
2136 DELAY(1);
2137 }
2138 if (ntries == 100) {
2139 device_printf(sc->sc_dev, "could not read RF register\n");
2140 return 0xff;
2141 }
2142 return tmp & 0xff;
2143 }
2144
2145 void
rt3090_rf_write(struct rt2860_softc * sc,uint8_t reg,uint8_t val)2146 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2147 {
2148 uint32_t tmp;
2149 int ntries;
2150
2151 for (ntries = 0; ntries < 10; ntries++) {
2152 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2153 break;
2154 DELAY(10);
2155 }
2156 if (ntries == 10) {
2157 device_printf(sc->sc_dev, "could not write to RF\n");
2158 return;
2159 }
2160
2161 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
2162 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2163 }
2164
2165 /*
2166 * Send a command to the 8051 microcontroller unit.
2167 */
2168 int
rt2860_mcu_cmd(struct rt2860_softc * sc,uint8_t cmd,uint16_t arg,int wait)2169 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2170 {
2171 int slot, ntries;
2172 uint32_t tmp;
2173 uint8_t cid;
2174
2175 for (ntries = 0; ntries < 100; ntries++) {
2176 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2177 break;
2178 DELAY(2);
2179 }
2180 if (ntries == 100)
2181 return EIO;
2182
2183 cid = wait ? cmd : RT2860_TOKEN_NO_INTR;
2184 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg);
2185 RAL_BARRIER_WRITE(sc);
2186 RAL_WRITE(sc, RT2860_HOST_CMD, cmd);
2187
2188 if (!wait)
2189 return 0;
2190 /* wait for the command to complete */
2191 for (ntries = 0; ntries < 200; ntries++) {
2192 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
2193 /* find the command slot */
2194 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2195 if ((tmp & 0xff) == cid)
2196 break;
2197 if (slot < 4)
2198 break;
2199 DELAY(100);
2200 }
2201 if (ntries == 200) {
2202 /* clear command and status */
2203 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2204 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2205 return ETIMEDOUT;
2206 }
2207 /* get command status (1 means success) */
2208 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
2209 tmp = (tmp >> (slot * 8)) & 0xff;
2210 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2211 cmd, slot, tmp));
2212 /* clear command and status */
2213 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2214 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2215 return (tmp == 1) ? 0 : EIO;
2216 }
2217
2218 static void
rt2860_enable_mrr(struct rt2860_softc * sc)2219 rt2860_enable_mrr(struct rt2860_softc *sc)
2220 {
2221 #define CCK(mcs) (mcs)
2222 #define OFDM(mcs) (1 << 3 | (mcs))
2223 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,
2224 OFDM(6) << 28 | /* 54->48 */
2225 OFDM(5) << 24 | /* 48->36 */
2226 OFDM(4) << 20 | /* 36->24 */
2227 OFDM(3) << 16 | /* 24->18 */
2228 OFDM(2) << 12 | /* 18->12 */
2229 OFDM(1) << 8 | /* 12-> 9 */
2230 OFDM(0) << 4 | /* 9-> 6 */
2231 OFDM(0)); /* 6-> 6 */
2232
2233 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,
2234 CCK(2) << 12 | /* 11->5.5 */
2235 CCK(1) << 8 | /* 5.5-> 2 */
2236 CCK(0) << 4 | /* 2-> 1 */
2237 CCK(0)); /* 1-> 1 */
2238 #undef OFDM
2239 #undef CCK
2240 }
2241
2242 static void
rt2860_set_txpreamble(struct rt2860_softc * sc)2243 rt2860_set_txpreamble(struct rt2860_softc *sc)
2244 {
2245 struct ieee80211com *ic = &sc->sc_ic;
2246 uint32_t tmp;
2247
2248 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
2249 tmp &= ~RT2860_CCK_SHORT_EN;
2250 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2251 tmp |= RT2860_CCK_SHORT_EN;
2252 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
2253 }
2254
2255 void
rt2860_set_basicrates(struct rt2860_softc * sc,const struct ieee80211_rateset * rs)2256 rt2860_set_basicrates(struct rt2860_softc *sc,
2257 const struct ieee80211_rateset *rs)
2258 {
2259 struct ieee80211com *ic = &sc->sc_ic;
2260 uint32_t mask = 0;
2261 uint8_t rate;
2262 int i;
2263
2264 for (i = 0; i < rs->rs_nrates; i++) {
2265 rate = rs->rs_rates[i];
2266
2267 if (!(rate & IEEE80211_RATE_BASIC))
2268 continue;
2269
2270 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt,
2271 IEEE80211_RV(rate));
2272 }
2273
2274 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask);
2275 }
2276
2277 static void
rt2860_scan_start(struct ieee80211com * ic)2278 rt2860_scan_start(struct ieee80211com *ic)
2279 {
2280 struct rt2860_softc *sc = ic->ic_softc;
2281 uint32_t tmp;
2282
2283 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
2284 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
2285 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
2286 RT2860_TBTT_TIMER_EN));
2287 rt2860_set_gp_timer(sc, 0);
2288 }
2289
2290 static void
rt2860_scan_end(struct ieee80211com * ic)2291 rt2860_scan_end(struct ieee80211com *ic)
2292 {
2293 struct rt2860_softc *sc = ic->ic_softc;
2294 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2295
2296 if (vap->iv_state == IEEE80211_S_RUN) {
2297 rt2860_enable_tsf_sync(sc);
2298 rt2860_set_gp_timer(sc, 500);
2299 }
2300 }
2301
2302 static void
rt2860_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])2303 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans,
2304 struct ieee80211_channel chans[])
2305 {
2306 struct rt2860_softc *sc = ic->ic_softc;
2307 uint8_t bands[IEEE80211_MODE_BYTES];
2308
2309 memset(bands, 0, sizeof(bands));
2310 setbit(bands, IEEE80211_MODE_11B);
2311 setbit(bands, IEEE80211_MODE_11G);
2312 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
2313
2314 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) {
2315 setbit(bands, IEEE80211_MODE_11A);
2316 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans,
2317 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0);
2318 }
2319 }
2320
2321 static void
rt2860_set_channel(struct ieee80211com * ic)2322 rt2860_set_channel(struct ieee80211com *ic)
2323 {
2324 struct rt2860_softc *sc = ic->ic_softc;
2325
2326 RAL_LOCK(sc);
2327 rt2860_switch_chan(sc, ic->ic_curchan);
2328 RAL_UNLOCK(sc);
2329 }
2330
2331 static void
rt2860_select_chan_group(struct rt2860_softc * sc,int group)2332 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2333 {
2334 uint32_t tmp;
2335 uint8_t agc;
2336
2337 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2338 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2339 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2340 rt2860_mcu_bbp_write(sc, 86, 0x00);
2341
2342 if (group == 0) {
2343 if (sc->ext_2ghz_lna) {
2344 rt2860_mcu_bbp_write(sc, 82, 0x62);
2345 rt2860_mcu_bbp_write(sc, 75, 0x46);
2346 } else {
2347 rt2860_mcu_bbp_write(sc, 82, 0x84);
2348 rt2860_mcu_bbp_write(sc, 75, 0x50);
2349 }
2350 } else {
2351 if (sc->ext_5ghz_lna) {
2352 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2353 rt2860_mcu_bbp_write(sc, 75, 0x46);
2354 } else {
2355 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2356 rt2860_mcu_bbp_write(sc, 75, 0x50);
2357 }
2358 }
2359
2360 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
2361 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2362 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2363 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2364
2365 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2366 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
2367 if (sc->nrxchains > 1)
2368 tmp |= RT2860_LNA_PE1_EN;
2369 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2370 tmp |= RT3593_LNA_PE2_EN;
2371 if (group == 0) { /* 2GHz */
2372 tmp |= RT2860_PA_PE_G0_EN;
2373 if (sc->ntxchains > 1)
2374 tmp |= RT2860_PA_PE_G1_EN;
2375 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2376 tmp |= RT3593_PA_PE_G2_EN;
2377 } else { /* 5GHz */
2378 tmp |= RT2860_PA_PE_A0_EN;
2379 if (sc->ntxchains > 1)
2380 tmp |= RT2860_PA_PE_A1_EN;
2381 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2382 tmp |= RT3593_PA_PE_A2_EN;
2383 }
2384 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2385
2386 if (sc->mac_ver == 0x3593) {
2387 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
2388 if (sc->sc_flags & RT2860_PCIE) {
2389 tmp &= ~0x01010000;
2390 if (group == 0)
2391 tmp |= 0x00010000;
2392 } else {
2393 tmp &= ~0x00008080;
2394 if (group == 0)
2395 tmp |= 0x00000080;
2396 }
2397 tmp = (tmp & ~0x00001000) | 0x00000010;
2398 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
2399 }
2400
2401 /* set initial AGC value */
2402 if (group == 0) { /* 2GHz band */
2403 if (sc->mac_ver >= 0x3071)
2404 agc = 0x1c + sc->lna[0] * 2;
2405 else
2406 agc = 0x2e + sc->lna[0];
2407 } else { /* 5GHz band */
2408 agc = 0x32 + (sc->lna[group] * 5) / 3;
2409 }
2410 rt2860_mcu_bbp_write(sc, 66, agc);
2411
2412 DELAY(1000);
2413 }
2414
2415 static void
rt2860_set_chan(struct rt2860_softc * sc,u_int chan)2416 rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2417 {
2418 const struct rfprog *rfprog = rt2860_rf2850;
2419 uint32_t r2, r3, r4;
2420 int8_t txpow1, txpow2;
2421 u_int i;
2422
2423 /* find the settings for this channel (we know it exists) */
2424 for (i = 0; rfprog[i].chan != chan; i++);
2425
2426 r2 = rfprog[i].r2;
2427 if (sc->ntxchains == 1)
2428 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2429 if (sc->nrxchains == 1)
2430 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2431 else if (sc->nrxchains == 2)
2432 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2433
2434 /* use Tx power values from EEPROM */
2435 txpow1 = sc->txpow1[i];
2436 txpow2 = sc->txpow2[i];
2437 if (chan > 14) {
2438 if (txpow1 >= 0)
2439 txpow1 = txpow1 << 1 | 1;
2440 else
2441 txpow1 = (7 + txpow1) << 1;
2442 if (txpow2 >= 0)
2443 txpow2 = txpow2 << 1 | 1;
2444 else
2445 txpow2 = (7 + txpow2) << 1;
2446 }
2447 r3 = rfprog[i].r3 | txpow1 << 7;
2448 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2449
2450 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2451 rt2860_rf_write(sc, RT2860_RF2, r2);
2452 rt2860_rf_write(sc, RT2860_RF3, r3);
2453 rt2860_rf_write(sc, RT2860_RF4, r4);
2454
2455 DELAY(200);
2456
2457 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2458 rt2860_rf_write(sc, RT2860_RF2, r2);
2459 rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
2460 rt2860_rf_write(sc, RT2860_RF4, r4);
2461
2462 DELAY(200);
2463
2464 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2465 rt2860_rf_write(sc, RT2860_RF2, r2);
2466 rt2860_rf_write(sc, RT2860_RF3, r3);
2467 rt2860_rf_write(sc, RT2860_RF4, r4);
2468 }
2469
2470 static void
rt3090_set_chan(struct rt2860_softc * sc,u_int chan)2471 rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2472 {
2473 int8_t txpow1, txpow2;
2474 uint8_t rf;
2475 int i;
2476
2477 /* RT3090 is 2GHz only */
2478 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2479
2480 /* find the settings for this channel (we know it exists) */
2481 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2482
2483 /* use Tx power values from EEPROM */
2484 txpow1 = sc->txpow1[i];
2485 txpow2 = sc->txpow2[i];
2486
2487 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2488 rf = rt3090_rf_read(sc, 3);
2489 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2490 rt3090_rf_write(sc, 3, rf);
2491 rf = rt3090_rf_read(sc, 6);
2492 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2493 rt3090_rf_write(sc, 6, rf);
2494
2495 /* set Tx0 power */
2496 rf = rt3090_rf_read(sc, 12);
2497 rf = (rf & ~0x1f) | txpow1;
2498 rt3090_rf_write(sc, 12, rf);
2499
2500 /* set Tx1 power */
2501 rf = rt3090_rf_read(sc, 13);
2502 rf = (rf & ~0x1f) | txpow2;
2503 rt3090_rf_write(sc, 13, rf);
2504
2505 rf = rt3090_rf_read(sc, 1);
2506 rf &= ~0xfc;
2507 if (sc->ntxchains == 1)
2508 rf |= RT3070_TX1_PD | RT3070_TX2_PD;
2509 else if (sc->ntxchains == 2)
2510 rf |= RT3070_TX2_PD;
2511 if (sc->nrxchains == 1)
2512 rf |= RT3070_RX1_PD | RT3070_RX2_PD;
2513 else if (sc->nrxchains == 2)
2514 rf |= RT3070_RX2_PD;
2515 rt3090_rf_write(sc, 1, rf);
2516
2517 /* set RF offset */
2518 rf = rt3090_rf_read(sc, 23);
2519 rf = (rf & ~0x7f) | sc->freq;
2520 rt3090_rf_write(sc, 23, rf);
2521
2522 /* program RF filter */
2523 rf = rt3090_rf_read(sc, 24); /* Tx */
2524 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2525 rt3090_rf_write(sc, 24, rf);
2526 rf = rt3090_rf_read(sc, 31); /* Rx */
2527 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2528 rt3090_rf_write(sc, 31, rf);
2529
2530 /* enable RF tuning */
2531 rf = rt3090_rf_read(sc, 7);
2532 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2533 }
2534
2535 static void
rt5390_set_chan(struct rt2860_softc * sc,u_int chan)2536 rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2537 {
2538 uint8_t h20mhz, rf, tmp;
2539 int8_t txpow1, txpow2;
2540 int i;
2541
2542 /* RT5390 is 2GHz only */
2543 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2544
2545 /* find the settings for this channel (we know it exists) */
2546 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2547
2548 /* use Tx power values from EEPROM */
2549 txpow1 = sc->txpow1[i];
2550 txpow2 = sc->txpow2[i];
2551
2552 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2553 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2554 rf = rt3090_rf_read(sc, 11);
2555 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2556 rt3090_rf_write(sc, 11, rf);
2557
2558 rf = rt3090_rf_read(sc, 49);
2559 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2560 /* the valid range of the RF R49 is 0x00~0x27 */
2561 if ((rf & 0x3f) > 0x27)
2562 rf = (rf & ~0x3f) | 0x27;
2563 rt3090_rf_write(sc, 49, rf);
2564 if (sc->mac_ver == 0x5392) {
2565 rf = rt3090_rf_read(sc, 50);
2566 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2567 /* the valid range of the RF R50 is 0x00~0x27 */
2568 if ((rf & 0x3f) > 0x27)
2569 rf = (rf & ~0x3f) | 0x27;
2570 rt3090_rf_write(sc, 50, rf);
2571 }
2572
2573 rf = rt3090_rf_read(sc, 1);
2574 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
2575 if (sc->mac_ver == 0x5392)
2576 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2577 rt3090_rf_write(sc, 1, rf);
2578
2579 rf = rt3090_rf_read(sc, 2);
2580 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2581 DELAY(1000);
2582 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2583
2584 rf = rt3090_rf_read(sc, 17);
2585 tmp = rf;
2586 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2587 rf = MIN(rf, 0x5f);
2588 if (tmp != rf)
2589 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2590
2591 if (sc->mac_ver == 0x5390) {
2592 if (chan <= 4)
2593 rf = 0x73;
2594 else if (chan >= 5 && chan <= 6)
2595 rf = 0x63;
2596 else if (chan >= 7 && chan <= 10)
2597 rf = 0x53;
2598 else
2599 rf = 43;
2600 rt3090_rf_write(sc, 55, rf);
2601
2602 if (chan == 1)
2603 rf = 0x0c;
2604 else if (chan == 2)
2605 rf = 0x0b;
2606 else if (chan == 3)
2607 rf = 0x0a;
2608 else if (chan >= 4 && chan <= 6)
2609 rf = 0x09;
2610 else if (chan >= 7 && chan <= 12)
2611 rf = 0x08;
2612 else if (chan == 13)
2613 rf = 0x07;
2614 else
2615 rf = 0x06;
2616 rt3090_rf_write(sc, 59, rf);
2617 }
2618
2619 /* Tx/Rx h20M */
2620 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2621 rf = rt3090_rf_read(sc, 30);
2622 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2623 rt3090_rf_write(sc, 30, rf);
2624
2625 /* Rx BB filter VCM */
2626 rf = rt3090_rf_read(sc, 30);
2627 rf = (rf & ~0x18) | 0x10;
2628 rt3090_rf_write(sc, 30, rf);
2629
2630 /* Initiate VCO calibration. */
2631 rf = rt3090_rf_read(sc, 3);
2632 rf |= RT3593_VCOCAL;
2633 rt3090_rf_write(sc, 3, rf);
2634 }
2635
2636 static int
rt3090_rf_init(struct rt2860_softc * sc)2637 rt3090_rf_init(struct rt2860_softc *sc)
2638 {
2639 uint32_t tmp;
2640 uint8_t rf, bbp;
2641 int i;
2642
2643 rf = rt3090_rf_read(sc, 30);
2644 /* toggle RF R30 bit 7 */
2645 rt3090_rf_write(sc, 30, rf | 0x80);
2646 DELAY(1000);
2647 rt3090_rf_write(sc, 30, rf & ~0x80);
2648
2649 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2650 tmp &= ~0x1f000000;
2651 if (sc->patch_dac && sc->mac_rev < 0x0211)
2652 tmp |= 0x0d000000; /* 1.35V */
2653 else
2654 tmp |= 0x01000000; /* 1.2V */
2655 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2656
2657 /* patch LNA_PE_G1 */
2658 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
2659 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
2660
2661 /* initialize RF registers to default value */
2662 for (i = 0; i < nitems(rt3090_def_rf); i++) {
2663 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2664 rt3090_def_rf[i].val);
2665 }
2666
2667 /* select 20MHz bandwidth */
2668 rt3090_rf_write(sc, 31, 0x14);
2669
2670 rf = rt3090_rf_read(sc, 6);
2671 rt3090_rf_write(sc, 6, rf | 0x40);
2672
2673 if (sc->mac_ver != 0x3593) {
2674 /* calibrate filter for 20MHz bandwidth */
2675 sc->rf24_20mhz = 0x1f; /* default value */
2676 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2677
2678 /* select 40MHz bandwidth */
2679 bbp = rt2860_mcu_bbp_read(sc, 4);
2680 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2681 rf = rt3090_rf_read(sc, 31);
2682 rt3090_rf_write(sc, 31, rf | 0x20);
2683
2684 /* calibrate filter for 40MHz bandwidth */
2685 sc->rf24_40mhz = 0x2f; /* default value */
2686 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2687
2688 /* go back to 20MHz bandwidth */
2689 bbp = rt2860_mcu_bbp_read(sc, 4);
2690 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2691 }
2692 if (sc->mac_rev < 0x0211)
2693 rt3090_rf_write(sc, 27, 0x03);
2694
2695 tmp = RAL_READ(sc, RT3070_OPT_14);
2696 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
2697
2698 if (sc->rf_rev == RT3070_RF_3020)
2699 rt3090_set_rx_antenna(sc, 0);
2700
2701 bbp = rt2860_mcu_bbp_read(sc, 138);
2702 if (sc->mac_ver == 0x3593) {
2703 if (sc->ntxchains == 1)
2704 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2705 else if (sc->ntxchains == 2)
2706 bbp |= 0x40; /* turn off DAC2 */
2707 if (sc->nrxchains == 1)
2708 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2709 else if (sc->nrxchains == 2)
2710 bbp &= ~0x04; /* turn off ADC2 */
2711 } else {
2712 if (sc->ntxchains == 1)
2713 bbp |= 0x20; /* turn off DAC1 */
2714 if (sc->nrxchains == 1)
2715 bbp &= ~0x02; /* turn off ADC1 */
2716 }
2717 rt2860_mcu_bbp_write(sc, 138, bbp);
2718
2719 rf = rt3090_rf_read(sc, 1);
2720 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD);
2721 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD;
2722 rt3090_rf_write(sc, 1, rf);
2723
2724 rf = rt3090_rf_read(sc, 15);
2725 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2);
2726
2727 rf = rt3090_rf_read(sc, 17);
2728 rf &= ~RT3070_TX_LO1;
2729 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2730 rf |= 0x20; /* fix for long range Rx issue */
2731 if (sc->txmixgain_2ghz >= 2)
2732 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2733 rt3090_rf_write(sc, 17, rf);
2734
2735 rf = rt3090_rf_read(sc, 20);
2736 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1);
2737
2738 rf = rt3090_rf_read(sc, 21);
2739 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2);
2740
2741 return (0);
2742 }
2743
2744 static void
rt5390_rf_init(struct rt2860_softc * sc)2745 rt5390_rf_init(struct rt2860_softc *sc)
2746 {
2747 uint8_t rf, bbp;
2748 int i;
2749
2750 rf = rt3090_rf_read(sc, 2);
2751 /* Toggle RF R2 bit 7. */
2752 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2753 DELAY(1000);
2754 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2755
2756 /* Initialize RF registers to default value. */
2757 if (sc->mac_ver == 0x5392) {
2758 for (i = 0; i < nitems(rt5392_def_rf); i++) {
2759 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2760 rt5392_def_rf[i].val);
2761 }
2762 } else {
2763 for (i = 0; i < nitems(rt5390_def_rf); i++) {
2764 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2765 rt5390_def_rf[i].val);
2766 }
2767 }
2768
2769 sc->rf24_20mhz = 0x1f;
2770 sc->rf24_40mhz = 0x2f;
2771
2772 if (sc->mac_rev < 0x0211)
2773 rt3090_rf_write(sc, 27, 0x03);
2774
2775 /* Set led open drain enable. */
2776 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1);
2777
2778 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2779 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2780
2781 if (sc->mac_ver == 0x5390)
2782 rt3090_set_rx_antenna(sc, 0);
2783
2784 /* Patch RSSI inaccurate issue. */
2785 rt2860_mcu_bbp_write(sc, 79, 0x13);
2786 rt2860_mcu_bbp_write(sc, 80, 0x05);
2787 rt2860_mcu_bbp_write(sc, 81, 0x33);
2788
2789 /* Enable DC filter. */
2790 if (sc->mac_rev >= 0x0211)
2791 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2792
2793 bbp = rt2860_mcu_bbp_read(sc, 138);
2794 if (sc->ntxchains == 1)
2795 bbp |= 0x20; /* Turn off DAC1. */
2796 if (sc->nrxchains == 1)
2797 bbp &= ~0x02; /* Turn off ADC1. */
2798 rt2860_mcu_bbp_write(sc, 138, bbp);
2799
2800 /* Enable RX LO1 and LO2. */
2801 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1);
2802 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2);
2803
2804 /* Avoid data lost and CRC error. */
2805 rt2860_mcu_bbp_write(sc, 4,
2806 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL);
2807
2808 rf = rt3090_rf_read(sc, 30);
2809 rf = (rf & ~0x18) | 0x10;
2810 rt3090_rf_write(sc, 30, rf);
2811 }
2812
2813 static void
rt3090_rf_wakeup(struct rt2860_softc * sc)2814 rt3090_rf_wakeup(struct rt2860_softc *sc)
2815 {
2816 uint32_t tmp;
2817 uint8_t rf;
2818
2819 if (sc->mac_ver == 0x3593) {
2820 /* enable VCO */
2821 rf = rt3090_rf_read(sc, 1);
2822 rt3090_rf_write(sc, 1, rf | RT3593_VCO);
2823
2824 /* initiate VCO calibration */
2825 rf = rt3090_rf_read(sc, 3);
2826 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL);
2827
2828 /* enable VCO bias current control */
2829 rf = rt3090_rf_read(sc, 6);
2830 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC);
2831
2832 /* initiate res calibration */
2833 rf = rt3090_rf_read(sc, 2);
2834 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2835
2836 /* set reference current control to 0.33 mA */
2837 rf = rt3090_rf_read(sc, 22);
2838 rf &= ~RT3593_CP_IC_MASK;
2839 rf |= 1 << RT3593_CP_IC_SHIFT;
2840 rt3090_rf_write(sc, 22, rf);
2841
2842 /* enable RX CTB */
2843 rf = rt3090_rf_read(sc, 46);
2844 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB);
2845
2846 rf = rt3090_rf_read(sc, 20);
2847 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK);
2848 rt3090_rf_write(sc, 20, rf);
2849 } else {
2850 /* enable RF block */
2851 rf = rt3090_rf_read(sc, 1);
2852 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK);
2853
2854 /* enable VCO bias current control */
2855 rf = rt3090_rf_read(sc, 7);
2856 rt3090_rf_write(sc, 7, rf | 0x30);
2857
2858 rf = rt3090_rf_read(sc, 9);
2859 rt3090_rf_write(sc, 9, rf | 0x0e);
2860
2861 /* enable RX CTB */
2862 rf = rt3090_rf_read(sc, 21);
2863 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB);
2864
2865 /* fix Tx to Rx IQ glitch by raising RF voltage */
2866 rf = rt3090_rf_read(sc, 27);
2867 rf &= ~0x77;
2868 if (sc->mac_rev < 0x0211)
2869 rf |= 0x03;
2870 rt3090_rf_write(sc, 27, rf);
2871 }
2872 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2873 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2874 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2875 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2876 }
2877 }
2878
2879 static void
rt5390_rf_wakeup(struct rt2860_softc * sc)2880 rt5390_rf_wakeup(struct rt2860_softc *sc)
2881 {
2882 uint32_t tmp;
2883 uint8_t rf;
2884
2885 rf = rt3090_rf_read(sc, 1);
2886 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
2887 RT3070_TX0_PD;
2888 if (sc->mac_ver == 0x5392)
2889 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2890 rt3090_rf_write(sc, 1, rf);
2891
2892 rf = rt3090_rf_read(sc, 6);
2893 rf |= RT3593_VCO_IC | RT3593_VCOCAL;
2894 if (sc->mac_ver == 0x5390)
2895 rf &= ~RT3593_VCO_IC;
2896 rt3090_rf_write(sc, 6, rf);
2897
2898 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL);
2899
2900 rf = rt3090_rf_read(sc, 22);
2901 rf = (rf & ~0xe0) | 0x20;
2902 rt3090_rf_write(sc, 22, rf);
2903
2904 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB);
2905 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2906 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL);
2907
2908 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2909 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2910 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2911 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2912 }
2913 }
2914
2915 static int
rt3090_filter_calib(struct rt2860_softc * sc,uint8_t init,uint8_t target,uint8_t * val)2916 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2917 uint8_t *val)
2918 {
2919 uint8_t rf22, rf24;
2920 uint8_t bbp55_pb, bbp55_sb, delta;
2921 int ntries;
2922
2923 /* program filter */
2924 rf24 = rt3090_rf_read(sc, 24);
2925 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2926 rt3090_rf_write(sc, 24, rf24);
2927
2928 /* enable baseband loopback mode */
2929 rf22 = rt3090_rf_read(sc, 22);
2930 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK);
2931
2932 /* set power and frequency of passband test tone */
2933 rt2860_mcu_bbp_write(sc, 24, 0x00);
2934 for (ntries = 0; ntries < 100; ntries++) {
2935 /* transmit test tone */
2936 rt2860_mcu_bbp_write(sc, 25, 0x90);
2937 DELAY(1000);
2938 /* read received power */
2939 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
2940 if (bbp55_pb != 0)
2941 break;
2942 }
2943 if (ntries == 100)
2944 return (ETIMEDOUT);
2945
2946 /* set power and frequency of stopband test tone */
2947 rt2860_mcu_bbp_write(sc, 24, 0x06);
2948 for (ntries = 0; ntries < 100; ntries++) {
2949 /* transmit test tone */
2950 rt2860_mcu_bbp_write(sc, 25, 0x90);
2951 DELAY(1000);
2952 /* read received power */
2953 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
2954
2955 delta = bbp55_pb - bbp55_sb;
2956 if (delta > target)
2957 break;
2958
2959 /* reprogram filter */
2960 rf24++;
2961 rt3090_rf_write(sc, 24, rf24);
2962 }
2963 if (ntries < 100) {
2964 if (rf24 != init)
2965 rf24--; /* backtrack */
2966 *val = rf24;
2967 rt3090_rf_write(sc, 24, rf24);
2968 }
2969
2970 /* restore initial state */
2971 rt2860_mcu_bbp_write(sc, 24, 0x00);
2972
2973 /* disable baseband loopback mode */
2974 rf22 = rt3090_rf_read(sc, 22);
2975 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK);
2976
2977 return (0);
2978 }
2979
2980 static void
rt3090_rf_setup(struct rt2860_softc * sc)2981 rt3090_rf_setup(struct rt2860_softc *sc)
2982 {
2983 uint8_t bbp;
2984 int i;
2985
2986 if (sc->mac_rev >= 0x0211) {
2987 /* enable DC filter */
2988 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2989
2990 /* improve power consumption */
2991 bbp = rt2860_mcu_bbp_read(sc, 31);
2992 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
2993 }
2994
2995 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2996 if (sc->mac_rev < 0x0211) {
2997 RAL_WRITE(sc, RT2860_TX_SW_CFG2,
2998 sc->patch_dac ? 0x2c : 0x0f);
2999 } else
3000 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
3001
3002 /* initialize RF registers from ROM */
3003 if (sc->mac_ver < 0x5390) {
3004 for (i = 0; i < 10; i++) {
3005 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
3006 continue;
3007 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
3008 }
3009 }
3010 }
3011
3012 static void
rt2860_set_leds(struct rt2860_softc * sc,uint16_t which)3013 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
3014 {
3015 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
3016 which | (sc->leds & 0x7f), 0);
3017 }
3018
3019 /*
3020 * Hardware has a general-purpose programmable timer interrupt that can
3021 * periodically raise MAC_INT_4.
3022 */
3023 static void
rt2860_set_gp_timer(struct rt2860_softc * sc,int ms)3024 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
3025 {
3026 uint32_t tmp;
3027
3028 /* disable GP timer before reprogramming it */
3029 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3030 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
3031
3032 if (ms == 0)
3033 return;
3034
3035 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
3036 ms *= 16; /* Unit: 64us */
3037 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
3038 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
3039
3040 /* enable GP timer */
3041 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3042 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
3043 }
3044
3045 static void
rt2860_set_bssid(struct rt2860_softc * sc,const uint8_t * bssid)3046 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
3047 {
3048 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,
3049 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
3050 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,
3051 bssid[4] | bssid[5] << 8);
3052 }
3053
3054 static void
rt2860_set_macaddr(struct rt2860_softc * sc,const uint8_t * addr)3055 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
3056 {
3057 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,
3058 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3059 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,
3060 addr[4] | addr[5] << 8 | 0xff << 16);
3061 }
3062
3063 static void
rt2860_updateslot(struct ieee80211com * ic)3064 rt2860_updateslot(struct ieee80211com *ic)
3065 {
3066 struct rt2860_softc *sc = ic->ic_softc;
3067 uint32_t tmp;
3068
3069 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
3070 tmp &= ~0xff;
3071 tmp |= IEEE80211_GET_SLOTTIME(ic);
3072 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
3073 }
3074
3075 static void
rt2860_updateprot(struct rt2860_softc * sc)3076 rt2860_updateprot(struct rt2860_softc *sc)
3077 {
3078 struct ieee80211com *ic = &sc->sc_ic;
3079 uint32_t tmp;
3080
3081 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
3082 /* setup protection frame rate (MCS code) */
3083 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
3084 rt2860_rates[RT2860_RIDX_OFDM6].mcs :
3085 rt2860_rates[RT2860_RIDX_CCK11].mcs;
3086
3087 /* CCK frames don't require protection */
3088 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
3089
3090 if (ic->ic_flags & IEEE80211_F_USEPROT) {
3091 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3092 tmp |= RT2860_PROT_CTRL_RTS_CTS;
3093 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3094 tmp |= RT2860_PROT_CTRL_CTS;
3095 }
3096 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
3097 }
3098
3099 static void
rt2860_update_promisc(struct ieee80211com * ic)3100 rt2860_update_promisc(struct ieee80211com *ic)
3101 {
3102 struct rt2860_softc *sc = ic->ic_softc;
3103 uint32_t tmp;
3104
3105 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG);
3106 tmp &= ~RT2860_DROP_NOT_MYBSS;
3107 if (ic->ic_promisc == 0)
3108 tmp |= RT2860_DROP_NOT_MYBSS;
3109 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3110 }
3111
3112 static int
rt2860_updateedca(struct ieee80211com * ic)3113 rt2860_updateedca(struct ieee80211com *ic)
3114 {
3115 struct rt2860_softc *sc = ic->ic_softc;
3116 const struct wmeParams *wmep;
3117 int aci;
3118
3119 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
3120
3121 /* update MAC TX configuration registers */
3122 for (aci = 0; aci < WME_NUM_AC; aci++) {
3123 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
3124 wmep[aci].wmep_logcwmax << 16 |
3125 wmep[aci].wmep_logcwmin << 12 |
3126 wmep[aci].wmep_aifsn << 8 |
3127 wmep[aci].wmep_txopLimit);
3128 }
3129
3130 /* update SCH/DMA registers too */
3131 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
3132 wmep[WME_AC_VO].wmep_aifsn << 12 |
3133 wmep[WME_AC_VI].wmep_aifsn << 8 |
3134 wmep[WME_AC_BK].wmep_aifsn << 4 |
3135 wmep[WME_AC_BE].wmep_aifsn);
3136 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
3137 wmep[WME_AC_VO].wmep_logcwmin << 12 |
3138 wmep[WME_AC_VI].wmep_logcwmin << 8 |
3139 wmep[WME_AC_BK].wmep_logcwmin << 4 |
3140 wmep[WME_AC_BE].wmep_logcwmin);
3141 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
3142 wmep[WME_AC_VO].wmep_logcwmax << 12 |
3143 wmep[WME_AC_VI].wmep_logcwmax << 8 |
3144 wmep[WME_AC_BK].wmep_logcwmax << 4 |
3145 wmep[WME_AC_BE].wmep_logcwmax);
3146 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
3147 wmep[WME_AC_BK].wmep_txopLimit << 16 |
3148 wmep[WME_AC_BE].wmep_txopLimit);
3149 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
3150 wmep[WME_AC_VO].wmep_txopLimit << 16 |
3151 wmep[WME_AC_VI].wmep_txopLimit);
3152
3153 return 0;
3154 }
3155
3156 #ifdef HW_CRYPTO
3157 static int
rt2860_set_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)3158 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3159 struct ieee80211_key *k)
3160 {
3161 struct rt2860_softc *sc = ic->ic_softc;
3162 bus_size_t base;
3163 uint32_t attr;
3164 uint8_t mode, wcid, iv[8];
3165
3166 /* defer setting of WEP keys until interface is brought up */
3167 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
3168 (IFF_UP | IFF_RUNNING))
3169 return 0;
3170
3171 /* map net80211 cipher to RT2860 security mode */
3172 switch (k->k_cipher) {
3173 case IEEE80211_CIPHER_WEP40:
3174 mode = RT2860_MODE_WEP40;
3175 break;
3176 case IEEE80211_CIPHER_WEP104:
3177 mode = RT2860_MODE_WEP104;
3178 break;
3179 case IEEE80211_CIPHER_TKIP:
3180 mode = RT2860_MODE_TKIP;
3181 break;
3182 case IEEE80211_CIPHER_CCMP:
3183 mode = RT2860_MODE_AES_CCMP;
3184 break;
3185 default:
3186 return EINVAL;
3187 }
3188
3189 if (k->k_flags & IEEE80211_KEY_GROUP) {
3190 wcid = 0; /* NB: update WCID0 for group keys */
3191 base = RT2860_SKEY(0, k->k_id);
3192 } else {
3193 wcid = ((struct rt2860_node *)ni)->wcid;
3194 base = RT2860_PKEY(wcid);
3195 }
3196
3197 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3198 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3199 #ifndef IEEE80211_STA_ONLY
3200 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3201 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3202 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3203 } else
3204 #endif
3205 {
3206 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3207 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3208 }
3209 } else
3210 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3211
3212 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3213 (k->k_flags & IEEE80211_KEY_TX)) {
3214 /* set initial packet number in IV+EIV */
3215 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3216 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3217 uint32_t val = arc4random();
3218 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3219 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3220 val += 0x000100;
3221 iv[0] = val;
3222 iv[1] = val >> 8;
3223 iv[2] = val >> 16;
3224 iv[3] = k->k_id << 6;
3225 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3226 } else {
3227 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3228 iv[0] = k->k_tsc >> 8;
3229 iv[1] = (iv[0] | 0x20) & 0x7f;
3230 iv[2] = k->k_tsc;
3231 } else /* CCMP */ {
3232 iv[0] = k->k_tsc;
3233 iv[1] = k->k_tsc >> 8;
3234 iv[2] = 0;
3235 }
3236 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3237 iv[4] = k->k_tsc >> 16;
3238 iv[5] = k->k_tsc >> 24;
3239 iv[6] = k->k_tsc >> 32;
3240 iv[7] = k->k_tsc >> 40;
3241 }
3242 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8);
3243 }
3244
3245 if (k->k_flags & IEEE80211_KEY_GROUP) {
3246 /* install group key */
3247 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3248 attr &= ~(0xf << (k->k_id * 4));
3249 attr |= mode << (k->k_id * 4);
3250 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3251 } else {
3252 /* install pairwise key */
3253 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3254 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN;
3255 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3256 }
3257 return 0;
3258 }
3259
3260 static void
rt2860_delete_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)3261 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3262 struct ieee80211_key *k)
3263 {
3264 struct rt2860_softc *sc = ic->ic_softc;
3265 uint32_t attr;
3266 uint8_t wcid;
3267
3268 if (k->k_flags & IEEE80211_KEY_GROUP) {
3269 /* remove group key */
3270 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3271 attr &= ~(0xf << (k->k_id * 4));
3272 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3273
3274 } else {
3275 /* remove pairwise key */
3276 wcid = ((struct rt2860_node *)ni)->wcid;
3277 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3278 attr &= ~0xf;
3279 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3280 }
3281 }
3282 #endif
3283
3284 static int8_t
rt2860_rssi2dbm(struct rt2860_softc * sc,uint8_t rssi,uint8_t rxchain)3285 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3286 {
3287 struct ieee80211com *ic = &sc->sc_ic;
3288 struct ieee80211_channel *c = ic->ic_curchan;
3289 int delta;
3290
3291 if (IEEE80211_IS_CHAN_5GHZ(c)) {
3292 u_int chan = ieee80211_chan2ieee(ic, c);
3293 delta = sc->rssi_5ghz[rxchain];
3294
3295 /* determine channel group */
3296 if (chan <= 64)
3297 delta -= sc->lna[1];
3298 else if (chan <= 128)
3299 delta -= sc->lna[2];
3300 else
3301 delta -= sc->lna[3];
3302 } else
3303 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3304
3305 return -12 - delta - rssi;
3306 }
3307
3308 /*
3309 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3310 * Used to adjust per-rate Tx power registers.
3311 */
3312 static __inline uint32_t
b4inc(uint32_t b32,int8_t delta)3313 b4inc(uint32_t b32, int8_t delta)
3314 {
3315 int8_t i, b4;
3316
3317 for (i = 0; i < 8; i++) {
3318 b4 = b32 & 0xf;
3319 b4 += delta;
3320 if (b4 < 0)
3321 b4 = 0;
3322 else if (b4 > 0xf)
3323 b4 = 0xf;
3324 b32 = b32 >> 4 | b4 << 28;
3325 }
3326 return b32;
3327 }
3328
3329 static const char *
rt2860_get_rf(uint16_t rev)3330 rt2860_get_rf(uint16_t rev)
3331 {
3332 switch (rev) {
3333 case RT2860_RF_2820: return "RT2820";
3334 case RT2860_RF_2850: return "RT2850";
3335 case RT2860_RF_2720: return "RT2720";
3336 case RT2860_RF_2750: return "RT2750";
3337 case RT3070_RF_3020: return "RT3020";
3338 case RT3070_RF_2020: return "RT2020";
3339 case RT3070_RF_3021: return "RT3021";
3340 case RT3070_RF_3022: return "RT3022";
3341 case RT3070_RF_3052: return "RT3052";
3342 case RT3070_RF_3320: return "RT3320";
3343 case RT3070_RF_3053: return "RT3053";
3344 case RT5390_RF_5360: return "RT5360";
3345 case RT5390_RF_5390: return "RT5390";
3346 default: return "unknown";
3347 }
3348 }
3349
3350 static int
rt2860_read_eeprom(struct rt2860_softc * sc,uint8_t macaddr[IEEE80211_ADDR_LEN])3351 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
3352 {
3353 int8_t delta_2ghz, delta_5ghz;
3354 uint32_t tmp;
3355 uint16_t val;
3356 int ridx, ant, i;
3357
3358 /* check whether the ROM is eFUSE ROM or EEPROM */
3359 sc->sc_srom_read = rt2860_eeprom_read_2;
3360 if (sc->mac_ver >= 0x3071) {
3361 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
3362 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3363 if (tmp & RT3070_SEL_EFUSE)
3364 sc->sc_srom_read = rt3090_efuse_read_2;
3365 }
3366
3367 #ifdef RAL_DEBUG
3368 /* read EEPROM version */
3369 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
3370 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff));
3371 #endif
3372
3373 /* read MAC address */
3374 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
3375 macaddr[0] = val & 0xff;
3376 macaddr[1] = val >> 8;
3377 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
3378 macaddr[2] = val & 0xff;
3379 macaddr[3] = val >> 8;
3380 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
3381 macaddr[4] = val & 0xff;
3382 macaddr[5] = val >> 8;
3383
3384 #ifdef RAL_DEBUG
3385 /* read country code */
3386 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
3387 DPRINTF(("EEPROM region code=0x%04x\n", val));
3388 #endif
3389
3390 /* read vendor BBP settings */
3391 for (i = 0; i < 8; i++) {
3392 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
3393 sc->bbp[i].val = val & 0xff;
3394 sc->bbp[i].reg = val >> 8;
3395 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3396 }
3397 if (sc->mac_ver >= 0x3071) {
3398 /* read vendor RF settings */
3399 for (i = 0; i < 10; i++) {
3400 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
3401 sc->rf[i].val = val & 0xff;
3402 sc->rf[i].reg = val >> 8;
3403 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3404 sc->rf[i].val));
3405 }
3406 }
3407
3408 /* read RF frequency offset from EEPROM */
3409 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
3410 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3411 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3412 if ((val >> 8) != 0xff) {
3413 /* read LEDs operating mode */
3414 sc->leds = val >> 8;
3415 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3416 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3417 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3418 } else {
3419 /* broken EEPROM, use default settings */
3420 sc->leds = 0x01;
3421 sc->led[0] = 0x5555;
3422 sc->led[1] = 0x2221;
3423 sc->led[2] = 0xa9f8;
3424 }
3425 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3426 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3427
3428 /* read RF information */
3429 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
3430 if (sc->mac_ver >= 0x5390)
3431 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID);
3432 else
3433 sc->rf_rev = (val >> 8) & 0xf;
3434 sc->ntxchains = (val >> 4) & 0xf;
3435 sc->nrxchains = val & 0xf;
3436 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3437 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3438
3439 /* check if RF supports automatic Tx access gain control */
3440 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
3441 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3442 /* check if driver should patch the DAC issue */
3443 if ((val >> 8) != 0xff)
3444 sc->patch_dac = (val >> 15) & 1;
3445 if ((val & 0xff) != 0xff) {
3446 sc->ext_5ghz_lna = (val >> 3) & 1;
3447 sc->ext_2ghz_lna = (val >> 2) & 1;
3448 /* check if RF supports automatic Tx access gain control */
3449 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */
3450 /* check if we have a hardware radio switch */
3451 sc->rfswitch = val & 1;
3452 }
3453 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3454 /* read PCIe power save level */
3455 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
3456 if ((val & 0xff) != 0xff) {
3457 sc->pslevel = val & 0x3;
3458 val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
3459 if ((val & 0xff80) != 0x9280)
3460 sc->pslevel = MIN(sc->pslevel, 1);
3461 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3462 }
3463 }
3464
3465 /* read power settings for 2GHz channels */
3466 for (i = 0; i < 14; i += 2) {
3467 val = rt2860_srom_read(sc,
3468 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
3469 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3470 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3471
3472 if (sc->mac_ver != 0x5390) {
3473 val = rt2860_srom_read(sc,
3474 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
3475 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3476 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3477 }
3478 }
3479 /* fix broken Tx power entries */
3480 for (i = 0; i < 14; i++) {
3481 if (sc->txpow1[i] < 0 ||
3482 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3483 sc->txpow1[i] = 5;
3484 if (sc->mac_ver != 0x5390) {
3485 if (sc->txpow2[i] < 0 ||
3486 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3487 sc->txpow2[i] = 5;
3488 }
3489 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3490 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3491 }
3492 /* read power settings for 5GHz channels */
3493 for (i = 0; i < 40; i += 2) {
3494 val = rt2860_srom_read(sc,
3495 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
3496 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3497 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3498
3499 val = rt2860_srom_read(sc,
3500 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
3501 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3502 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3503 }
3504 /* fix broken Tx power entries */
3505 for (i = 0; i < 40; i++) {
3506 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3507 sc->txpow1[14 + i] = 5;
3508 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3509 sc->txpow2[14 + i] = 5;
3510 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3511 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3512 sc->txpow2[14 + i]));
3513 }
3514
3515 /* read Tx power compensation for each Tx rate */
3516 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
3517 delta_2ghz = delta_5ghz = 0;
3518 if ((val & 0xff) != 0xff && (val & 0x80)) {
3519 delta_2ghz = val & 0xf;
3520 if (!(val & 0x40)) /* negative number */
3521 delta_2ghz = -delta_2ghz;
3522 }
3523 val >>= 8;
3524 if ((val & 0xff) != 0xff && (val & 0x80)) {
3525 delta_5ghz = val & 0xf;
3526 if (!(val & 0x40)) /* negative number */
3527 delta_5ghz = -delta_5ghz;
3528 }
3529 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3530 delta_2ghz, delta_5ghz));
3531
3532 for (ridx = 0; ridx < 5; ridx++) {
3533 uint32_t reg;
3534
3535 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
3536 reg = val;
3537 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
3538 reg |= (uint32_t)val << 16;
3539
3540 sc->txpow20mhz[ridx] = reg;
3541 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3542 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3543
3544 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3545 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3546 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3547 }
3548
3549 /* read factory-calibrated samples for temperature compensation */
3550 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
3551 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3552 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3553 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
3554 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3555 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3556 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
3557 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3558 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3559 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
3560 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3561 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3562 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
3563 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3564 sc->step_2ghz = val >> 8;
3565 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3566 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3567 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3568 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3569 sc->tssi_2ghz[8], sc->step_2ghz));
3570 /* check that ref value is correct, otherwise disable calibration */
3571 if (sc->tssi_2ghz[4] == 0xff)
3572 sc->calib_2ghz = 0;
3573
3574 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
3575 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3576 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3577 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
3578 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3579 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3580 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
3581 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3582 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3583 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
3584 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3585 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3586 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
3587 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3588 sc->step_5ghz = val >> 8;
3589 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3590 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3591 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3592 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3593 sc->tssi_5ghz[8], sc->step_5ghz));
3594 /* check that ref value is correct, otherwise disable calibration */
3595 if (sc->tssi_5ghz[4] == 0xff)
3596 sc->calib_5ghz = 0;
3597
3598 /* read RSSI offsets and LNA gains from EEPROM */
3599 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
3600 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3601 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3602 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
3603 if (sc->mac_ver >= 0x3071) {
3604 /*
3605 * On RT3090 chips (limited to 2 Rx chains), this ROM
3606 * field contains the Tx mixer gain for the 2GHz band.
3607 */
3608 if ((val & 0xff) != 0xff)
3609 sc->txmixgain_2ghz = val & 0x7;
3610 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3611 } else
3612 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3613 sc->lna[2] = val >> 8; /* channel group 2 */
3614
3615 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
3616 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3617 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3618 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
3619 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3620 sc->lna[3] = val >> 8; /* channel group 3 */
3621
3622 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
3623 if (sc->mac_ver >= 0x3071)
3624 sc->lna[0] = RT3090_DEF_LNA;
3625 else /* channel group 0 */
3626 sc->lna[0] = val & 0xff;
3627 sc->lna[1] = val >> 8; /* channel group 1 */
3628
3629 /* fix broken 5GHz LNA entries */
3630 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3631 DPRINTF(("invalid LNA for channel group %d\n", 2));
3632 sc->lna[2] = sc->lna[1];
3633 }
3634 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3635 DPRINTF(("invalid LNA for channel group %d\n", 3));
3636 sc->lna[3] = sc->lna[1];
3637 }
3638
3639 /* fix broken RSSI offset entries */
3640 for (ant = 0; ant < 3; ant++) {
3641 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3642 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3643 ant + 1, sc->rssi_2ghz[ant]));
3644 sc->rssi_2ghz[ant] = 0;
3645 }
3646 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3647 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3648 ant + 1, sc->rssi_5ghz[ant]));
3649 sc->rssi_5ghz[ant] = 0;
3650 }
3651 }
3652
3653 return 0;
3654 }
3655
3656 static int
rt2860_bbp_init(struct rt2860_softc * sc)3657 rt2860_bbp_init(struct rt2860_softc *sc)
3658 {
3659 int i, ntries;
3660
3661 /* wait for BBP to wake up */
3662 for (ntries = 0; ntries < 20; ntries++) {
3663 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3664 if (bbp0 != 0 && bbp0 != 0xff)
3665 break;
3666 }
3667 if (ntries == 20) {
3668 device_printf(sc->sc_dev,
3669 "timeout waiting for BBP to wake up\n");
3670 return (ETIMEDOUT);
3671 }
3672
3673 /* initialize BBP registers to default values */
3674 if (sc->mac_ver >= 0x5390)
3675 rt5390_bbp_init(sc);
3676 else {
3677 for (i = 0; i < nitems(rt2860_def_bbp); i++) {
3678 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3679 rt2860_def_bbp[i].val);
3680 }
3681 }
3682
3683 /* fix BBP84 for RT2860E */
3684 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3685 rt2860_mcu_bbp_write(sc, 84, 0x19);
3686
3687 if (sc->mac_ver >= 0x3071) {
3688 rt2860_mcu_bbp_write(sc, 79, 0x13);
3689 rt2860_mcu_bbp_write(sc, 80, 0x05);
3690 rt2860_mcu_bbp_write(sc, 81, 0x33);
3691 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3692 rt2860_mcu_bbp_write(sc, 69, 0x16);
3693 rt2860_mcu_bbp_write(sc, 73, 0x12);
3694 }
3695
3696 return 0;
3697 }
3698
3699 static void
rt5390_bbp_init(struct rt2860_softc * sc)3700 rt5390_bbp_init(struct rt2860_softc *sc)
3701 {
3702 uint8_t bbp;
3703 int i;
3704
3705 /* Apply maximum likelihood detection for 2 stream case. */
3706 if (sc->nrxchains > 1) {
3707 bbp = rt2860_mcu_bbp_read(sc, 105);
3708 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD);
3709 }
3710
3711 /* Avoid data lost and CRC error. */
3712 bbp = rt2860_mcu_bbp_read(sc, 4);
3713 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
3714
3715 for (i = 0; i < nitems(rt5390_def_bbp); i++) {
3716 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3717 rt5390_def_bbp[i].val);
3718 }
3719
3720 if (sc->mac_ver == 0x5392) {
3721 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3722 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3723 rt2860_mcu_bbp_write(sc, 98, 0x12);
3724 rt2860_mcu_bbp_write(sc, 106, 0x05);
3725 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3726 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3727 }
3728
3729 bbp = rt2860_mcu_bbp_read(sc, 152);
3730 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3731
3732 /* Disable hardware antenna diversity. */
3733 if (sc->mac_ver == 0x5390)
3734 rt2860_mcu_bbp_write(sc, 154, 0);
3735 }
3736
3737 static int
rt2860_txrx_enable(struct rt2860_softc * sc)3738 rt2860_txrx_enable(struct rt2860_softc *sc)
3739 {
3740 struct ieee80211com *ic = &sc->sc_ic;
3741 uint32_t tmp;
3742 int ntries;
3743
3744 /* enable Tx/Rx DMA engine */
3745 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
3746 RAL_BARRIER_READ_WRITE(sc);
3747 for (ntries = 0; ntries < 200; ntries++) {
3748 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3749 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3750 break;
3751 DELAY(1000);
3752 }
3753 if (ntries == 200) {
3754 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3755 return ETIMEDOUT;
3756 }
3757
3758 DELAY(50);
3759
3760 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
3761 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
3762 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3763
3764 /* set Rx filter */
3765 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
3766 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3767 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
3768 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
3769 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
3770 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
3771 if (ic->ic_opmode == IEEE80211_M_STA)
3772 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
3773 }
3774 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3775
3776 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
3777 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3778
3779 return 0;
3780 }
3781
3782 static void
rt2860_init(void * arg)3783 rt2860_init(void *arg)
3784 {
3785 struct rt2860_softc *sc = arg;
3786 struct ieee80211com *ic = &sc->sc_ic;
3787
3788 RAL_LOCK(sc);
3789 rt2860_init_locked(sc);
3790 RAL_UNLOCK(sc);
3791
3792 if (sc->sc_flags & RT2860_RUNNING)
3793 ieee80211_start_all(ic);
3794 }
3795
3796 static void
rt2860_init_locked(struct rt2860_softc * sc)3797 rt2860_init_locked(struct rt2860_softc *sc)
3798 {
3799 struct ieee80211com *ic = &sc->sc_ic;
3800 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3801 uint32_t tmp;
3802 uint8_t bbp1, bbp3;
3803 int i, qid, ridx, ntries, error;
3804
3805 RAL_LOCK_ASSERT(sc);
3806
3807 if (sc->rfswitch) {
3808 /* hardware has a radio switch on GPIO pin 2 */
3809 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) {
3810 device_printf(sc->sc_dev,
3811 "radio is disabled by hardware switch\n");
3812 #ifdef notyet
3813 rt2860_stop_locked(sc);
3814 return;
3815 #endif
3816 }
3817 }
3818 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE);
3819
3820 /* disable DMA */
3821 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3822 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
3823 RT2860_TX_DMA_EN);
3824 tmp |= RT2860_TX_WB_DDONE;
3825 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3826
3827 /* reset DMA indexes */
3828 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 |
3829 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 |
3830 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0);
3831
3832 /* PBF hardware reset */
3833 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3834 RAL_BARRIER_WRITE(sc);
3835 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3836
3837 if ((error = rt2860_load_microcode(sc)) != 0) {
3838 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
3839 rt2860_stop_locked(sc);
3840 return;
3841 }
3842
3843 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
3844
3845 /* init Tx power for all Tx rates (from EEPROM) */
3846 for (ridx = 0; ridx < 5; ridx++) {
3847 if (sc->txpow20mhz[ridx] == 0xffffffff)
3848 continue;
3849 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3850 }
3851
3852 for (ntries = 0; ntries < 100; ntries++) {
3853 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3854 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3855 break;
3856 DELAY(1000);
3857 }
3858 if (ntries == 100) {
3859 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3860 rt2860_stop_locked(sc);
3861 return;
3862 }
3863 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
3864 RT2860_TX_DMA_EN);
3865 tmp |= RT2860_TX_WB_DDONE;
3866 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3867
3868 /* reset Rx ring and all 6 Tx rings */
3869 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
3870
3871 /* PBF hardware reset */
3872 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3873 RAL_BARRIER_WRITE(sc);
3874 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3875
3876 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE);
3877
3878 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3879 RAL_BARRIER_WRITE(sc);
3880 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3881
3882 for (i = 0; i < nitems(rt2860_def_mac); i++)
3883 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
3884 if (sc->mac_ver >= 0x5390)
3885 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404);
3886 else if (sc->mac_ver >= 0x3071) {
3887 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3888 RAL_WRITE(sc, RT2860_TX_SW_CFG0,
3889 4 << RT2860_DLY_PAPE_EN_SHIFT);
3890 }
3891
3892 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) {
3893 sc->sc_flags |= RT2860_PCIE;
3894 /* PCIe has different clock cycle count than PCI */
3895 tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
3896 tmp = (tmp & ~0xff) | 0x7d;
3897 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
3898 }
3899
3900 /* wait while MAC is busy */
3901 for (ntries = 0; ntries < 100; ntries++) {
3902 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) &
3903 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
3904 break;
3905 DELAY(1000);
3906 }
3907 if (ntries == 100) {
3908 device_printf(sc->sc_dev, "timeout waiting for MAC\n");
3909 rt2860_stop_locked(sc);
3910 return;
3911 }
3912
3913 /* clear Host to MCU mailbox */
3914 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
3915 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
3916
3917 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3918 DELAY(1000);
3919
3920 if ((error = rt2860_bbp_init(sc)) != 0) {
3921 rt2860_stop_locked(sc);
3922 return;
3923 }
3924
3925 /* clear RX WCID search table */
3926 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
3927 /* clear pairwise key table */
3928 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048);
3929 /* clear IV/EIV table */
3930 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512);
3931 /* clear WCID attribute table */
3932 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256);
3933 /* clear shared key table */
3934 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
3935 /* clear shared key mode */
3936 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
3937
3938 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
3939 for (qid = 0; qid < 6; qid++) {
3940 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
3941 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
3942 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
3943 }
3944
3945 /* init Rx ring */
3946 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
3947 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
3948 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
3949
3950 /* setup maximum buffer sizes */
3951 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
3952 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
3953
3954 for (ntries = 0; ntries < 100; ntries++) {
3955 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3956 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3957 break;
3958 DELAY(1000);
3959 }
3960 if (ntries == 100) {
3961 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3962 rt2860_stop_locked(sc);
3963 return;
3964 }
3965 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
3966 RT2860_TX_DMA_EN);
3967 tmp |= RT2860_TX_WB_DDONE;
3968 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3969
3970 /* disable interrupts mitigation */
3971 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
3972
3973 /* write vendor-specific BBP values (from EEPROM) */
3974 for (i = 0; i < 8; i++) {
3975 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
3976 continue;
3977 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
3978 }
3979
3980 /* select Main antenna for 1T1R devices */
3981 if (sc->rf_rev == RT3070_RF_2020 ||
3982 sc->rf_rev == RT3070_RF_3020 ||
3983 sc->rf_rev == RT3070_RF_3320 ||
3984 sc->mac_ver == 0x5390)
3985 rt3090_set_rx_antenna(sc, 0);
3986
3987 /* send LEDs operating mode to microcontroller */
3988 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
3989 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
3990 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
3991
3992 if (sc->mac_ver >= 0x5390)
3993 rt5390_rf_init(sc);
3994 else if (sc->mac_ver >= 0x3071) {
3995 if ((error = rt3090_rf_init(sc)) != 0) {
3996 rt2860_stop_locked(sc);
3997 return;
3998 }
3999 }
4000
4001 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1);
4002 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1);
4003
4004 if (sc->mac_ver >= 0x5390)
4005 rt5390_rf_wakeup(sc);
4006 else if (sc->mac_ver >= 0x3071)
4007 rt3090_rf_wakeup(sc);
4008
4009 /* disable non-existing Rx chains */
4010 bbp3 = rt2860_mcu_bbp_read(sc, 3);
4011 bbp3 &= ~(1 << 3 | 1 << 4);
4012 if (sc->nrxchains == 2)
4013 bbp3 |= 1 << 3;
4014 else if (sc->nrxchains == 3)
4015 bbp3 |= 1 << 4;
4016 rt2860_mcu_bbp_write(sc, 3, bbp3);
4017
4018 /* disable non-existing Tx chains */
4019 bbp1 = rt2860_mcu_bbp_read(sc, 1);
4020 if (sc->ntxchains == 1)
4021 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
4022 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
4023 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
4024 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
4025 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
4026 rt2860_mcu_bbp_write(sc, 1, bbp1);
4027
4028 if (sc->mac_ver >= 0x3071)
4029 rt3090_rf_setup(sc);
4030
4031 /* select default channel */
4032 rt2860_switch_chan(sc, ic->ic_curchan);
4033
4034 /* reset RF from MCU */
4035 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
4036
4037 /* set RTS threshold */
4038 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
4039 tmp &= ~0xffff00;
4040 tmp |= IEEE80211_RTS_DEFAULT << 8;
4041 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
4042
4043 /* setup initial protection mode */
4044 rt2860_updateprot(sc);
4045
4046 /* turn radio LED on */
4047 rt2860_set_leds(sc, RT2860_LED_RADIO);
4048
4049 /* enable Tx/Rx DMA engine */
4050 if ((error = rt2860_txrx_enable(sc)) != 0) {
4051 rt2860_stop_locked(sc);
4052 return;
4053 }
4054
4055 /* clear pending interrupts */
4056 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
4057 /* enable interrupts */
4058 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
4059
4060 if (sc->sc_flags & RT2860_ADVANCED_PS)
4061 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
4062
4063 sc->sc_flags |= RT2860_RUNNING;
4064
4065 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
4066 }
4067
4068 static void
rt2860_stop(void * arg)4069 rt2860_stop(void *arg)
4070 {
4071 struct rt2860_softc *sc = arg;
4072
4073 RAL_LOCK(sc);
4074 rt2860_stop_locked(sc);
4075 RAL_UNLOCK(sc);
4076 }
4077
4078 static void
rt2860_stop_locked(struct rt2860_softc * sc)4079 rt2860_stop_locked(struct rt2860_softc *sc)
4080 {
4081 uint32_t tmp;
4082 int qid;
4083
4084 if (sc->sc_flags & RT2860_RUNNING)
4085 rt2860_set_leds(sc, 0); /* turn all LEDs off */
4086
4087 callout_stop(&sc->watchdog_ch);
4088 sc->sc_tx_timer = 0;
4089 sc->sc_flags &= ~RT2860_RUNNING;
4090
4091 /* disable interrupts */
4092 RAL_WRITE(sc, RT2860_INT_MASK, 0);
4093
4094 /* disable GP timer */
4095 rt2860_set_gp_timer(sc, 0);
4096
4097 /* disable Rx */
4098 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
4099 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
4100 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
4101
4102 /* reset adapter */
4103 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
4104 RAL_BARRIER_WRITE(sc);
4105 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
4106
4107 /* reset Tx and Rx rings (and reclaim TXWIs) */
4108 sc->qfullmsk = 0;
4109 for (qid = 0; qid < 6; qid++)
4110 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
4111 rt2860_reset_rx_ring(sc, &sc->rxq);
4112 }
4113
4114 int
rt2860_load_microcode(struct rt2860_softc * sc)4115 rt2860_load_microcode(struct rt2860_softc *sc)
4116 {
4117 const struct firmware *fp;
4118 int ntries, error;
4119
4120 RAL_LOCK_ASSERT(sc);
4121
4122 RAL_UNLOCK(sc);
4123 fp = firmware_get("rt2860fw");
4124 RAL_LOCK(sc);
4125 if (fp == NULL) {
4126 device_printf(sc->sc_dev,
4127 "unable to receive rt2860fw firmware image\n");
4128 return EINVAL;
4129 }
4130
4131 /* set "host program ram write selection" bit */
4132 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
4133 /* write microcode image */
4134 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize);
4135 /* kick microcontroller unit */
4136 RAL_WRITE(sc, RT2860_SYS_CTRL, 0);
4137 RAL_BARRIER_WRITE(sc);
4138 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
4139
4140 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
4141 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
4142
4143 /* wait until microcontroller is ready */
4144 RAL_BARRIER_READ_WRITE(sc);
4145 for (ntries = 0; ntries < 1000; ntries++) {
4146 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
4147 break;
4148 DELAY(1000);
4149 }
4150 if (ntries == 1000) {
4151 device_printf(sc->sc_dev,
4152 "timeout waiting for MCU to initialize\n");
4153 error = ETIMEDOUT;
4154 } else
4155 error = 0;
4156
4157 firmware_put(fp, FIRMWARE_UNLOAD);
4158 return error;
4159 }
4160
4161 /*
4162 * This function is called periodically to adjust Tx power based on
4163 * temperature variation.
4164 */
4165 #ifdef NOT_YET
4166 static void
rt2860_calib(struct rt2860_softc * sc)4167 rt2860_calib(struct rt2860_softc *sc)
4168 {
4169 struct ieee80211com *ic = &sc->sc_ic;
4170 const uint8_t *tssi;
4171 uint8_t step, bbp49;
4172 int8_t ridx, d;
4173
4174 /* read current temperature */
4175 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4176
4177 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4178 tssi = &sc->tssi_2ghz[4];
4179 step = sc->step_2ghz;
4180 } else {
4181 tssi = &sc->tssi_5ghz[4];
4182 step = sc->step_5ghz;
4183 }
4184
4185 if (bbp49 < tssi[0]) { /* lower than reference */
4186 /* use higher Tx power than default */
4187 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4188 } else if (bbp49 > tssi[0]) { /* greater than reference */
4189 /* use lower Tx power than default */
4190 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++);
4191 } else {
4192 /* use default Tx power */
4193 d = 0;
4194 }
4195 d *= step;
4196
4197 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4198
4199 /* write adjusted Tx power values for each Tx rate */
4200 for (ridx = 0; ridx < 5; ridx++) {
4201 if (sc->txpow20mhz[ridx] == 0xffffffff)
4202 continue;
4203 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),
4204 b4inc(sc->txpow20mhz[ridx], d));
4205 }
4206 }
4207 #endif
4208
4209 static void
rt3090_set_rx_antenna(struct rt2860_softc * sc,int aux)4210 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4211 {
4212 uint32_t tmp;
4213
4214 if (aux) {
4215 if (sc->mac_ver == 0x5390) {
4216 rt2860_mcu_bbp_write(sc, 152,
4217 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4218 } else {
4219 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4220 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
4221 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4222 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
4223 }
4224 } else {
4225 if (sc->mac_ver == 0x5390) {
4226 rt2860_mcu_bbp_write(sc, 152,
4227 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4228 } else {
4229 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4230 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
4231 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4232 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
4233 }
4234 }
4235 }
4236
4237 static void
rt2860_switch_chan(struct rt2860_softc * sc,struct ieee80211_channel * c)4238 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4239 {
4240 struct ieee80211com *ic = &sc->sc_ic;
4241 u_int chan, group;
4242
4243 chan = ieee80211_chan2ieee(ic, c);
4244 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
4245 return;
4246
4247 if (sc->mac_ver >= 0x5390)
4248 rt5390_set_chan(sc, chan);
4249 else if (sc->mac_ver >= 0x3071)
4250 rt3090_set_chan(sc, chan);
4251 else
4252 rt2860_set_chan(sc, chan);
4253
4254 /* determine channel group */
4255 if (chan <= 14)
4256 group = 0;
4257 else if (chan <= 64)
4258 group = 1;
4259 else if (chan <= 128)
4260 group = 2;
4261 else
4262 group = 3;
4263
4264 /* XXX necessary only when group has changed! */
4265 if (sc->mac_ver < 0x5390)
4266 rt2860_select_chan_group(sc, group);
4267
4268 DELAY(1000);
4269 }
4270
4271 static int
rt2860_setup_beacon(struct rt2860_softc * sc,struct ieee80211vap * vap)4272 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap)
4273 {
4274 struct ieee80211com *ic = vap->iv_ic;
4275 struct rt2860_txwi txwi;
4276 struct mbuf *m;
4277 int ridx;
4278
4279 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL)
4280 return ENOBUFS;
4281
4282 memset(&txwi, 0, sizeof txwi);
4283 txwi.wcid = 0xff;
4284 txwi.len = htole16(m->m_pkthdr.len);
4285 /* send beacons at the lowest available rate */
4286 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ?
4287 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
4288 txwi.phy = htole16(rt2860_rates[ridx].mcs);
4289 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4290 txwi.phy |= htole16(RT2860_PHY_OFDM);
4291 txwi.txop = RT2860_TX_TXOP_HT;
4292 txwi.flags = RT2860_TX_TS;
4293 txwi.xflags = RT2860_TX_NSEQ;
4294
4295 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),
4296 (uint8_t *)&txwi, sizeof txwi);
4297 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,
4298 mtod(m, uint8_t *), m->m_pkthdr.len);
4299
4300 m_freem(m);
4301
4302 return 0;
4303 }
4304
4305 static void
rt2860_enable_tsf_sync(struct rt2860_softc * sc)4306 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4307 {
4308 struct ieee80211com *ic = &sc->sc_ic;
4309 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4310 uint32_t tmp;
4311
4312 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
4313
4314 tmp &= ~0x1fffff;
4315 tmp |= vap->iv_bss->ni_intval * 16;
4316 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
4317 if (vap->iv_opmode == IEEE80211_M_STA) {
4318 /*
4319 * Local TSF is always updated with remote TSF on beacon
4320 * reception.
4321 */
4322 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
4323 }
4324 else if (vap->iv_opmode == IEEE80211_M_IBSS ||
4325 vap->iv_opmode == IEEE80211_M_MBSS) {
4326 tmp |= RT2860_BCN_TX_EN;
4327 /*
4328 * Local TSF is updated with remote TSF on beacon reception
4329 * only if the remote TSF is greater than local TSF.
4330 */
4331 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
4332 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
4333 tmp |= RT2860_BCN_TX_EN;
4334 /* SYNC with nobody */
4335 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
4336 }
4337
4338 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
4339 }
4340