1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
2 /* $NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
3
4 /*
5 * Copyright (c) 2019 Internet Initiative Japan, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * Copyright(c) 2014 Intel Corporation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 *
36 * * Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * * Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in
40 * the documentation and/or other materials provided with the
41 * distribution.
42 * * Neither the name of Intel Corporation nor the names of its
43 * contributors may be used to endorse or promote products derived
44 * from this software without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <sys/cdefs.h>
60 #if 0
61 __KERNEL_RCSID(0, "$NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
62 #endif
63
64 #include <sys/param.h>
65 #include <sys/bus.h>
66 #include <sys/systm.h>
67
68 #include <machine/bus.h>
69
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
72
73 #include "qatreg.h"
74 #include "qat_hw17reg.h"
75 #include "qat_c62xreg.h"
76 #include "qatvar.h"
77 #include "qat_hw17var.h"
78
79 static uint32_t
qat_c62x_get_accel_mask(struct qat_softc * sc)80 qat_c62x_get_accel_mask(struct qat_softc *sc)
81 {
82 uint32_t fusectl, strap;
83
84 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
85 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
86
87 return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C62X) &
88 ACCEL_MASK_C62X);
89 }
90
91 static uint32_t
qat_c62x_get_ae_mask(struct qat_softc * sc)92 qat_c62x_get_ae_mask(struct qat_softc *sc)
93 {
94 uint32_t fusectl, me_strap, me_disable, ssms_disabled;
95
96 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
97 me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
98
99 /* If SSMs are disabled, then disable the corresponding MEs */
100 ssms_disabled = (~qat_c62x_get_accel_mask(sc)) & ACCEL_MASK_C62X;
101 me_disable = 0x3;
102 while (ssms_disabled) {
103 if (ssms_disabled & 1)
104 me_strap |= me_disable;
105 ssms_disabled >>= 1;
106 me_disable <<= 2;
107 }
108
109 return (~(fusectl | me_strap)) & AE_MASK_C62X;
110 }
111
112 static enum qat_sku
qat_c62x_get_sku(struct qat_softc * sc)113 qat_c62x_get_sku(struct qat_softc *sc)
114 {
115 switch (sc->sc_ae_num) {
116 case 8:
117 return QAT_SKU_2;
118 case MAX_AE_C62X:
119 return QAT_SKU_4;
120 }
121
122 return QAT_SKU_UNKNOWN;
123 }
124
125 static uint32_t
qat_c62x_get_accel_cap(struct qat_softc * sc)126 qat_c62x_get_accel_cap(struct qat_softc *sc)
127 {
128 uint32_t cap, legfuse, strap;
129
130 legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
131 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
132
133 cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
134 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
135 QAT_ACCEL_CAP_CIPHER +
136 QAT_ACCEL_CAP_AUTHENTICATION +
137 QAT_ACCEL_CAP_COMPRESSION +
138 QAT_ACCEL_CAP_ZUC +
139 QAT_ACCEL_CAP_SHA3;
140
141 if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
142 cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
143 cap &= ~QAT_ACCEL_CAP_CIPHER;
144 }
145 if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
146 cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
147 if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
148 cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
149 if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
150 cap &= ~QAT_ACCEL_CAP_COMPRESSION;
151 if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
152 cap &= ~QAT_ACCEL_CAP_ZUC;
153
154 if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C62X)
155 cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
156 if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C62X)
157 cap &= ~QAT_ACCEL_CAP_COMPRESSION;
158
159 return cap;
160 }
161
162 static const char *
qat_c62x_get_fw_uof_name(struct qat_softc * sc)163 qat_c62x_get_fw_uof_name(struct qat_softc *sc)
164 {
165
166 return AE_FW_UOF_NAME_C62X;
167 }
168
169 static void
qat_c62x_enable_intr(struct qat_softc * sc)170 qat_c62x_enable_intr(struct qat_softc *sc)
171 {
172
173 /* Enable bundle and misc interrupts */
174 qat_misc_write_4(sc, SMIAPF0_C62X, SMIA0_MASK_C62X);
175 qat_misc_write_4(sc, SMIAPF1_C62X, SMIA1_MASK_C62X);
176 }
177
178 /* Worker thread to service arbiter mappings */
179 static uint32_t thrd_to_arb_map[] = {
180 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
181 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
182 };
183
184 static void
qat_c62x_get_arb_mapping(struct qat_softc * sc,const uint32_t ** arb_map_config)185 qat_c62x_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
186 {
187 int i;
188
189 for (i = 1; i < MAX_AE_C62X; i++) {
190 if ((~sc->sc_ae_mask) & (1 << i))
191 thrd_to_arb_map[i] = 0;
192 }
193 *arb_map_config = thrd_to_arb_map;
194 }
195
196 static void
qat_c62x_enable_error_interrupts(struct qat_softc * sc)197 qat_c62x_enable_error_interrupts(struct qat_softc *sc)
198 {
199 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C62X); /* ME0-ME3 */
200 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C62X); /* ME4-ME7 */
201 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_C62X); /* ME8-ME9 */
202 qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C62X); /* SSM2-SSM4 */
203
204 /* Reset everything except VFtoPF1_16. */
205 qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C62X);
206 /* Disable Secure RAM correctable error interrupt */
207 qat_misc_read_write_or_4(sc, ERRMSK3, ERRMSK3_CERR_C62X);
208
209 /* RI CPP bus interface error detection and reporting. */
210 qat_misc_write_4(sc, RICPPINTCTL_C62X, RICPP_EN_C62X);
211
212 /* TI CPP bus interface error detection and reporting. */
213 qat_misc_write_4(sc, TICPPINTCTL_C62X, TICPP_EN_C62X);
214
215 /* Enable CFC Error interrupts and logging. */
216 qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C62X, CPP_CFC_UE_C62X);
217
218 /* Enable SecureRAM to fix and log Correctable errors */
219 qat_misc_write_4(sc, SECRAMCERR_C62X, SECRAM_CERR_C62X);
220
221 /* Enable SecureRAM Uncorrectable error interrupts and logging */
222 qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_C62X);
223
224 /* Enable Push/Pull Misc Uncorrectable error interrupts and logging */
225 qat_misc_write_4(sc, CPPMEMTGTERR, TGT_UERR_C62X);
226 }
227
228 static void
qat_c62x_disable_error_interrupts(struct qat_softc * sc)229 qat_c62x_disable_error_interrupts(struct qat_softc *sc)
230 {
231 /* ME0-ME3 */
232 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C62X | ERRMSK0_CERR_C62X);
233 /* ME4-ME7 */
234 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C62X | ERRMSK1_CERR_C62X);
235 /* Secure RAM, CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
236 qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C62X | ERRMSK3_CERR_C62X);
237 /* ME8-ME9 */
238 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_UERR_C62X | ERRMSK4_CERR_C62X);
239 /* SSM2-SSM4 */
240 qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C62X | ERRMSK5_CERR_C62X);
241 }
242
243 static void
qat_c62x_enable_error_correction(struct qat_softc * sc)244 qat_c62x_enable_error_correction(struct qat_softc *sc)
245 {
246 u_int i, mask;
247
248 /* Enable Accel Engine error detection & correction */
249 for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
250 if (!(mask & 1))
251 continue;
252 qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C62X(i),
253 ENABLE_AE_ECC_ERR_C62X);
254 qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C62X(i),
255 ENABLE_AE_ECC_PARITY_CORR_C62X);
256 }
257
258 /* Enable shared memory error detection & correction */
259 for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
260 if (!(mask & 1))
261 continue;
262
263 qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C62X);
264 qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C62X);
265 qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C62X);
266 }
267
268 qat_c62x_enable_error_interrupts(sc);
269 }
270
271 const struct qat_hw qat_hw_c62x = {
272 .qhw_sram_bar_id = BAR_SRAM_ID_C62X,
273 .qhw_misc_bar_id = BAR_PMISC_ID_C62X,
274 .qhw_etr_bar_id = BAR_ETR_ID_C62X,
275 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C62X,
276 .qhw_ae_offset = AE_OFFSET_C62X,
277 .qhw_ae_local_offset = AE_LOCAL_OFFSET_C62X,
278 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C62X,
279 .qhw_num_banks = ETR_MAX_BANKS_C62X,
280 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
281 .qhw_num_accel = MAX_ACCEL_C62X,
282 .qhw_num_engines = MAX_AE_C62X,
283 .qhw_tx_rx_gap = ETR_TX_RX_GAP_C62X,
284 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C62X,
285 .qhw_clock_per_sec = CLOCK_PER_SEC_C62X,
286 .qhw_fw_auth = true,
287 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
288 .qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
289 .qhw_ring_asym_tx = 0,
290 .qhw_ring_asym_rx = 8,
291 .qhw_ring_sym_tx = 2,
292 .qhw_ring_sym_rx = 10,
293 .qhw_mof_fwname = AE_FW_MOF_NAME_C62X,
294 .qhw_mmp_fwname = AE_FW_MMP_NAME_C62X,
295 .qhw_prod_type = AE_FW_PROD_TYPE_C62X,
296 .qhw_get_accel_mask = qat_c62x_get_accel_mask,
297 .qhw_get_ae_mask = qat_c62x_get_ae_mask,
298 .qhw_get_sku = qat_c62x_get_sku,
299 .qhw_get_accel_cap = qat_c62x_get_accel_cap,
300 .qhw_get_fw_uof_name = qat_c62x_get_fw_uof_name,
301 .qhw_enable_intr = qat_c62x_enable_intr,
302 .qhw_init_admin_comms = qat_adm_mailbox_init,
303 .qhw_send_admin_init = qat_adm_mailbox_send_init,
304 .qhw_init_arb = qat_arb_init,
305 .qhw_get_arb_mapping = qat_c62x_get_arb_mapping,
306 .qhw_enable_error_correction = qat_c62x_enable_error_correction,
307 .qhw_disable_error_interrupts = qat_c62x_disable_error_interrupts,
308 .qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
309 .qhw_check_slice_hang = qat_check_slice_hang,
310 .qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
311 .qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
312 .qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
313 };
314