1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 *
28 */
29
30 #ifndef _PCIVAR_H_
31 #define _PCIVAR_H_
32
33 #include <sys/queue.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44 uint8_t br_seclat;
45 uint8_t br_subbus;
46 uint8_t br_secbus;
47 uint8_t br_pribus;
48 uint16_t br_control;
49 };
50
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
56 uint8_t pp_data; /* conf. space addr. of PM data reg */
57 };
58
59 struct pci_map {
60 pci_addr_t pm_value; /* Raw BAR value */
61 pci_addr_t pm_size;
62 uint16_t pm_reg;
63 STAILQ_ENTRY(pci_map) pm_link;
64 };
65
66 struct vpd_readonly {
67 char keyword[2];
68 char *value;
69 int len;
70 };
71
72 struct vpd_write {
73 char keyword[2];
74 char *value;
75 int start;
76 int len;
77 };
78
79 struct pcicfg_vpd {
80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
81 char vpd_cached;
82 char *vpd_ident; /* string identifier */
83 int vpd_rocnt;
84 struct vpd_readonly *vpd_ros;
85 int vpd_wcnt;
86 struct vpd_write *vpd_w;
87 };
88
89 /* Interesting values for PCI MSI */
90 struct pcicfg_msi {
91 uint16_t msi_ctrl; /* Message Control */
92 uint8_t msi_location; /* Offset of MSI capability registers. */
93 uint8_t msi_msgnum; /* Number of messages */
94 int msi_alloc; /* Number of allocated messages. */
95 uint64_t msi_addr; /* Contents of address register. */
96 uint16_t msi_data; /* Contents of data register. */
97 u_int msi_handlers;
98 };
99
100 /* Interesting values for PCI MSI-X */
101 struct msix_vector {
102 uint64_t mv_address; /* Contents of address register. */
103 uint32_t mv_data; /* Contents of data register. */
104 int mv_irq;
105 };
106
107 struct msix_table_entry {
108 u_int mte_vector; /* 1-based index into msix_vectors array. */
109 u_int mte_handlers;
110 };
111
112 struct pcicfg_msix {
113 uint16_t msix_ctrl; /* Message Control */
114 uint16_t msix_msgnum; /* Number of messages */
115 uint8_t msix_location; /* Offset of MSI-X capability registers. */
116 uint8_t msix_table_bar; /* BAR containing vector table. */
117 uint8_t msix_pba_bar; /* BAR containing PBA. */
118 uint32_t msix_table_offset;
119 uint32_t msix_pba_offset;
120 int msix_alloc; /* Number of allocated vectors. */
121 int msix_table_len; /* Length of virtual table. */
122 struct msix_table_entry *msix_table; /* Virtual table. */
123 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
124 struct resource *msix_table_res; /* Resource containing vector table. */
125 struct resource *msix_pba_res; /* Resource containing PBA. */
126 };
127
128 /* Interesting values for HyperTransport */
129 struct pcicfg_ht {
130 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
131 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
132 uint16_t ht_msictrl; /* MSI mapping control */
133 uint64_t ht_msiaddr; /* MSI mapping base address */
134 };
135
136 /* Interesting values for PCI-express */
137 struct pcicfg_pcie {
138 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
139 uint8_t pcie_type; /* Device type. */
140 uint16_t pcie_flags; /* Device capabilities register. */
141 uint16_t pcie_device_ctl; /* Device control register. */
142 uint16_t pcie_link_ctl; /* Link control register. */
143 uint16_t pcie_slot_ctl; /* Slot control register. */
144 uint16_t pcie_root_ctl; /* Root control register. */
145 uint16_t pcie_device_ctl2; /* Second device control register. */
146 uint16_t pcie_link_ctl2; /* Second link control register. */
147 uint16_t pcie_slot_ctl2; /* Second slot control register. */
148 };
149
150 struct pcicfg_pcix {
151 uint16_t pcix_command;
152 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
153 };
154
155 struct pcicfg_vf {
156 int index;
157 };
158
159 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
160
161 /* config header information common to all header types */
162 typedef struct pcicfg {
163 struct device *dev; /* device which owns this */
164
165 STAILQ_HEAD(, pci_map) maps; /* BARs */
166
167 uint16_t subvendor; /* card vendor ID */
168 uint16_t subdevice; /* card device ID, assigned by card vendor */
169 uint16_t vendor; /* chip vendor ID */
170 uint16_t device; /* chip device ID, assigned by chip vendor */
171
172 uint16_t cmdreg; /* disable/enable chip and PCI options */
173 uint16_t statreg; /* supported PCI features and error state */
174
175 uint8_t baseclass; /* chip PCI class */
176 uint8_t subclass; /* chip PCI subclass */
177 uint8_t progif; /* chip PCI programming interface */
178 uint8_t revid; /* chip revision ID */
179
180 uint8_t hdrtype; /* chip config header type */
181 uint8_t cachelnsz; /* cache line size in 4byte units */
182 uint8_t intpin; /* PCI interrupt pin */
183 uint8_t intline; /* interrupt line (IRQ for PC arch) */
184
185 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
186 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
187 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
188
189 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
190 uint8_t nummaps; /* actual number of PCI maps used */
191
192 uint32_t domain; /* PCI domain */
193 uint8_t bus; /* config space bus address */
194 uint8_t slot; /* config space slot address */
195 uint8_t func; /* config space function number */
196
197 uint32_t flags; /* flags defined above */
198 size_t devinfo_size; /* Size of devinfo for this bus type. */
199
200 struct pcicfg_bridge bridge; /* Bridges */
201 struct pcicfg_pp pp; /* Power management */
202 struct pcicfg_vpd vpd; /* Vital product data */
203 struct pcicfg_msi msi; /* PCI MSI */
204 struct pcicfg_msix msix; /* PCI MSI-X */
205 struct pcicfg_ht ht; /* HyperTransport */
206 struct pcicfg_pcie pcie; /* PCI Express */
207 struct pcicfg_pcix pcix; /* PCI-X */
208 struct pcicfg_iov *iov; /* SR-IOV */
209 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
210 } pcicfgregs;
211
212 /* additional type 1 device config header information (PCI to PCI bridge) */
213
214 typedef struct {
215 pci_addr_t pmembase; /* base address of prefetchable memory */
216 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
217 uint32_t membase; /* base address of memory window */
218 uint32_t memlimit; /* topmost address of memory window */
219 uint32_t iobase; /* base address of port window */
220 uint32_t iolimit; /* topmost address of port window */
221 uint16_t secstat; /* secondary bus status register */
222 uint16_t bridgectl; /* bridge control register */
223 uint8_t seclat; /* CardBus latency timer */
224 } pcih1cfgregs;
225
226 /* additional type 2 device config header information (CardBus bridge) */
227
228 typedef struct {
229 uint32_t membase0; /* base address of memory window */
230 uint32_t memlimit0; /* topmost address of memory window */
231 uint32_t membase1; /* base address of memory window */
232 uint32_t memlimit1; /* topmost address of memory window */
233 uint32_t iobase0; /* base address of port window */
234 uint32_t iolimit0; /* topmost address of port window */
235 uint32_t iobase1; /* base address of port window */
236 uint32_t iolimit1; /* topmost address of port window */
237 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
238 uint16_t secstat; /* secondary bus status register */
239 uint16_t bridgectl; /* bridge control register */
240 uint8_t seclat; /* CardBus latency timer */
241 } pcih2cfgregs;
242
243 extern uint32_t pci_numdevs;
244
245 /* Only if the prerequisites are present */
246 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
247 struct pci_devinfo {
248 STAILQ_ENTRY(pci_devinfo) pci_links;
249 struct resource_list resources;
250 pcicfgregs cfg;
251 struct pci_conf conf;
252 };
253 #endif
254
255 #ifdef _SYS_BUS_H_
256
257 #include "pci_if.h"
258
259 enum pci_device_ivars {
260 PCI_IVAR_SUBVENDOR,
261 PCI_IVAR_SUBDEVICE,
262 PCI_IVAR_VENDOR,
263 PCI_IVAR_DEVICE,
264 PCI_IVAR_DEVID,
265 PCI_IVAR_CLASS,
266 PCI_IVAR_SUBCLASS,
267 PCI_IVAR_PROGIF,
268 PCI_IVAR_REVID,
269 PCI_IVAR_INTPIN,
270 PCI_IVAR_IRQ,
271 PCI_IVAR_DOMAIN,
272 PCI_IVAR_BUS,
273 PCI_IVAR_SLOT,
274 PCI_IVAR_FUNCTION,
275 PCI_IVAR_ETHADDR,
276 PCI_IVAR_CMDREG,
277 PCI_IVAR_CACHELNSZ,
278 PCI_IVAR_MINGNT,
279 PCI_IVAR_MAXLAT,
280 PCI_IVAR_LATTIMER
281 };
282
283 /*
284 * Simplified accessors for pci devices
285 */
286 #define PCI_ACCESSOR(var, ivar, type) \
287 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
288
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)289 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
290 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
291 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
292 PCI_ACCESSOR(device, DEVICE, uint16_t)
293 PCI_ACCESSOR(devid, DEVID, uint32_t)
294 PCI_ACCESSOR(class, CLASS, uint8_t)
295 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
296 PCI_ACCESSOR(progif, PROGIF, uint8_t)
297 PCI_ACCESSOR(revid, REVID, uint8_t)
298 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
299 PCI_ACCESSOR(irq, IRQ, uint8_t)
300 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
301 PCI_ACCESSOR(bus, BUS, uint8_t)
302 PCI_ACCESSOR(slot, SLOT, uint8_t)
303 PCI_ACCESSOR(function, FUNCTION, uint8_t)
304 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
305 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
306 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
307 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
308 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
309 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
310
311 #undef PCI_ACCESSOR
312
313 /*
314 * Operations on configuration space.
315 */
316 static __inline uint32_t
317 pci_read_config(device_t dev, int reg, int width)
318 {
319 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
320 }
321
322 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)323 pci_write_config(device_t dev, int reg, uint32_t val, int width)
324 {
325 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
326 }
327
328 /*
329 * Ivars for pci bridges.
330 */
331
332 /*typedef enum pci_device_ivars pcib_device_ivars;*/
333 enum pcib_device_ivars {
334 PCIB_IVAR_DOMAIN,
335 PCIB_IVAR_BUS
336 };
337
338 #define PCIB_ACCESSOR(var, ivar, type) \
339 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
340
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)341 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
342 PCIB_ACCESSOR(bus, BUS, uint32_t)
343
344 #undef PCIB_ACCESSOR
345
346 /*
347 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
348 * on i386 or other platforms should be mapped out in the MD pcireadconf
349 * code and not here, since the only MI invalid IRQ is 255.
350 */
351 #define PCI_INVALID_IRQ 255
352 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
353
354 /*
355 * Convenience functions.
356 *
357 * These should be used in preference to manually manipulating
358 * configuration space.
359 */
360 static __inline int
361 pci_enable_busmaster(device_t dev)
362 {
363 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
364 }
365
366 static __inline int
pci_disable_busmaster(device_t dev)367 pci_disable_busmaster(device_t dev)
368 {
369 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
370 }
371
372 static __inline int
pci_enable_io(device_t dev,int space)373 pci_enable_io(device_t dev, int space)
374 {
375 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
376 }
377
378 static __inline int
pci_disable_io(device_t dev,int space)379 pci_disable_io(device_t dev, int space)
380 {
381 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
382 }
383
384 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)385 pci_get_vpd_ident(device_t dev, const char **identptr)
386 {
387 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
388 }
389
390 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)391 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
392 {
393 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
394 }
395
396 /*
397 * Check if the address range falls within the VGA defined address range(s)
398 */
399 static __inline int
pci_is_vga_ioport_range(u_long start,u_long end)400 pci_is_vga_ioport_range(u_long start, u_long end)
401 {
402
403 return (((start >= 0x3b0 && end <= 0x3bb) ||
404 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
405 }
406
407 static __inline int
pci_is_vga_memory_range(u_long start,u_long end)408 pci_is_vga_memory_range(u_long start, u_long end)
409 {
410
411 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
412 }
413
414 /*
415 * PCI power states are as defined by ACPI:
416 *
417 * D0 State in which device is on and running. It is receiving full
418 * power from the system and delivering full functionality to the user.
419 * D1 Class-specific low-power state in which device context may or may not
420 * be lost. Buses in D1 cannot do anything to the bus that would force
421 * devices on that bus to lose context.
422 * D2 Class-specific low-power state in which device context may or may
423 * not be lost. Attains greater power savings than D1. Buses in D2
424 * can cause devices on that bus to lose some context. Devices in D2
425 * must be prepared for the bus to be in D2 or higher.
426 * D3 State in which the device is off and not running. Device context is
427 * lost. Power can be removed from the device.
428 */
429 #define PCI_POWERSTATE_D0 0
430 #define PCI_POWERSTATE_D1 1
431 #define PCI_POWERSTATE_D2 2
432 #define PCI_POWERSTATE_D3 3
433 #define PCI_POWERSTATE_UNKNOWN -1
434
435 static __inline int
pci_set_powerstate(device_t dev,int state)436 pci_set_powerstate(device_t dev, int state)
437 {
438 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
439 }
440
441 static __inline int
pci_get_powerstate(device_t dev)442 pci_get_powerstate(device_t dev)
443 {
444 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
445 }
446
447 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)448 pci_find_cap(device_t dev, int capability, int *capreg)
449 {
450 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
451 }
452
453 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)454 pci_find_extcap(device_t dev, int capability, int *capreg)
455 {
456 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
457 }
458
459 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)460 pci_find_htcap(device_t dev, int capability, int *capreg)
461 {
462 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
463 }
464
465 static __inline int
pci_alloc_msi(device_t dev,int * count)466 pci_alloc_msi(device_t dev, int *count)
467 {
468 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
469 }
470
471 static __inline int
pci_alloc_msix(device_t dev,int * count)472 pci_alloc_msix(device_t dev, int *count)
473 {
474 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
475 }
476
477 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)478 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
479 {
480 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
481 }
482
483 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)484 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
485 {
486 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
487 }
488
489 static __inline void
pci_disable_msi(device_t dev)490 pci_disable_msi(device_t dev)
491 {
492 PCI_DISABLE_MSI(device_get_parent(dev), dev);
493 }
494
495 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)496 pci_remap_msix(device_t dev, int count, const u_int *vectors)
497 {
498 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
499 }
500
501 static __inline int
pci_release_msi(device_t dev)502 pci_release_msi(device_t dev)
503 {
504 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
505 }
506
507 static __inline int
pci_msi_count(device_t dev)508 pci_msi_count(device_t dev)
509 {
510 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
511 }
512
513 static __inline int
pci_msix_count(device_t dev)514 pci_msix_count(device_t dev)
515 {
516 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
517 }
518
519 static __inline int
pci_msix_pba_bar(device_t dev)520 pci_msix_pba_bar(device_t dev)
521 {
522 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
523 }
524
525 static __inline int
pci_msix_table_bar(device_t dev)526 pci_msix_table_bar(device_t dev)
527 {
528 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
529 }
530
531 static __inline uint16_t
pci_get_rid(device_t dev)532 pci_get_rid(device_t dev)
533 {
534 return (PCI_GET_RID(device_get_parent(dev), dev));
535 }
536
537 static __inline void
pci_child_added(device_t dev)538 pci_child_added(device_t dev)
539 {
540
541 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
542 }
543
544 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
545 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
546 device_t pci_find_device(uint16_t, uint16_t);
547 device_t pci_find_class(uint8_t class, uint8_t subclass);
548
549 /* Can be used by drivers to manage the MSI-X table. */
550 int pci_pending_msix(device_t dev, u_int index);
551
552 int pci_msi_device_blacklisted(device_t dev);
553 int pci_msix_device_blacklisted(device_t dev);
554
555 void pci_ht_map_msi(device_t dev, uint64_t addr);
556
557 device_t pci_find_pcie_root_port(device_t dev);
558 int pci_get_max_read_req(device_t dev);
559 void pci_restore_state(device_t dev);
560 void pci_save_state(device_t dev);
561 int pci_set_max_read_req(device_t dev, int size);
562 uint32_t pcie_read_config(device_t dev, int reg, int width);
563 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
564 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
565 uint32_t value, int width);
566
567
568 #ifdef BUS_SPACE_MAXADDR
569 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
570 #define PCI_DMA_BOUNDARY 0x100000000
571 #else
572 #define PCI_DMA_BOUNDARY 0
573 #endif
574 #endif
575
576 #endif /* _SYS_BUS_H_ */
577
578 /*
579 * cdev switch for control device, initialised in generic PCI code
580 */
581 extern struct cdevsw pcicdev;
582
583 /*
584 * List of all PCI devices, generation count for the list.
585 */
586 STAILQ_HEAD(devlist, pci_devinfo);
587
588 extern struct devlist pci_devq;
589 extern uint32_t pci_generation;
590
591 struct pci_map *pci_find_bar(device_t dev, int reg);
592 int pci_bar_enabled(device_t dev, struct pci_map *pm);
593 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
594
595 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
596 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
597
598 int vga_pci_is_boot_display(device_t dev);
599 void * vga_pci_map_bios(device_t dev, size_t *size);
600 void vga_pci_unmap_bios(device_t dev, void *bios);
601 int vga_pci_repost(device_t dev);
602
603 #endif /* _PCIVAR_H_ */
604