1 /*-
2 * Written by: yen_cw@myson.com.tw
3 * Copyright (c) 2002 Myson Technology Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/module.h>
43 #include <sys/lock.h>
44 #include <sys/mutex.h>
45
46 #define NBPFILTER 1
47
48 #include <net/if.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/if_dl.h>
54 #include <net/bpf.h>
55
56 #include <vm/vm.h> /* for vtophys */
57 #include <vm/pmap.h> /* for vtophys */
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60 #include <sys/bus.h>
61 #include <sys/rman.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65
66 /*
67 * #define MY_USEIOSPACE
68 */
69
70 static int MY_USEIOSPACE = 1;
71
72 #ifdef MY_USEIOSPACE
73 #define MY_RES SYS_RES_IOPORT
74 #define MY_RID MY_PCI_LOIO
75 #else
76 #define MY_RES SYS_RES_MEMORY
77 #define MY_RID MY_PCI_LOMEM
78 #endif
79
80
81 #include <dev/my/if_myreg.h>
82
83 /*
84 * Various supported device vendors/types and their names.
85 */
86 struct my_type *my_info_tmp;
87 static struct my_type my_devs[] = {
88 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
89 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
90 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
91 {0, 0, NULL}
92 };
93
94 /*
95 * Various supported PHY vendors/types and their names. Note that this driver
96 * will work with pretty much any MII-compliant PHY, so failure to positively
97 * identify the chip is not a fatal error.
98 */
99 static struct my_type my_phys[] = {
100 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
101 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
102 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
103 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
104 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
105 {0, 0, "<MII-compliant physical interface>"}
106 };
107
108 static int my_probe(device_t);
109 static int my_attach(device_t);
110 static int my_detach(device_t);
111 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
112 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
113 static void my_rxeof(struct my_softc *);
114 static void my_txeof(struct my_softc *);
115 static void my_txeoc(struct my_softc *);
116 static void my_intr(void *);
117 static void my_start(struct ifnet *);
118 static void my_start_locked(struct ifnet *);
119 static int my_ioctl(struct ifnet *, u_long, caddr_t);
120 static void my_init(void *);
121 static void my_init_locked(struct my_softc *);
122 static void my_stop(struct my_softc *);
123 static void my_autoneg_timeout(void *);
124 static void my_watchdog(void *);
125 static int my_shutdown(device_t);
126 static int my_ifmedia_upd(struct ifnet *);
127 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
128 static u_int16_t my_phy_readreg(struct my_softc *, int);
129 static void my_phy_writereg(struct my_softc *, int, int);
130 static void my_autoneg_xmit(struct my_softc *);
131 static void my_autoneg_mii(struct my_softc *, int, int);
132 static void my_setmode_mii(struct my_softc *, int);
133 static void my_getmode_mii(struct my_softc *);
134 static void my_setcfg(struct my_softc *, int);
135 static void my_setmulti(struct my_softc *);
136 static void my_reset(struct my_softc *);
137 static int my_list_rx_init(struct my_softc *);
138 static int my_list_tx_init(struct my_softc *);
139 static long my_send_cmd_to_phy(struct my_softc *, int, int);
140
141 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
142 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
143
144 static device_method_t my_methods[] = {
145 /* Device interface */
146 DEVMETHOD(device_probe, my_probe),
147 DEVMETHOD(device_attach, my_attach),
148 DEVMETHOD(device_detach, my_detach),
149 DEVMETHOD(device_shutdown, my_shutdown),
150
151 DEVMETHOD_END
152 };
153
154 static driver_t my_driver = {
155 "my",
156 my_methods,
157 sizeof(struct my_softc)
158 };
159
160 static devclass_t my_devclass;
161
162 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
163 MODULE_DEPEND(my, pci, 1, 1, 1);
164 MODULE_DEPEND(my, ether, 1, 1, 1);
165
166 static long
my_send_cmd_to_phy(struct my_softc * sc,int opcode,int regad)167 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
168 {
169 long miir;
170 int i;
171 int mask, data;
172
173 MY_LOCK_ASSERT(sc);
174
175 /* enable MII output */
176 miir = CSR_READ_4(sc, MY_MANAGEMENT);
177 miir &= 0xfffffff0;
178
179 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
180
181 /* send 32 1's preamble */
182 for (i = 0; i < 32; i++) {
183 /* low MDC; MDO is already high (miir) */
184 miir &= ~MY_MASK_MIIR_MII_MDC;
185 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
186
187 /* high MDC */
188 miir |= MY_MASK_MIIR_MII_MDC;
189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
190 }
191
192 /* calculate ST+OP+PHYAD+REGAD+TA */
193 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
194
195 /* sent out */
196 mask = 0x8000;
197 while (mask) {
198 /* low MDC, prepare MDO */
199 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
200 if (mask & data)
201 miir |= MY_MASK_MIIR_MII_MDO;
202
203 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
204 /* high MDC */
205 miir |= MY_MASK_MIIR_MII_MDC;
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
207 DELAY(30);
208
209 /* next */
210 mask >>= 1;
211 if (mask == 0x2 && opcode == MY_OP_READ)
212 miir &= ~MY_MASK_MIIR_MII_WRITE;
213 }
214
215 return miir;
216 }
217
218
219 static u_int16_t
my_phy_readreg(struct my_softc * sc,int reg)220 my_phy_readreg(struct my_softc * sc, int reg)
221 {
222 long miir;
223 int mask, data;
224
225 MY_LOCK_ASSERT(sc);
226
227 if (sc->my_info->my_did == MTD803ID)
228 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
229 else {
230 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
231
232 /* read data */
233 mask = 0x8000;
234 data = 0;
235 while (mask) {
236 /* low MDC */
237 miir &= ~MY_MASK_MIIR_MII_MDC;
238 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
239
240 /* read MDI */
241 miir = CSR_READ_4(sc, MY_MANAGEMENT);
242 if (miir & MY_MASK_MIIR_MII_MDI)
243 data |= mask;
244
245 /* high MDC, and wait */
246 miir |= MY_MASK_MIIR_MII_MDC;
247 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
248 DELAY(30);
249
250 /* next */
251 mask >>= 1;
252 }
253
254 /* low MDC */
255 miir &= ~MY_MASK_MIIR_MII_MDC;
256 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
257 }
258
259 return (u_int16_t) data;
260 }
261
262
263 static void
my_phy_writereg(struct my_softc * sc,int reg,int data)264 my_phy_writereg(struct my_softc * sc, int reg, int data)
265 {
266 long miir;
267 int mask;
268
269 MY_LOCK_ASSERT(sc);
270
271 if (sc->my_info->my_did == MTD803ID)
272 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
273 else {
274 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
275
276 /* write data */
277 mask = 0x8000;
278 while (mask) {
279 /* low MDC, prepare MDO */
280 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
281 if (mask & data)
282 miir |= MY_MASK_MIIR_MII_MDO;
283 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
284 DELAY(1);
285
286 /* high MDC */
287 miir |= MY_MASK_MIIR_MII_MDC;
288 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
289 DELAY(1);
290
291 /* next */
292 mask >>= 1;
293 }
294
295 /* low MDC */
296 miir &= ~MY_MASK_MIIR_MII_MDC;
297 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
298 }
299 return;
300 }
301
302
303 /*
304 * Program the 64-bit multicast hash filter.
305 */
306 static void
my_setmulti(struct my_softc * sc)307 my_setmulti(struct my_softc * sc)
308 {
309 struct ifnet *ifp;
310 int h = 0;
311 u_int32_t hashes[2] = {0, 0};
312 struct ifmultiaddr *ifma;
313 u_int32_t rxfilt;
314 int mcnt = 0;
315
316 MY_LOCK_ASSERT(sc);
317
318 ifp = sc->my_ifp;
319
320 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
321
322 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
323 rxfilt |= MY_AM;
324 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
325 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
326 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
327
328 return;
329 }
330 /* first, zot all the existing hash bits */
331 CSR_WRITE_4(sc, MY_MAR0, 0);
332 CSR_WRITE_4(sc, MY_MAR1, 0);
333
334 /* now program new ones */
335 if_maddr_rlock(ifp);
336 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
337 if (ifma->ifma_addr->sa_family != AF_LINK)
338 continue;
339 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
340 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
341 if (h < 32)
342 hashes[0] |= (1 << h);
343 else
344 hashes[1] |= (1 << (h - 32));
345 mcnt++;
346 }
347 if_maddr_runlock(ifp);
348
349 if (mcnt)
350 rxfilt |= MY_AM;
351 else
352 rxfilt &= ~MY_AM;
353 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
354 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
355 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
356 return;
357 }
358
359 /*
360 * Initiate an autonegotiation session.
361 */
362 static void
my_autoneg_xmit(struct my_softc * sc)363 my_autoneg_xmit(struct my_softc * sc)
364 {
365 u_int16_t phy_sts = 0;
366
367 MY_LOCK_ASSERT(sc);
368
369 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
370 DELAY(500);
371 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
372
373 phy_sts = my_phy_readreg(sc, PHY_BMCR);
374 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
375 my_phy_writereg(sc, PHY_BMCR, phy_sts);
376
377 return;
378 }
379
380 static void
my_autoneg_timeout(void * arg)381 my_autoneg_timeout(void *arg)
382 {
383 struct my_softc *sc;
384
385 sc = arg;
386 MY_LOCK_ASSERT(sc);
387 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
388 }
389
390 /*
391 * Invoke autonegotiation on a PHY.
392 */
393 static void
my_autoneg_mii(struct my_softc * sc,int flag,int verbose)394 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
395 {
396 u_int16_t phy_sts = 0, media, advert, ability;
397 u_int16_t ability2 = 0;
398 struct ifnet *ifp;
399 struct ifmedia *ifm;
400
401 MY_LOCK_ASSERT(sc);
402
403 ifm = &sc->ifmedia;
404 ifp = sc->my_ifp;
405
406 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
407
408 #ifndef FORCE_AUTONEG_TFOUR
409 /*
410 * First, see if autoneg is supported. If not, there's no point in
411 * continuing.
412 */
413 phy_sts = my_phy_readreg(sc, PHY_BMSR);
414 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
415 if (verbose)
416 device_printf(sc->my_dev,
417 "autonegotiation not supported\n");
418 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
419 return;
420 }
421 #endif
422 switch (flag) {
423 case MY_FLAG_FORCEDELAY:
424 /*
425 * XXX Never use this option anywhere but in the probe
426 * routine: making the kernel stop dead in its tracks for
427 * three whole seconds after we've gone multi-user is really
428 * bad manners.
429 */
430 my_autoneg_xmit(sc);
431 DELAY(5000000);
432 break;
433 case MY_FLAG_SCHEDDELAY:
434 /*
435 * Wait for the transmitter to go idle before starting an
436 * autoneg session, otherwise my_start() may clobber our
437 * timeout, and we don't want to allow transmission during an
438 * autoneg session since that can screw it up.
439 */
440 if (sc->my_cdata.my_tx_head != NULL) {
441 sc->my_want_auto = 1;
442 MY_UNLOCK(sc);
443 return;
444 }
445 my_autoneg_xmit(sc);
446 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
447 sc);
448 sc->my_autoneg = 1;
449 sc->my_want_auto = 0;
450 return;
451 case MY_FLAG_DELAYTIMEO:
452 callout_stop(&sc->my_autoneg_timer);
453 sc->my_autoneg = 0;
454 break;
455 default:
456 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
457 return;
458 }
459
460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
461 if (verbose)
462 device_printf(sc->my_dev, "autoneg complete, ");
463 phy_sts = my_phy_readreg(sc, PHY_BMSR);
464 } else {
465 if (verbose)
466 device_printf(sc->my_dev, "autoneg not complete, ");
467 }
468
469 media = my_phy_readreg(sc, PHY_BMCR);
470
471 /* Link is good. Report modes and set duplex mode. */
472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
473 if (verbose)
474 device_printf(sc->my_dev, "link status good. ");
475 advert = my_phy_readreg(sc, PHY_ANAR);
476 ability = my_phy_readreg(sc, PHY_LPAR);
477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 ability2 = my_phy_readreg(sc, PHY_1000SR);
480 if (ability2 & PHY_1000SR_1000BTXFULL) {
481 advert = 0;
482 ability = 0;
483 /*
484 * this version did not support 1000M,
485 * ifm->ifm_media =
486 * IFM_ETHER|IFM_1000_T|IFM_FDX;
487 */
488 ifm->ifm_media =
489 IFM_ETHER | IFM_100_TX | IFM_FDX;
490 media &= ~PHY_BMCR_SPEEDSEL;
491 media |= PHY_BMCR_1000;
492 media |= PHY_BMCR_DUPLEX;
493 printf("(full-duplex, 1000Mbps)\n");
494 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
495 advert = 0;
496 ability = 0;
497 /*
498 * this version did not support 1000M,
499 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
500 */
501 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 media &= ~PHY_BMCR_SPEEDSEL;
503 media &= ~PHY_BMCR_DUPLEX;
504 media |= PHY_BMCR_1000;
505 printf("(half-duplex, 1000Mbps)\n");
506 }
507 }
508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 media |= PHY_BMCR_SPEEDSEL;
511 media &= ~PHY_BMCR_DUPLEX;
512 printf("(100baseT4)\n");
513 } else if (advert & PHY_ANAR_100BTXFULL &&
514 ability & PHY_ANAR_100BTXFULL) {
515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 media |= PHY_BMCR_SPEEDSEL;
517 media |= PHY_BMCR_DUPLEX;
518 printf("(full-duplex, 100Mbps)\n");
519 } else if (advert & PHY_ANAR_100BTXHALF &&
520 ability & PHY_ANAR_100BTXHALF) {
521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 media |= PHY_BMCR_SPEEDSEL;
523 media &= ~PHY_BMCR_DUPLEX;
524 printf("(half-duplex, 100Mbps)\n");
525 } else if (advert & PHY_ANAR_10BTFULL &&
526 ability & PHY_ANAR_10BTFULL) {
527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 media &= ~PHY_BMCR_SPEEDSEL;
529 media |= PHY_BMCR_DUPLEX;
530 printf("(full-duplex, 10Mbps)\n");
531 } else if (advert) {
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 printf("(half-duplex, 10Mbps)\n");
536 }
537 media &= ~PHY_BMCR_AUTONEGENBL;
538
539 /* Set ASIC's duplex mode to match the PHY. */
540 my_phy_writereg(sc, PHY_BMCR, media);
541 my_setcfg(sc, media);
542 } else {
543 if (verbose)
544 device_printf(sc->my_dev, "no carrier\n");
545 }
546
547 my_init_locked(sc);
548 if (sc->my_tx_pend) {
549 sc->my_autoneg = 0;
550 sc->my_tx_pend = 0;
551 my_start_locked(ifp);
552 }
553 return;
554 }
555
556 /*
557 * To get PHY ability.
558 */
559 static void
my_getmode_mii(struct my_softc * sc)560 my_getmode_mii(struct my_softc * sc)
561 {
562 u_int16_t bmsr;
563 struct ifnet *ifp;
564
565 MY_LOCK_ASSERT(sc);
566 ifp = sc->my_ifp;
567 bmsr = my_phy_readreg(sc, PHY_BMSR);
568 if (bootverbose)
569 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
570
571 /* fallback */
572 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
573
574 if (bmsr & PHY_BMSR_10BTHALF) {
575 if (bootverbose)
576 device_printf(sc->my_dev,
577 "10Mbps half-duplex mode supported\n");
578 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
579 0, NULL);
580 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
581 }
582 if (bmsr & PHY_BMSR_10BTFULL) {
583 if (bootverbose)
584 device_printf(sc->my_dev,
585 "10Mbps full-duplex mode supported\n");
586
587 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
588 0, NULL);
589 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
590 }
591 if (bmsr & PHY_BMSR_100BTXHALF) {
592 if (bootverbose)
593 device_printf(sc->my_dev,
594 "100Mbps half-duplex mode supported\n");
595 ifp->if_baudrate = 100000000;
596 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
597 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
598 0, NULL);
599 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
600 }
601 if (bmsr & PHY_BMSR_100BTXFULL) {
602 if (bootverbose)
603 device_printf(sc->my_dev,
604 "100Mbps full-duplex mode supported\n");
605 ifp->if_baudrate = 100000000;
606 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
607 0, NULL);
608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
609 }
610 /* Some also support 100BaseT4. */
611 if (bmsr & PHY_BMSR_100BT4) {
612 if (bootverbose)
613 device_printf(sc->my_dev, "100baseT4 mode supported\n");
614 ifp->if_baudrate = 100000000;
615 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
616 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
617 #ifdef FORCE_AUTONEG_TFOUR
618 if (bootverbose)
619 device_printf(sc->my_dev,
620 "forcing on autoneg support for BT4\n");
621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
622 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
623 #endif
624 }
625 #if 0 /* this version did not support 1000M, */
626 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
627 if (bootverbose)
628 device_printf(sc->my_dev,
629 "1000Mbps half-duplex mode supported\n");
630
631 ifp->if_baudrate = 1000000000;
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
634 0, NULL);
635 if (bootverbose)
636 device_printf(sc->my_dev,
637 "1000Mbps full-duplex mode supported\n");
638 ifp->if_baudrate = 1000000000;
639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
640 0, NULL);
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
642 }
643 #endif
644 if (bmsr & PHY_BMSR_CANAUTONEG) {
645 if (bootverbose)
646 device_printf(sc->my_dev, "autoneg supported\n");
647 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
648 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
649 }
650 return;
651 }
652
653 /*
654 * Set speed and duplex mode.
655 */
656 static void
my_setmode_mii(struct my_softc * sc,int media)657 my_setmode_mii(struct my_softc * sc, int media)
658 {
659 u_int16_t bmcr;
660
661 MY_LOCK_ASSERT(sc);
662 /*
663 * If an autoneg session is in progress, stop it.
664 */
665 if (sc->my_autoneg) {
666 device_printf(sc->my_dev, "canceling autoneg session\n");
667 callout_stop(&sc->my_autoneg_timer);
668 sc->my_autoneg = sc->my_want_auto = 0;
669 bmcr = my_phy_readreg(sc, PHY_BMCR);
670 bmcr &= ~PHY_BMCR_AUTONEGENBL;
671 my_phy_writereg(sc, PHY_BMCR, bmcr);
672 }
673 device_printf(sc->my_dev, "selecting MII, ");
674 bmcr = my_phy_readreg(sc, PHY_BMCR);
675 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
676 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
677
678 #if 0 /* this version did not support 1000M, */
679 if (IFM_SUBTYPE(media) == IFM_1000_T) {
680 printf("1000Mbps/T4, half-duplex\n");
681 bmcr &= ~PHY_BMCR_SPEEDSEL;
682 bmcr &= ~PHY_BMCR_DUPLEX;
683 bmcr |= PHY_BMCR_1000;
684 }
685 #endif
686 if (IFM_SUBTYPE(media) == IFM_100_T4) {
687 printf("100Mbps/T4, half-duplex\n");
688 bmcr |= PHY_BMCR_SPEEDSEL;
689 bmcr &= ~PHY_BMCR_DUPLEX;
690 }
691 if (IFM_SUBTYPE(media) == IFM_100_TX) {
692 printf("100Mbps, ");
693 bmcr |= PHY_BMCR_SPEEDSEL;
694 }
695 if (IFM_SUBTYPE(media) == IFM_10_T) {
696 printf("10Mbps, ");
697 bmcr &= ~PHY_BMCR_SPEEDSEL;
698 }
699 if ((media & IFM_GMASK) == IFM_FDX) {
700 printf("full duplex\n");
701 bmcr |= PHY_BMCR_DUPLEX;
702 } else {
703 printf("half duplex\n");
704 bmcr &= ~PHY_BMCR_DUPLEX;
705 }
706 my_phy_writereg(sc, PHY_BMCR, bmcr);
707 my_setcfg(sc, bmcr);
708 return;
709 }
710
711 /*
712 * The Myson manual states that in order to fiddle with the 'full-duplex' and
713 * '100Mbps' bits in the netconfig register, we first have to put the
714 * transmit and/or receive logic in the idle state.
715 */
716 static void
my_setcfg(struct my_softc * sc,int bmcr)717 my_setcfg(struct my_softc * sc, int bmcr)
718 {
719 int i, restart = 0;
720
721 MY_LOCK_ASSERT(sc);
722 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
723 restart = 1;
724 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
725 for (i = 0; i < MY_TIMEOUT; i++) {
726 DELAY(10);
727 if (!(CSR_READ_4(sc, MY_TCRRCR) &
728 (MY_TXRUN | MY_RXRUN)))
729 break;
730 }
731 if (i == MY_TIMEOUT)
732 device_printf(sc->my_dev,
733 "failed to force tx and rx to idle \n");
734 }
735 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
736 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
737 if (bmcr & PHY_BMCR_1000)
738 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
739 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
740 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
741 if (bmcr & PHY_BMCR_DUPLEX)
742 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
743 else
744 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
745 if (restart)
746 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
747 return;
748 }
749
750 static void
my_reset(struct my_softc * sc)751 my_reset(struct my_softc * sc)
752 {
753 register int i;
754
755 MY_LOCK_ASSERT(sc);
756 MY_SETBIT(sc, MY_BCR, MY_SWR);
757 for (i = 0; i < MY_TIMEOUT; i++) {
758 DELAY(10);
759 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
760 break;
761 }
762 if (i == MY_TIMEOUT)
763 device_printf(sc->my_dev, "reset never completed!\n");
764
765 /* Wait a little while for the chip to get its brains in order. */
766 DELAY(1000);
767 return;
768 }
769
770 /*
771 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
772 * list and return a device name if we find a match.
773 */
774 static int
my_probe(device_t dev)775 my_probe(device_t dev)
776 {
777 struct my_type *t;
778
779 t = my_devs;
780 while (t->my_name != NULL) {
781 if ((pci_get_vendor(dev) == t->my_vid) &&
782 (pci_get_device(dev) == t->my_did)) {
783 device_set_desc(dev, t->my_name);
784 my_info_tmp = t;
785 return (BUS_PROBE_DEFAULT);
786 }
787 t++;
788 }
789 return (ENXIO);
790 }
791
792 /*
793 * Attach the interface. Allocate softc structures, do ifmedia setup and
794 * ethernet/BPF attach.
795 */
796 static int
my_attach(device_t dev)797 my_attach(device_t dev)
798 {
799 int i;
800 u_char eaddr[ETHER_ADDR_LEN];
801 u_int32_t iobase;
802 struct my_softc *sc;
803 struct ifnet *ifp;
804 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
805 unsigned int round;
806 caddr_t roundptr;
807 struct my_type *p;
808 u_int16_t phy_vid, phy_did, phy_sts = 0;
809 int rid, error = 0;
810
811 sc = device_get_softc(dev);
812 sc->my_dev = dev;
813 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
814 MTX_DEF);
815 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
816 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
817
818 /*
819 * Map control/status registers.
820 */
821 pci_enable_busmaster(dev);
822
823 if (my_info_tmp->my_did == MTD800ID) {
824 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
825 if (iobase & 0x300)
826 MY_USEIOSPACE = 0;
827 }
828
829 rid = MY_RID;
830 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
831
832 if (sc->my_res == NULL) {
833 device_printf(dev, "couldn't map ports/memory\n");
834 error = ENXIO;
835 goto destroy_mutex;
836 }
837 sc->my_btag = rman_get_bustag(sc->my_res);
838 sc->my_bhandle = rman_get_bushandle(sc->my_res);
839
840 rid = 0;
841 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
842 RF_SHAREABLE | RF_ACTIVE);
843
844 if (sc->my_irq == NULL) {
845 device_printf(dev, "couldn't map interrupt\n");
846 error = ENXIO;
847 goto release_io;
848 }
849
850 sc->my_info = my_info_tmp;
851
852 /* Reset the adapter. */
853 MY_LOCK(sc);
854 my_reset(sc);
855 MY_UNLOCK(sc);
856
857 /*
858 * Get station address
859 */
860 for (i = 0; i < ETHER_ADDR_LEN; ++i)
861 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
862
863 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
864 M_DEVBUF, M_NOWAIT);
865 if (sc->my_ldata_ptr == NULL) {
866 device_printf(dev, "no memory for list buffers!\n");
867 error = ENXIO;
868 goto release_irq;
869 }
870 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
871 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
872 roundptr = sc->my_ldata_ptr;
873 for (i = 0; i < 8; i++) {
874 if (round % 8) {
875 round++;
876 roundptr++;
877 } else
878 break;
879 }
880 sc->my_ldata = (struct my_list_data *) roundptr;
881 bzero(sc->my_ldata, sizeof(struct my_list_data));
882
883 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
884 if (ifp == NULL) {
885 device_printf(dev, "can not if_alloc()\n");
886 error = ENOSPC;
887 goto free_ldata;
888 }
889 ifp->if_softc = sc;
890 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
891 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
892 ifp->if_ioctl = my_ioctl;
893 ifp->if_start = my_start;
894 ifp->if_init = my_init;
895 ifp->if_baudrate = 10000000;
896 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
897 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
898 IFQ_SET_READY(&ifp->if_snd);
899
900 if (sc->my_info->my_did == MTD803ID)
901 sc->my_pinfo = my_phys;
902 else {
903 if (bootverbose)
904 device_printf(dev, "probing for a PHY\n");
905 MY_LOCK(sc);
906 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
907 if (bootverbose)
908 device_printf(dev, "checking address: %d\n", i);
909 sc->my_phy_addr = i;
910 phy_sts = my_phy_readreg(sc, PHY_BMSR);
911 if ((phy_sts != 0) && (phy_sts != 0xffff))
912 break;
913 else
914 phy_sts = 0;
915 }
916 if (phy_sts) {
917 phy_vid = my_phy_readreg(sc, PHY_VENID);
918 phy_did = my_phy_readreg(sc, PHY_DEVID);
919 if (bootverbose) {
920 device_printf(dev, "found PHY at address %d, ",
921 sc->my_phy_addr);
922 printf("vendor id: %x device id: %x\n",
923 phy_vid, phy_did);
924 }
925 p = my_phys;
926 while (p->my_vid) {
927 if (phy_vid == p->my_vid) {
928 sc->my_pinfo = p;
929 break;
930 }
931 p++;
932 }
933 if (sc->my_pinfo == NULL)
934 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
935 if (bootverbose)
936 device_printf(dev, "PHY type: %s\n",
937 sc->my_pinfo->my_name);
938 } else {
939 MY_UNLOCK(sc);
940 device_printf(dev, "MII without any phy!\n");
941 error = ENXIO;
942 goto free_if;
943 }
944 MY_UNLOCK(sc);
945 }
946
947 /* Do ifmedia setup. */
948 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
949 MY_LOCK(sc);
950 my_getmode_mii(sc);
951 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
952 media = sc->ifmedia.ifm_media;
953 my_stop(sc);
954 MY_UNLOCK(sc);
955 ifmedia_set(&sc->ifmedia, media);
956
957 ether_ifattach(ifp, eaddr);
958
959 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
960 NULL, my_intr, sc, &sc->my_intrhand);
961
962 if (error) {
963 device_printf(dev, "couldn't set up irq\n");
964 goto detach_if;
965 }
966
967 return (0);
968
969 detach_if:
970 ether_ifdetach(ifp);
971 free_if:
972 if_free(ifp);
973 free_ldata:
974 free(sc->my_ldata_ptr, M_DEVBUF);
975 release_irq:
976 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
977 release_io:
978 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
979 destroy_mutex:
980 mtx_destroy(&sc->my_mtx);
981 return (error);
982 }
983
984 static int
my_detach(device_t dev)985 my_detach(device_t dev)
986 {
987 struct my_softc *sc;
988 struct ifnet *ifp;
989
990 sc = device_get_softc(dev);
991 ifp = sc->my_ifp;
992 ether_ifdetach(ifp);
993 MY_LOCK(sc);
994 my_stop(sc);
995 MY_UNLOCK(sc);
996 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
997 callout_drain(&sc->my_watchdog);
998 callout_drain(&sc->my_autoneg_timer);
999
1000 if_free(ifp);
1001 free(sc->my_ldata_ptr, M_DEVBUF);
1002
1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1004 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1005 mtx_destroy(&sc->my_mtx);
1006 return (0);
1007 }
1008
1009
1010 /*
1011 * Initialize the transmit descriptors.
1012 */
1013 static int
my_list_tx_init(struct my_softc * sc)1014 my_list_tx_init(struct my_softc * sc)
1015 {
1016 struct my_chain_data *cd;
1017 struct my_list_data *ld;
1018 int i;
1019
1020 MY_LOCK_ASSERT(sc);
1021 cd = &sc->my_cdata;
1022 ld = sc->my_ldata;
1023 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1024 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1025 if (i == (MY_TX_LIST_CNT - 1))
1026 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1027 else
1028 cd->my_tx_chain[i].my_nextdesc =
1029 &cd->my_tx_chain[i + 1];
1030 }
1031 cd->my_tx_free = &cd->my_tx_chain[0];
1032 cd->my_tx_tail = cd->my_tx_head = NULL;
1033 return (0);
1034 }
1035
1036 /*
1037 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1038 * arrange the descriptors in a closed ring, so that the last descriptor
1039 * points back to the first.
1040 */
1041 static int
my_list_rx_init(struct my_softc * sc)1042 my_list_rx_init(struct my_softc * sc)
1043 {
1044 struct my_chain_data *cd;
1045 struct my_list_data *ld;
1046 int i;
1047
1048 MY_LOCK_ASSERT(sc);
1049 cd = &sc->my_cdata;
1050 ld = sc->my_ldata;
1051 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1052 cd->my_rx_chain[i].my_ptr =
1053 (struct my_desc *) & ld->my_rx_list[i];
1054 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1055 MY_UNLOCK(sc);
1056 return (ENOBUFS);
1057 }
1058 if (i == (MY_RX_LIST_CNT - 1)) {
1059 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1060 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1061 } else {
1062 cd->my_rx_chain[i].my_nextdesc =
1063 &cd->my_rx_chain[i + 1];
1064 ld->my_rx_list[i].my_next =
1065 vtophys(&ld->my_rx_list[i + 1]);
1066 }
1067 }
1068 cd->my_rx_head = &cd->my_rx_chain[0];
1069 return (0);
1070 }
1071
1072 /*
1073 * Initialize an RX descriptor and attach an MBUF cluster.
1074 */
1075 static int
my_newbuf(struct my_softc * sc,struct my_chain_onefrag * c)1076 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1077 {
1078 struct mbuf *m_new = NULL;
1079
1080 MY_LOCK_ASSERT(sc);
1081 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1082 if (m_new == NULL) {
1083 device_printf(sc->my_dev,
1084 "no memory for rx list -- packet dropped!\n");
1085 return (ENOBUFS);
1086 }
1087 MCLGET(m_new, M_NOWAIT);
1088 if (!(m_new->m_flags & M_EXT)) {
1089 device_printf(sc->my_dev,
1090 "no memory for rx list -- packet dropped!\n");
1091 m_freem(m_new);
1092 return (ENOBUFS);
1093 }
1094 c->my_mbuf = m_new;
1095 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1096 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1097 c->my_ptr->my_status = MY_OWNByNIC;
1098 return (0);
1099 }
1100
1101 /*
1102 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1103 * level protocols.
1104 */
1105 static void
my_rxeof(struct my_softc * sc)1106 my_rxeof(struct my_softc * sc)
1107 {
1108 struct ether_header *eh;
1109 struct mbuf *m;
1110 struct ifnet *ifp;
1111 struct my_chain_onefrag *cur_rx;
1112 int total_len = 0;
1113 u_int32_t rxstat;
1114
1115 MY_LOCK_ASSERT(sc);
1116 ifp = sc->my_ifp;
1117 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1118 & MY_OWNByNIC)) {
1119 cur_rx = sc->my_cdata.my_rx_head;
1120 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1121
1122 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1123 ifp->if_ierrors++;
1124 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1125 continue;
1126 }
1127 /* No errors; receive the packet. */
1128 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1129 total_len -= ETHER_CRC_LEN;
1130
1131 if (total_len < MINCLSIZE) {
1132 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1133 total_len, 0, ifp, NULL);
1134 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1135 if (m == NULL) {
1136 ifp->if_ierrors++;
1137 continue;
1138 }
1139 } else {
1140 m = cur_rx->my_mbuf;
1141 /*
1142 * Try to conjure up a new mbuf cluster. If that
1143 * fails, it means we have an out of memory condition
1144 * and should leave the buffer in place and continue.
1145 * This will result in a lost packet, but there's
1146 * little else we can do in this situation.
1147 */
1148 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1149 ifp->if_ierrors++;
1150 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1151 continue;
1152 }
1153 m->m_pkthdr.rcvif = ifp;
1154 m->m_pkthdr.len = m->m_len = total_len;
1155 }
1156 ifp->if_ipackets++;
1157 eh = mtod(m, struct ether_header *);
1158 #if NBPFILTER > 0
1159 /*
1160 * Handle BPF listeners. Let the BPF user see the packet, but
1161 * don't pass it up to the ether_input() layer unless it's a
1162 * broadcast packet, multicast packet, matches our ethernet
1163 * address or the interface is in promiscuous mode.
1164 */
1165 if (bpf_peers_present(ifp->if_bpf)) {
1166 bpf_mtap(ifp->if_bpf, m);
1167 if (ifp->if_flags & IFF_PROMISC &&
1168 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1169 ETHER_ADDR_LEN) &&
1170 (eh->ether_dhost[0] & 1) == 0)) {
1171 m_freem(m);
1172 continue;
1173 }
1174 }
1175 #endif
1176 MY_UNLOCK(sc);
1177 (*ifp->if_input)(ifp, m);
1178 MY_LOCK(sc);
1179 }
1180 return;
1181 }
1182
1183
1184 /*
1185 * A frame was downloaded to the chip. It's safe for us to clean up the list
1186 * buffers.
1187 */
1188 static void
my_txeof(struct my_softc * sc)1189 my_txeof(struct my_softc * sc)
1190 {
1191 struct my_chain *cur_tx;
1192 struct ifnet *ifp;
1193
1194 MY_LOCK_ASSERT(sc);
1195 ifp = sc->my_ifp;
1196 /* Clear the timeout timer. */
1197 sc->my_timer = 0;
1198 if (sc->my_cdata.my_tx_head == NULL) {
1199 return;
1200 }
1201 /*
1202 * Go through our tx list and free mbufs for those frames that have
1203 * been transmitted.
1204 */
1205 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1206 u_int32_t txstat;
1207
1208 cur_tx = sc->my_cdata.my_tx_head;
1209 txstat = MY_TXSTATUS(cur_tx);
1210 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1211 break;
1212 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1213 if (txstat & MY_TXERR) {
1214 ifp->if_oerrors++;
1215 if (txstat & MY_EC) /* excessive collision */
1216 ifp->if_collisions++;
1217 if (txstat & MY_LC) /* late collision */
1218 ifp->if_collisions++;
1219 }
1220 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1221 MY_NCRShift;
1222 }
1223 ifp->if_opackets++;
1224 m_freem(cur_tx->my_mbuf);
1225 cur_tx->my_mbuf = NULL;
1226 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1227 sc->my_cdata.my_tx_head = NULL;
1228 sc->my_cdata.my_tx_tail = NULL;
1229 break;
1230 }
1231 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1232 }
1233 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1234 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1235 }
1236 return;
1237 }
1238
1239 /*
1240 * TX 'end of channel' interrupt handler.
1241 */
1242 static void
my_txeoc(struct my_softc * sc)1243 my_txeoc(struct my_softc * sc)
1244 {
1245 struct ifnet *ifp;
1246
1247 MY_LOCK_ASSERT(sc);
1248 ifp = sc->my_ifp;
1249 sc->my_timer = 0;
1250 if (sc->my_cdata.my_tx_head == NULL) {
1251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1252 sc->my_cdata.my_tx_tail = NULL;
1253 if (sc->my_want_auto)
1254 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1255 } else {
1256 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1257 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1258 sc->my_timer = 5;
1259 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1260 }
1261 }
1262 return;
1263 }
1264
1265 static void
my_intr(void * arg)1266 my_intr(void *arg)
1267 {
1268 struct my_softc *sc;
1269 struct ifnet *ifp;
1270 u_int32_t status;
1271
1272 sc = arg;
1273 MY_LOCK(sc);
1274 ifp = sc->my_ifp;
1275 if (!(ifp->if_flags & IFF_UP)) {
1276 MY_UNLOCK(sc);
1277 return;
1278 }
1279 /* Disable interrupts. */
1280 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1281
1282 for (;;) {
1283 status = CSR_READ_4(sc, MY_ISR);
1284 status &= MY_INTRS;
1285 if (status)
1286 CSR_WRITE_4(sc, MY_ISR, status);
1287 else
1288 break;
1289
1290 if (status & MY_RI) /* receive interrupt */
1291 my_rxeof(sc);
1292
1293 if ((status & MY_RBU) || (status & MY_RxErr)) {
1294 /* rx buffer unavailable or rx error */
1295 ifp->if_ierrors++;
1296 #ifdef foo
1297 my_stop(sc);
1298 my_reset(sc);
1299 my_init_locked(sc);
1300 #endif
1301 }
1302 if (status & MY_TI) /* tx interrupt */
1303 my_txeof(sc);
1304 if (status & MY_ETI) /* tx early interrupt */
1305 my_txeof(sc);
1306 if (status & MY_TBU) /* tx buffer unavailable */
1307 my_txeoc(sc);
1308
1309 #if 0 /* 90/1/18 delete */
1310 if (status & MY_FBE) {
1311 my_reset(sc);
1312 my_init_locked(sc);
1313 }
1314 #endif
1315
1316 }
1317
1318 /* Re-enable interrupts. */
1319 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1320 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1321 my_start_locked(ifp);
1322 MY_UNLOCK(sc);
1323 return;
1324 }
1325
1326 /*
1327 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1328 * pointers to the fragment pointers.
1329 */
1330 static int
my_encap(struct my_softc * sc,struct my_chain * c,struct mbuf * m_head)1331 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1332 {
1333 struct my_desc *f = NULL;
1334 int total_len;
1335 struct mbuf *m, *m_new = NULL;
1336
1337 MY_LOCK_ASSERT(sc);
1338 /* calculate the total tx pkt length */
1339 total_len = 0;
1340 for (m = m_head; m != NULL; m = m->m_next)
1341 total_len += m->m_len;
1342 /*
1343 * Start packing the mbufs in this chain into the fragment pointers.
1344 * Stop when we run out of fragments or hit the end of the mbuf
1345 * chain.
1346 */
1347 m = m_head;
1348 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1349 if (m_new == NULL) {
1350 device_printf(sc->my_dev, "no memory for tx list");
1351 return (1);
1352 }
1353 if (m_head->m_pkthdr.len > MHLEN) {
1354 MCLGET(m_new, M_NOWAIT);
1355 if (!(m_new->m_flags & M_EXT)) {
1356 m_freem(m_new);
1357 device_printf(sc->my_dev, "no memory for tx list");
1358 return (1);
1359 }
1360 }
1361 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1362 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1363 m_freem(m_head);
1364 m_head = m_new;
1365 f = &c->my_ptr->my_frag[0];
1366 f->my_status = 0;
1367 f->my_data = vtophys(mtod(m_new, caddr_t));
1368 total_len = m_new->m_len;
1369 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1370 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1371 f->my_ctl |= total_len; /* buffer size */
1372 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1373 if (sc->my_info->my_did == MTD891ID)
1374 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1375 c->my_mbuf = m_head;
1376 c->my_lastdesc = 0;
1377 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1378 return (0);
1379 }
1380
1381 /*
1382 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1383 * to the mbuf data regions directly in the transmit lists. We also save a
1384 * copy of the pointers since the transmit list fragment pointers are
1385 * physical addresses.
1386 */
1387 static void
my_start(struct ifnet * ifp)1388 my_start(struct ifnet * ifp)
1389 {
1390 struct my_softc *sc;
1391
1392 sc = ifp->if_softc;
1393 MY_LOCK(sc);
1394 my_start_locked(ifp);
1395 MY_UNLOCK(sc);
1396 }
1397
1398 static void
my_start_locked(struct ifnet * ifp)1399 my_start_locked(struct ifnet * ifp)
1400 {
1401 struct my_softc *sc;
1402 struct mbuf *m_head = NULL;
1403 struct my_chain *cur_tx = NULL, *start_tx;
1404
1405 sc = ifp->if_softc;
1406 MY_LOCK_ASSERT(sc);
1407 if (sc->my_autoneg) {
1408 sc->my_tx_pend = 1;
1409 return;
1410 }
1411 /*
1412 * Check for an available queue slot. If there are none, punt.
1413 */
1414 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1415 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1416 return;
1417 }
1418 start_tx = sc->my_cdata.my_tx_free;
1419 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1420 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1421 if (m_head == NULL)
1422 break;
1423
1424 /* Pick a descriptor off the free list. */
1425 cur_tx = sc->my_cdata.my_tx_free;
1426 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1427
1428 /* Pack the data into the descriptor. */
1429 my_encap(sc, cur_tx, m_head);
1430
1431 if (cur_tx != start_tx)
1432 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1433 #if NBPFILTER > 0
1434 /*
1435 * If there's a BPF listener, bounce a copy of this frame to
1436 * him.
1437 */
1438 BPF_MTAP(ifp, cur_tx->my_mbuf);
1439 #endif
1440 }
1441 /*
1442 * If there are no packets queued, bail.
1443 */
1444 if (cur_tx == NULL) {
1445 return;
1446 }
1447 /*
1448 * Place the request for the upload interrupt in the last descriptor
1449 * in the chain. This way, if we're chaining several packets at once,
1450 * we'll only get an interrupt once for the whole chain rather than
1451 * once for each packet.
1452 */
1453 MY_TXCTL(cur_tx) |= MY_TXIC;
1454 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1455 sc->my_cdata.my_tx_tail = cur_tx;
1456 if (sc->my_cdata.my_tx_head == NULL)
1457 sc->my_cdata.my_tx_head = start_tx;
1458 MY_TXOWN(start_tx) = MY_OWNByNIC;
1459 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1460
1461 /*
1462 * Set a timeout in case the chip goes out to lunch.
1463 */
1464 sc->my_timer = 5;
1465 return;
1466 }
1467
1468 static void
my_init(void * xsc)1469 my_init(void *xsc)
1470 {
1471 struct my_softc *sc = xsc;
1472
1473 MY_LOCK(sc);
1474 my_init_locked(sc);
1475 MY_UNLOCK(sc);
1476 }
1477
1478 static void
my_init_locked(struct my_softc * sc)1479 my_init_locked(struct my_softc *sc)
1480 {
1481 struct ifnet *ifp = sc->my_ifp;
1482 u_int16_t phy_bmcr = 0;
1483
1484 MY_LOCK_ASSERT(sc);
1485 if (sc->my_autoneg) {
1486 return;
1487 }
1488 if (sc->my_pinfo != NULL)
1489 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1490 /*
1491 * Cancel pending I/O and free all RX/TX buffers.
1492 */
1493 my_stop(sc);
1494 my_reset(sc);
1495
1496 /*
1497 * Set cache alignment and burst length.
1498 */
1499 #if 0 /* 89/9/1 modify, */
1500 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1501 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1502 #endif
1503 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1504 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1505 /*
1506 * 89/12/29 add, for mtd891,
1507 */
1508 if (sc->my_info->my_did == MTD891ID) {
1509 MY_SETBIT(sc, MY_BCR, MY_PROG);
1510 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1511 }
1512 my_setcfg(sc, phy_bmcr);
1513 /* Init circular RX list. */
1514 if (my_list_rx_init(sc) == ENOBUFS) {
1515 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1516 my_stop(sc);
1517 return;
1518 }
1519 /* Init TX descriptors. */
1520 my_list_tx_init(sc);
1521
1522 /* If we want promiscuous mode, set the allframes bit. */
1523 if (ifp->if_flags & IFF_PROMISC)
1524 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1525 else
1526 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1527
1528 /*
1529 * Set capture broadcast bit to capture broadcast frames.
1530 */
1531 if (ifp->if_flags & IFF_BROADCAST)
1532 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1533 else
1534 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1535
1536 /*
1537 * Program the multicast filter, if necessary.
1538 */
1539 my_setmulti(sc);
1540
1541 /*
1542 * Load the address of the RX list.
1543 */
1544 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1545 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1546
1547 /*
1548 * Enable interrupts.
1549 */
1550 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1551 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1552
1553 /* Enable receiver and transmitter. */
1554 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1555 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1556 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1557 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1558
1559 /* Restore state of BMCR */
1560 if (sc->my_pinfo != NULL)
1561 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1562 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1563 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1564
1565 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1566 return;
1567 }
1568
1569 /*
1570 * Set media options.
1571 */
1572
1573 static int
my_ifmedia_upd(struct ifnet * ifp)1574 my_ifmedia_upd(struct ifnet * ifp)
1575 {
1576 struct my_softc *sc;
1577 struct ifmedia *ifm;
1578
1579 sc = ifp->if_softc;
1580 MY_LOCK(sc);
1581 ifm = &sc->ifmedia;
1582 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1583 MY_UNLOCK(sc);
1584 return (EINVAL);
1585 }
1586 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1587 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1588 else
1589 my_setmode_mii(sc, ifm->ifm_media);
1590 MY_UNLOCK(sc);
1591 return (0);
1592 }
1593
1594 /*
1595 * Report current media status.
1596 */
1597
1598 static void
my_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1599 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1600 {
1601 struct my_softc *sc;
1602 u_int16_t advert = 0, ability = 0;
1603
1604 sc = ifp->if_softc;
1605 MY_LOCK(sc);
1606 ifmr->ifm_active = IFM_ETHER;
1607 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1608 #if 0 /* this version did not support 1000M, */
1609 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1610 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1611 #endif
1612 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1613 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1614 else
1615 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1616 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1617 ifmr->ifm_active |= IFM_FDX;
1618 else
1619 ifmr->ifm_active |= IFM_HDX;
1620
1621 MY_UNLOCK(sc);
1622 return;
1623 }
1624 ability = my_phy_readreg(sc, PHY_LPAR);
1625 advert = my_phy_readreg(sc, PHY_ANAR);
1626
1627 #if 0 /* this version did not support 1000M, */
1628 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1629 ability2 = my_phy_readreg(sc, PHY_1000SR);
1630 if (ability2 & PHY_1000SR_1000BTXFULL) {
1631 advert = 0;
1632 ability = 0;
1633 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1634 } else if (ability & PHY_1000SR_1000BTXHALF) {
1635 advert = 0;
1636 ability = 0;
1637 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1638 }
1639 }
1640 #endif
1641 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1642 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1643 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1644 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1645 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1646 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1647 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1648 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1649 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1650 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1651 MY_UNLOCK(sc);
1652 return;
1653 }
1654
1655 static int
my_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1656 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1657 {
1658 struct my_softc *sc = ifp->if_softc;
1659 struct ifreq *ifr = (struct ifreq *) data;
1660 int error;
1661
1662 switch (command) {
1663 case SIOCSIFFLAGS:
1664 MY_LOCK(sc);
1665 if (ifp->if_flags & IFF_UP)
1666 my_init_locked(sc);
1667 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1668 my_stop(sc);
1669 MY_UNLOCK(sc);
1670 error = 0;
1671 break;
1672 case SIOCADDMULTI:
1673 case SIOCDELMULTI:
1674 MY_LOCK(sc);
1675 my_setmulti(sc);
1676 MY_UNLOCK(sc);
1677 error = 0;
1678 break;
1679 case SIOCGIFMEDIA:
1680 case SIOCSIFMEDIA:
1681 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1682 break;
1683 default:
1684 error = ether_ioctl(ifp, command, data);
1685 break;
1686 }
1687 return (error);
1688 }
1689
1690 static void
my_watchdog(void * arg)1691 my_watchdog(void *arg)
1692 {
1693 struct my_softc *sc;
1694 struct ifnet *ifp;
1695
1696 sc = arg;
1697 MY_LOCK_ASSERT(sc);
1698 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1699 if (sc->my_timer == 0 || --sc->my_timer > 0)
1700 return;
1701
1702 ifp = sc->my_ifp;
1703 ifp->if_oerrors++;
1704 if_printf(ifp, "watchdog timeout\n");
1705 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1706 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1707 my_stop(sc);
1708 my_reset(sc);
1709 my_init_locked(sc);
1710 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1711 my_start_locked(ifp);
1712 }
1713
1714
1715 /*
1716 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1717 */
1718 static void
my_stop(struct my_softc * sc)1719 my_stop(struct my_softc * sc)
1720 {
1721 register int i;
1722 struct ifnet *ifp;
1723
1724 MY_LOCK_ASSERT(sc);
1725 ifp = sc->my_ifp;
1726
1727 callout_stop(&sc->my_autoneg_timer);
1728 callout_stop(&sc->my_watchdog);
1729
1730 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1731 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1732 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1733 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1734
1735 /*
1736 * Free data in the RX lists.
1737 */
1738 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1739 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1740 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1741 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1742 }
1743 }
1744 bzero((char *)&sc->my_ldata->my_rx_list,
1745 sizeof(sc->my_ldata->my_rx_list));
1746 /*
1747 * Free the TX list buffers.
1748 */
1749 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1750 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1751 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1752 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1753 }
1754 }
1755 bzero((char *)&sc->my_ldata->my_tx_list,
1756 sizeof(sc->my_ldata->my_tx_list));
1757 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1758 return;
1759 }
1760
1761 /*
1762 * Stop all chip I/O so that the kernel's probe routines don't get confused
1763 * by errant DMAs when rebooting.
1764 */
1765 static int
my_shutdown(device_t dev)1766 my_shutdown(device_t dev)
1767 {
1768 struct my_softc *sc;
1769
1770 sc = device_get_softc(dev);
1771 MY_LOCK(sc);
1772 my_stop(sc);
1773 MY_UNLOCK(sc);
1774 return 0;
1775 }
1776