1 /*-
2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * Driver for Dallas/Maxim DS13xx real-time clock/calendar chips:
32 *
33 * - DS1307 = Original/basic rtc + 56 bytes ram; 5v only.
34 * - DS1308 = Updated 1307, available in 1.8v-5v variations.
35 * - DS1337 = Like 1308, integrated xtal, 32khz output on at powerup.
36 * - DS1338 = Like 1308, integrated xtal.
37 * - DS1339 = Like 1337, integrated xtal, integrated trickle charger.
38 * - DS1340 = Like 1338, ST M41T00 compatible.
39 * - DS1341 = Like 1338, can slave-sync osc to external clock signal.
40 * - DS1342 = Like 1341 but requires different xtal.
41 * - DS1371 = 32-bit binary counter, watchdog timer.
42 * - DS1372 = 32-bit binary counter, 64-bit unique id in rom.
43 * - DS1374 = 32-bit binary counter, watchdog timer, trickle charger.
44 * - DS1375 = Like 1308 but only 16 bytes ram.
45 * - DS1388 = Rtc, watchdog timer, 512 bytes eeprom (not sram).
46 *
47 * This driver supports only basic timekeeping functions. It provides no access
48 * to or control over any other functionality provided by the chips.
49 */
50
51 #include "opt_platform.h"
52
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/bus.h>
56 #include <sys/clock.h>
57 #include <sys/endian.h>
58 #include <sys/kernel.h>
59 #include <sys/libkern.h>
60 #include <sys/module.h>
61
62 #include <dev/iicbus/iicbus.h>
63 #include <dev/iicbus/iiconf.h>
64 #ifdef FDT
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
68 #endif
69
70 #include "clock_if.h"
71 #include "iicbus_if.h"
72
73 /*
74 * I2C address 1101 000x
75 */
76 #define DS13xx_ADDR 0xd0
77
78 /*
79 * Registers, bits within them, and masks for the various chip types.
80 */
81
82 #define DS13xx_R_NONE 0xff /* Placeholder */
83
84 #define DS130x_R_CONTROL 0x07
85 #define DS133x_R_CONTROL 0x0e
86 #define DS1340_R_CONTROL 0x07
87 #define DS1341_R_CONTROL 0x0e
88 #define DS1371_R_CONTROL 0x07
89 #define DS1372_R_CONTROL 0x07
90 #define DS1374_R_CONTROL 0x07
91 #define DS1375_R_CONTROL 0x0e
92 #define DS1388_R_CONTROL 0x0c
93
94 #define DS13xx_R_SECOND 0x00
95 #define DS1388_R_SECOND 0x01
96
97 #define DS130x_R_STATUS DS13xx_R_NONE
98 #define DS133x_R_STATUS 0x0f
99 #define DS1340_R_STATUS 0x09
100 #define DS137x_R_STATUS 0x08
101 #define DS1388_R_STATUS 0x0b
102
103 #define DS13xx_B_STATUS_OSF 0x80 /* OSF is 1<<7 in status and sec regs */
104 #define DS13xx_B_HOUR_AMPM 0x40 /* AMPM mode is bit 1<<6 */
105 #define DS13xx_B_HOUR_PM 0x20 /* PM hours indicated by 1<<5 */
106 #define DS13xx_B_MONTH_CENTURY 0x80 /* 21st century indicated by 1<<7 */
107
108 #define DS13xx_M_SECOND 0x7f /* Masks for all BCD time regs... */
109 #define DS13xx_M_MINUTE 0x7f
110 #define DS13xx_M_12HOUR 0x1f
111 #define DS13xx_M_24HOUR 0x3f
112 #define DS13xx_M_DAY 0x3f
113 #define DS13xx_M_MONTH 0x1f
114 #define DS13xx_M_YEAR 0xff
115
116 /*
117 * The chip types we support.
118 */
119 enum {
120 TYPE_NONE,
121 TYPE_DS1307,
122 TYPE_DS1308,
123 TYPE_DS1337,
124 TYPE_DS1338,
125 TYPE_DS1339,
126 TYPE_DS1340,
127 TYPE_DS1341,
128 TYPE_DS1342,
129 TYPE_DS1371,
130 TYPE_DS1372,
131 TYPE_DS1374,
132 TYPE_DS1375,
133 TYPE_DS1388,
134
135 TYPE_COUNT
136 };
137 static const char *desc_strings[] = {
138 "",
139 "Dallas/Maxim DS1307 RTC",
140 "Dallas/Maxim DS1308 RTC",
141 "Dallas/Maxim DS1337 RTC",
142 "Dallas/Maxim DS1338 RTC",
143 "Dallas/Maxim DS1339 RTC",
144 "Dallas/Maxim DS1340 RTC",
145 "Dallas/Maxim DS1341 RTC",
146 "Dallas/Maxim DS1342 RTC",
147 "Dallas/Maxim DS1371 RTC",
148 "Dallas/Maxim DS1372 RTC",
149 "Dallas/Maxim DS1374 RTC",
150 "Dallas/Maxim DS1375 RTC",
151 "Dallas/Maxim DS1388 RTC",
152 };
153 CTASSERT(nitems(desc_strings) == TYPE_COUNT);
154
155 /*
156 * The time registers in the order they are laid out in hardware.
157 */
158 struct time_regs {
159 uint8_t sec, min, hour, wday, day, month, year;
160 };
161
162 struct ds13rtc_softc {
163 device_t dev;
164 device_t busdev;
165 u_int chiptype; /* Type of DS13xx chip */
166 uint8_t secaddr; /* Address of seconds register */
167 uint8_t osfaddr; /* Address of register with OSF */
168 bool use_ampm; /* Use AM/PM mode. */
169 bool use_century; /* Use the Century bit. */
170 bool is_binary_counter; /* Chip has 32-bit binary counter. */
171 };
172
173 /*
174 * We use the compat_data table to look up hint strings in the non-FDT case, so
175 * define the struct locally when we don't get it from ofw_bus_subr.h.
176 */
177 #ifdef FDT
178 typedef struct ofw_compat_data ds13_compat_data;
179 #else
180 typedef struct {
181 const char *ocd_str;
182 uintptr_t ocd_data;
183 } ds13_compat_data;
184 #endif
185
186 static ds13_compat_data compat_data[] = {
187 {"dallas,ds1307", TYPE_DS1307},
188 {"dallas,ds1308", TYPE_DS1308},
189 {"dallas,ds1337", TYPE_DS1337},
190 {"dallas,ds1338", TYPE_DS1338},
191 {"dallas,ds1339", TYPE_DS1339},
192 {"dallas,ds1340", TYPE_DS1340},
193 {"dallas,ds1341", TYPE_DS1341},
194 {"dallas,ds1342", TYPE_DS1342},
195 {"dallas,ds1371", TYPE_DS1371},
196 {"dallas,ds1372", TYPE_DS1372},
197 {"dallas,ds1374", TYPE_DS1374},
198 {"dallas,ds1375", TYPE_DS1375},
199 {"dallas,ds1388", TYPE_DS1388},
200
201 {NULL, TYPE_NONE},
202 };
203
204 static int
read_reg(struct ds13rtc_softc * sc,uint8_t reg,uint8_t * val)205 read_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t *val)
206 {
207
208 return (iicdev_readfrom(sc->dev, reg, val, sizeof(*val), IIC_WAIT));
209 }
210
211 static int
write_reg(struct ds13rtc_softc * sc,uint8_t reg,uint8_t val)212 write_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t val)
213 {
214
215 return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), IIC_WAIT));
216 }
217
218 static int
read_timeregs(struct ds13rtc_softc * sc,struct time_regs * tregs)219 read_timeregs(struct ds13rtc_softc *sc, struct time_regs *tregs)
220 {
221 int err;
222
223 if ((err = iicdev_readfrom(sc->dev, sc->secaddr, tregs,
224 sizeof(*tregs), IIC_WAIT)) != 0)
225 return (err);
226
227 return (err);
228 }
229
230 static int
write_timeregs(struct ds13rtc_softc * sc,struct time_regs * tregs)231 write_timeregs(struct ds13rtc_softc *sc, struct time_regs *tregs)
232 {
233
234 return (iicdev_writeto(sc->dev, sc->secaddr, tregs,
235 sizeof(*tregs), IIC_WAIT));
236 }
237
238 static int
read_timeword(struct ds13rtc_softc * sc,time_t * secs)239 read_timeword(struct ds13rtc_softc *sc, time_t *secs)
240 {
241 int err;
242 uint8_t buf[4];
243
244 if ((err = iicdev_readfrom(sc->dev, sc->secaddr, buf, sizeof(buf),
245 IIC_WAIT)) == 0)
246 *secs = le32dec(buf);
247
248 return (err);
249 }
250
251 static int
write_timeword(struct ds13rtc_softc * sc,time_t secs)252 write_timeword(struct ds13rtc_softc *sc, time_t secs)
253 {
254 uint8_t buf[4];
255
256 le32enc(buf, (uint32_t)secs);
257 return (iicdev_writeto(sc->dev, sc->secaddr, buf, sizeof(buf),
258 IIC_WAIT));
259 }
260
261 static void
ds13rtc_start(void * arg)262 ds13rtc_start(void *arg)
263 {
264 struct ds13rtc_softc *sc;
265 uint8_t ctlreg, statreg;
266
267 sc = arg;
268
269 /*
270 * Every chip in this family can be usefully initialized by writing 0 to
271 * the control register, except DS1375 which has an external oscillator
272 * controlled by values in the ctlreg that we know nothing about, so
273 * we'd best leave them alone. For all other chips, writing 0 enables
274 * the oscillator, disables signals/outputs in battery-backed mode
275 * (saves power) and disables features like watchdog timers and alarms.
276 */
277 switch (sc->chiptype) {
278 case TYPE_DS1307:
279 case TYPE_DS1308:
280 case TYPE_DS1338:
281 case TYPE_DS1340:
282 case TYPE_DS1371:
283 case TYPE_DS1372:
284 case TYPE_DS1374:
285 ctlreg = DS130x_R_CONTROL;
286 break;
287 case TYPE_DS1337:
288 case TYPE_DS1339:
289 ctlreg = DS133x_R_CONTROL;
290 break;
291 case TYPE_DS1341:
292 case TYPE_DS1342:
293 ctlreg = DS1341_R_CONTROL;
294 break;
295 case TYPE_DS1375:
296 ctlreg = DS13xx_R_NONE;
297 break;
298 case TYPE_DS1388:
299 ctlreg = DS1388_R_CONTROL;
300 break;
301 default:
302 device_printf(sc->dev, "missing init code for this chiptype\n");
303 return;
304 }
305 if (ctlreg != DS13xx_R_NONE)
306 write_reg(sc, ctlreg, 0);
307
308 /*
309 * Common init. Read the OSF/CH status bit and report stopped clocks to
310 * the user. The status bit will be cleared the first time we write
311 * valid time to the chip (and must not be cleared before that).
312 */
313 if (read_reg(sc, sc->osfaddr, &statreg) != 0) {
314 device_printf(sc->dev, "cannot read RTC clock status bit\n");
315 return;
316 }
317 if (statreg & DS13xx_B_STATUS_OSF) {
318 device_printf(sc->dev,
319 "WARNING: RTC battery failed; time is invalid\n");
320 }
321
322 /*
323 * Figure out whether the chip is configured for AM/PM mode. On all
324 * chips that do AM/PM mode, the flag bit is in the hours register,
325 * which is secaddr+2.
326 */
327 if ((sc->chiptype != TYPE_DS1340) && !sc->is_binary_counter) {
328 if (read_reg(sc, sc->secaddr + 2, &statreg) != 0) {
329 device_printf(sc->dev,
330 "cannot read RTC clock AM/PM bit\n");
331 return;
332 }
333 if (statreg & DS13xx_B_HOUR_AMPM)
334 sc->use_ampm = true;
335 }
336
337 /*
338 * Everything looks good if we make it to here; register as an RTC.
339 * Schedule RTC updates to happen just after top-of-second.
340 */
341 clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
342 clock_schedule(sc->dev, 1);
343 }
344
345 static int
ds13rtc_gettime(device_t dev,struct timespec * ts)346 ds13rtc_gettime(device_t dev, struct timespec *ts)
347 {
348 struct bcd_clocktime bct;
349 struct time_regs tregs;
350 struct ds13rtc_softc *sc;
351 int err;
352 uint8_t statreg, hourmask;
353
354 sc = device_get_softc(dev);
355
356 /* Read the OSF/CH bit; if the clock stopped we can't provide time. */
357 if ((err = read_reg(sc, sc->osfaddr, &statreg)) != 0) {
358 return (err);
359 }
360 if (statreg & DS13xx_B_STATUS_OSF)
361 return (EINVAL); /* hardware is good, time is not. */
362
363 /* If the chip counts time in binary, we just read and return it. */
364 if (sc->is_binary_counter) {
365 ts->tv_nsec = 0;
366 return (read_timeword(sc, &ts->tv_sec));
367 }
368
369 /*
370 * Chip counts in BCD, read and decode it...
371 */
372 if ((err = read_timeregs(sc, &tregs)) != 0) {
373 device_printf(dev, "cannot read RTC time\n");
374 return (err);
375 }
376
377 if (sc->use_ampm)
378 hourmask = DS13xx_M_12HOUR;
379 else
380 hourmask = DS13xx_M_24HOUR;
381
382 bct.nsec = 0;
383 bct.ispm = tregs.hour & DS13xx_B_HOUR_PM;
384 bct.sec = tregs.sec & DS13xx_M_SECOND;
385 bct.min = tregs.min & DS13xx_M_MINUTE;
386 bct.hour = tregs.hour & hourmask;
387 bct.day = tregs.day & DS13xx_M_DAY;
388 bct.mon = tregs.month & DS13xx_M_MONTH;
389 bct.year = tregs.year & DS13xx_M_YEAR;
390
391 /*
392 * If this chip has a century bit, honor it. Otherwise let
393 * clock_ct_to_ts() infer the century from the 2-digit year.
394 */
395 if (sc->use_century)
396 bct.year += (tregs.month & DS13xx_B_MONTH_CENTURY) ? 0x100 : 0;
397
398 clock_dbgprint_bcd(sc->dev, CLOCK_DBG_READ, &bct);
399 err = clock_bcd_to_ts(&bct, ts, sc->use_ampm);
400
401 return (err);
402 }
403
404 static int
ds13rtc_settime(device_t dev,struct timespec * ts)405 ds13rtc_settime(device_t dev, struct timespec *ts)
406 {
407 struct bcd_clocktime bct;
408 struct time_regs tregs;
409 struct ds13rtc_softc *sc;
410 int err;
411 uint8_t cflag, statreg, pmflags;
412
413 sc = device_get_softc(dev);
414
415 /*
416 * We request a timespec with no resolution-adjustment. That also
417 * disables utc adjustment, so apply that ourselves.
418 */
419 ts->tv_sec -= utc_offset();
420
421 /* If the chip counts time in binary, store tv_sec and we're done. */
422 if (sc->is_binary_counter)
423 return (write_timeword(sc, ts->tv_sec));
424
425 clock_ts_to_bcd(ts, &bct, sc->use_ampm);
426 clock_dbgprint_bcd(sc->dev, CLOCK_DBG_WRITE, &bct);
427
428 /* If the chip is in AMPM mode deal with the PM flag. */
429 pmflags = 0;
430 if (sc->use_ampm) {
431 pmflags = DS13xx_B_HOUR_AMPM;
432 if (bct.ispm)
433 pmflags |= DS13xx_B_HOUR_PM;
434 }
435
436 /* If the chip has a century bit, set it as needed. */
437 cflag = 0;
438 if (sc->use_century) {
439 if (bct.year >= 2000)
440 cflag |= DS13xx_B_MONTH_CENTURY;
441 }
442
443 tregs.sec = bct.sec;
444 tregs.min = bct.min;
445 tregs.hour = bct.hour | pmflags;
446 tregs.day = bct.day;
447 tregs.month = bct.mon | cflag;
448 tregs.year = bct.year & 0xff;
449 tregs.wday = bct.dow;
450
451 /*
452 * Set the time. Reset the OSF bit if it is on and it is not part of
453 * the time registers (in which case writing time resets it).
454 */
455 if ((err = write_timeregs(sc, &tregs)) != 0)
456 goto errout;
457 if (sc->osfaddr != sc->secaddr) {
458 if ((err = read_reg(sc, sc->osfaddr, &statreg)) != 0)
459 goto errout;
460 if (statreg & DS13xx_B_STATUS_OSF) {
461 statreg &= ~DS13xx_B_STATUS_OSF;
462 err = write_reg(sc, sc->osfaddr, statreg);
463 }
464 }
465
466 errout:
467
468 if (err != 0)
469 device_printf(dev, "cannot update RTC time\n");
470
471 return (err);
472 }
473
474 static int
ds13rtc_get_chiptype(device_t dev)475 ds13rtc_get_chiptype(device_t dev)
476 {
477 #ifdef FDT
478
479 return (ofw_bus_search_compatible(dev, compat_data)->ocd_data);
480 #else
481 ds13_compat_data *cdata;
482 const char *htype;
483
484 /*
485 * We can only attach if provided a chiptype hint string.
486 */
487 if (resource_string_value(device_get_name(dev),
488 device_get_unit(dev), "compatible", &htype) != 0)
489 return (TYPE_NONE);
490
491 /*
492 * Loop through the ofw compat data comparing the hinted chip type to
493 * the compat strings.
494 */
495 for (cdata = compat_data; cdata->ocd_str != NULL; ++cdata) {
496 if (strcmp(htype, cdata->ocd_str) == 0)
497 break;
498 }
499 return (cdata->ocd_data);
500 #endif
501 }
502
503 static int
ds13rtc_probe(device_t dev)504 ds13rtc_probe(device_t dev)
505 {
506 int chiptype, goodrv;
507
508 #ifdef FDT
509 if (!ofw_bus_status_okay(dev))
510 return (ENXIO);
511 goodrv = BUS_PROBE_GENERIC;
512 #else
513 goodrv = BUS_PROBE_NOWILDCARD;
514 #endif
515
516 chiptype = ds13rtc_get_chiptype(dev);
517 if (chiptype == TYPE_NONE)
518 return (ENXIO);
519
520 device_set_desc(dev, desc_strings[chiptype]);
521 return (goodrv);
522 }
523
524 static int
ds13rtc_attach(device_t dev)525 ds13rtc_attach(device_t dev)
526 {
527 struct ds13rtc_softc *sc;
528
529 sc = device_get_softc(dev);
530 sc->dev = dev;
531 sc->busdev = device_get_parent(dev);
532
533 /*
534 * We need to know what kind of chip we're driving.
535 */
536 if ((sc->chiptype = ds13rtc_get_chiptype(dev)) == TYPE_NONE) {
537 device_printf(dev, "impossible: cannot determine chip type\n");
538 return (ENXIO);
539 }
540
541 /* The seconds register is in the same place on all except DS1388. */
542 if (sc->chiptype == TYPE_DS1388)
543 sc->secaddr = DS1388_R_SECOND;
544 else
545 sc->secaddr = DS13xx_R_SECOND;
546
547 /*
548 * The OSF/CH (osc failed/clock-halted) bit appears in different
549 * registers for different chip types. The DS1375 has no OSF indicator
550 * because it has no internal oscillator; we just point to an always-
551 * zero bit in the status register for that chip.
552 */
553 switch (sc->chiptype) {
554 case TYPE_DS1307:
555 case TYPE_DS1308:
556 case TYPE_DS1338:
557 sc->osfaddr = DS13xx_R_SECOND;
558 break;
559 case TYPE_DS1337:
560 case TYPE_DS1339:
561 case TYPE_DS1341:
562 case TYPE_DS1342:
563 case TYPE_DS1375:
564 sc->osfaddr = DS133x_R_STATUS;
565 sc->use_century = true;
566 break;
567 case TYPE_DS1340:
568 sc->osfaddr = DS1340_R_STATUS;
569 break;
570 case TYPE_DS1371:
571 case TYPE_DS1372:
572 case TYPE_DS1374:
573 sc->osfaddr = DS137x_R_STATUS;
574 sc->is_binary_counter = true;
575 break;
576 case TYPE_DS1388:
577 sc->osfaddr = DS1388_R_STATUS;
578 break;
579 }
580
581 /*
582 * We have to wait until interrupts are enabled. Sometimes I2C read
583 * and write only works when the interrupts are available.
584 */
585 config_intrhook_oneshot(ds13rtc_start, sc);
586
587 return (0);
588 }
589
590 static int
ds13rtc_detach(device_t dev)591 ds13rtc_detach(device_t dev)
592 {
593
594 clock_unregister(dev);
595 return (0);
596 }
597
598 static device_method_t ds13rtc_methods[] = {
599 DEVMETHOD(device_probe, ds13rtc_probe),
600 DEVMETHOD(device_attach, ds13rtc_attach),
601 DEVMETHOD(device_detach, ds13rtc_detach),
602
603 DEVMETHOD(clock_gettime, ds13rtc_gettime),
604 DEVMETHOD(clock_settime, ds13rtc_settime),
605
606 DEVMETHOD_END
607 };
608
609 static driver_t ds13rtc_driver = {
610 "ds13rtc",
611 ds13rtc_methods,
612 sizeof(struct ds13rtc_softc),
613 };
614
615 static devclass_t ds13rtc_devclass;
616
617 DRIVER_MODULE(ds13rtc, iicbus, ds13rtc_driver, ds13rtc_devclass, NULL, NULL);
618 MODULE_VERSION(ds13rtc, 1);
619 MODULE_DEPEND(ds13rtc, iicbus, IICBB_MINVER, IICBB_PREFVER, IICBB_MAXVER);
620