1 /* $NetBSD: pl181.c,v 1.9 2021/08/07 16:19:12 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pl181.c,v 1.9 2021/08/07 16:19:12 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38
39 #include <dev/sdmmc/sdmmcvar.h>
40 #include <dev/sdmmc/sdmmcchip.h>
41 #include <dev/sdmmc/sdmmc_ioreg.h>
42
43 #include <dev/ic/pl181reg.h>
44 #include <dev/ic/pl181var.h>
45
46 /*
47 * Data length register is 16 bits for a maximum of 65535 bytes. Round
48 * maximum transfer size down to the nearest sector.
49 */
50 #define PLMMC_MAXXFER rounddown(65535, SDMMC_SECTOR_SIZE)
51
52 /*
53 * PL181 FIFO is 16 words deep (64 bytes)
54 */
55 #define PL181_FIFO_DEPTH 64
56
57 /*
58 * Data transfer IRQ status bits
59 */
60 #define PLMMC_INT_DATA_MASK \
61 (MMCI_INT_DATA_TIMEOUT|MMCI_INT_DATA_CRC_FAIL| \
62 MMCI_INT_TX_FIFO_EMPTY|MMCI_INT_TX_FIFO_HALF_EMPTY| \
63 MMCI_INT_RX_FIFO_FULL|MMCI_INT_RX_FIFO_HALF_FULL| \
64 MMCI_INT_DATA_END|MMCI_INT_DATA_BLOCK_END)
65 #define PLMMC_INT_CMD_MASK \
66 (MMCI_INT_CMD_TIMEOUT|MMCI_INT_CMD_RESP_END)
67
68 static int plmmc_host_reset(sdmmc_chipset_handle_t);
69 static uint32_t plmmc_host_ocr(sdmmc_chipset_handle_t);
70 static int plmmc_host_maxblklen(sdmmc_chipset_handle_t);
71 static int plmmc_card_detect(sdmmc_chipset_handle_t);
72 static int plmmc_write_protect(sdmmc_chipset_handle_t);
73 static int plmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
74 static int plmmc_bus_clock(sdmmc_chipset_handle_t, int);
75 static int plmmc_bus_width(sdmmc_chipset_handle_t, int);
76 static int plmmc_bus_rod(sdmmc_chipset_handle_t, int);
77 static void plmmc_exec_command(sdmmc_chipset_handle_t,
78 struct sdmmc_command *);
79 static void plmmc_card_enable_intr(sdmmc_chipset_handle_t, int);
80 static void plmmc_card_intr_ack(sdmmc_chipset_handle_t);
81
82 static int plmmc_wait_cmd(struct plmmc_softc *);
83 static int plmmc_pio_transfer(struct plmmc_softc *,
84 struct sdmmc_command *, int);
85
86 static struct sdmmc_chip_functions plmmc_chip_functions = {
87 .host_reset = plmmc_host_reset,
88 .host_ocr = plmmc_host_ocr,
89 .host_maxblklen = plmmc_host_maxblklen,
90 .card_detect = plmmc_card_detect,
91 .write_protect = plmmc_write_protect,
92 .bus_power = plmmc_bus_power,
93 .bus_clock = plmmc_bus_clock,
94 .bus_width = plmmc_bus_width,
95 .bus_rod = plmmc_bus_rod,
96 .exec_command = plmmc_exec_command,
97 .card_enable_intr = plmmc_card_enable_intr,
98 .card_intr_ack = plmmc_card_intr_ack,
99 };
100
101 #define MMCI_WRITE(sc, reg, val) \
102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
103 #define MMCI_WRITE_MULTI(sc, reg, datap, cnt) \
104 bus_space_write_multi_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (datap), (cnt))
105 #define MMCI_READ(sc, reg) \
106 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
107 #define MMCI_READ_MULTI(sc, reg, datap, cnt) \
108 bus_space_read_multi_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (datap), (cnt))
109
110 void
plmmc_init(struct plmmc_softc * sc)111 plmmc_init(struct plmmc_softc *sc)
112 {
113 struct sdmmcbus_attach_args saa;
114
115 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_BIO);
116 cv_init(&sc->sc_intr_cv, "plmmcirq");
117
118 #ifdef PLMMC_DEBUG
119 device_printf(sc->sc_dev, "PeriphID %#x %#x %#x %#x\n",
120 MMCI_READ(sc, MMCI_PERIPH_ID0_REG),
121 MMCI_READ(sc, MMCI_PERIPH_ID1_REG),
122 MMCI_READ(sc, MMCI_PERIPH_ID2_REG),
123 MMCI_READ(sc, MMCI_PERIPH_ID3_REG));
124 device_printf(sc->sc_dev, "PCellID %#x %#x %#x %#x\n",
125 MMCI_READ(sc, MMCI_PCELL_ID0_REG),
126 MMCI_READ(sc, MMCI_PCELL_ID1_REG),
127 MMCI_READ(sc, MMCI_PCELL_ID2_REG),
128 MMCI_READ(sc, MMCI_PCELL_ID3_REG));
129 #endif
130
131 plmmc_bus_clock(sc, 400);
132 MMCI_WRITE(sc, MMCI_POWER_REG, 0);
133 delay(10000);
134 MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERUP);
135 delay(10000);
136 MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERON);
137 plmmc_host_reset(sc);
138
139 memset(&saa, 0, sizeof(saa));
140 saa.saa_busname = "sdmmc";
141 saa.saa_sct = &plmmc_chip_functions;
142 saa.saa_sch = sc;
143 saa.saa_clkmin = 400;
144 saa.saa_clkmax = sc->sc_max_freq > 0 ?
145 sc->sc_max_freq / 1000 : sc->sc_clock_freq / 1000;
146 saa.saa_caps = SMC_CAPS_4BIT_MODE;
147
148 sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL, CFARGS_NONE);
149 }
150
151 static int
plmmc_intr_xfer(struct plmmc_softc * sc,struct sdmmc_command * cmd)152 plmmc_intr_xfer(struct plmmc_softc *sc, struct sdmmc_command *cmd)
153 {
154 uint32_t len;
155
156 if (cmd == NULL) {
157 device_printf(sc->sc_dev, "TX/RX interrupt with no active transfer\n");
158 return EINVAL;
159 }
160
161 if (cmd->c_buf == NULL) {
162 return EINVAL;
163 }
164
165 const uint32_t fifo_cnt =
166 __SHIFTOUT(MMCI_READ(sc, MMCI_FIFO_CNT_REG), MMCI_FIFO_CNT) * 4;
167 if (fifo_cnt > sc->sc_fifo_resid) {
168 device_printf(sc->sc_dev, "FIFO counter is out of sync with active transfer\n");
169 return EIO;
170 }
171
172 if (cmd->c_flags & SCF_CMD_READ)
173 len = sc->sc_fifo_resid - fifo_cnt;
174 else
175 len = uimin(sc->sc_fifo_resid, PL181_FIFO_DEPTH);
176
177 if (len == 0)
178 return 0;
179
180 if (cmd->c_flags & SCF_CMD_READ)
181 MMCI_READ_MULTI(sc, MMCI_FIFO_REG, (uint32_t *)cmd->c_buf, len / 4);
182 else
183 MMCI_WRITE_MULTI(sc, MMCI_FIFO_REG, (uint32_t *)cmd->c_buf, len / 4);
184
185 sc->sc_fifo_resid -= len;
186 cmd->c_resid -= len;
187 cmd->c_buf += len;
188
189 return 0;
190 }
191
192 int
plmmc_intr(void * priv)193 plmmc_intr(void *priv)
194 {
195 struct plmmc_softc *sc = priv;
196 uint32_t status, mask;
197 int retry = 100000;
198
199 mutex_enter(&sc->sc_lock);
200
201 while (--retry > 0) {
202 status = MMCI_READ(sc, MMCI_STATUS_REG);
203 #ifdef PLMMC_DEBUG
204 printf("%s: MMCI_STATUS_REG = %#x\n", __func__, status);
205 #endif
206 if ((status & sc->sc_status_mask) == 0)
207 break;
208 MMCI_WRITE(sc, MMCI_CLEAR_REG, status);
209 sc->sc_intr_status |= status;
210
211 if (status & MMCI_INT_CMD_TIMEOUT)
212 break;
213
214 if (status & (MMCI_INT_DATA_TIMEOUT|MMCI_INT_DATA_CRC_FAIL)) {
215 device_printf(sc->sc_dev,
216 "data xfer error, status %08x\n", status);
217 break;
218 }
219
220 if (status & (MMCI_INT_TX_FIFO_EMPTY|MMCI_INT_TX_FIFO_HALF_EMPTY|
221 MMCI_INT_RX_FIFO_FULL|MMCI_INT_RX_FIFO_HALF_FULL|
222 MMCI_INT_DATA_END|MMCI_INT_DATA_BLOCK_END)) {
223
224 /* Data transfer in progress */
225 if (plmmc_intr_xfer(sc, sc->sc_cmd) == 0 &&
226 sc->sc_fifo_resid == 0) {
227 /* Disable data IRQs */
228 mask = MMCI_READ(sc, MMCI_MASK0_REG);
229 mask &= ~PLMMC_INT_DATA_MASK;
230 MMCI_WRITE(sc, MMCI_MASK0_REG, mask);
231 /* Ignore data status bits after transfer */
232 sc->sc_status_mask &= ~PLMMC_INT_DATA_MASK;
233 }
234 }
235
236 if (status & MMCI_INT_CMD_RESP_END)
237 cv_broadcast(&sc->sc_intr_cv);
238 }
239 if (retry == 0) {
240 device_printf(sc->sc_dev, "intr handler stuck, fifo resid %d, status %08x\n",
241 sc->sc_fifo_resid, MMCI_READ(sc, MMCI_STATUS_REG));
242 }
243
244 cv_broadcast(&sc->sc_intr_cv);
245 mutex_exit(&sc->sc_lock);
246
247 return 1;
248 }
249
250 static int
plmmc_wait_cmd(struct plmmc_softc * sc)251 plmmc_wait_cmd(struct plmmc_softc *sc)
252 {
253 int error = 0;
254
255 KASSERT(mutex_owned(&sc->sc_lock));
256
257 while (error == 0) {
258 if (sc->sc_intr_status & MMCI_INT_CMD_TIMEOUT) {
259 error = ETIMEDOUT;
260 break;
261 } else if (sc->sc_intr_status & MMCI_INT_CMD_RESP_END) {
262 break;
263 }
264
265 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_lock, hz * 2);
266 if (error != 0)
267 break;
268 }
269
270 return error;
271 }
272
273 static int
plmmc_pio_transfer(struct plmmc_softc * sc,struct sdmmc_command * cmd,int xferlen)274 plmmc_pio_transfer(struct plmmc_softc *sc, struct sdmmc_command *cmd,
275 int xferlen)
276 {
277 int error = 0;
278
279 while (sc->sc_fifo_resid > 0 && error == 0) {
280 error = cv_timedwait(&sc->sc_intr_cv,
281 &sc->sc_lock, hz * 5);
282 if (error != 0)
283 break;
284
285 if (sc->sc_intr_status & MMCI_INT_DATA_TIMEOUT)
286 error = ETIMEDOUT;
287 else if (sc->sc_intr_status & MMCI_INT_DATA_CRC_FAIL)
288 error = EIO;
289 }
290
291 return error;
292 }
293
294 static int
plmmc_host_reset(sdmmc_chipset_handle_t sch)295 plmmc_host_reset(sdmmc_chipset_handle_t sch)
296 {
297 struct plmmc_softc *sc = sch;
298
299 MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
300 MMCI_WRITE(sc, MMCI_MASK1_REG, 0);
301 MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
302
303 return 0;
304 }
305
306 static uint32_t
plmmc_host_ocr(sdmmc_chipset_handle_t sch)307 plmmc_host_ocr(sdmmc_chipset_handle_t sch)
308 {
309 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
310 }
311
312 static int
plmmc_host_maxblklen(sdmmc_chipset_handle_t sch)313 plmmc_host_maxblklen(sdmmc_chipset_handle_t sch)
314 {
315 return 2048;
316 }
317
318 static int
plmmc_card_detect(sdmmc_chipset_handle_t sch)319 plmmc_card_detect(sdmmc_chipset_handle_t sch)
320 {
321 return 1;
322 }
323
324 static int
plmmc_write_protect(sdmmc_chipset_handle_t sch)325 plmmc_write_protect(sdmmc_chipset_handle_t sch)
326 {
327 return 0;
328 }
329
330 static int
plmmc_bus_power(sdmmc_chipset_handle_t sch,uint32_t ocr)331 plmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
332 {
333 return 0;
334 }
335
336 static int
plmmc_bus_clock(sdmmc_chipset_handle_t sch,int freq)337 plmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
338 {
339 struct plmmc_softc *sc = sch;
340 u_int pll_freq, clk_div;
341 uint32_t clock;
342
343 clock = MMCI_CLOCK_PWRSAVE;
344 if (freq) {
345 pll_freq = sc->sc_clock_freq / 1000;
346 clk_div = (howmany(pll_freq, freq) >> 1) - 1;
347 clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);
348 clock |= MMCI_CLOCK_ENABLE;
349 }
350 MMCI_WRITE(sc, MMCI_CLOCK_REG, clock);
351
352 return 0;
353 }
354
355 static int
plmmc_bus_width(sdmmc_chipset_handle_t sch,int width)356 plmmc_bus_width(sdmmc_chipset_handle_t sch, int width)
357 {
358 return 0;
359 }
360
361 static int
plmmc_bus_rod(sdmmc_chipset_handle_t sch,int on)362 plmmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
363 {
364 struct plmmc_softc *sc = sch;
365 uint32_t power;
366
367
368 power = MMCI_READ(sc, MMCI_POWER_REG);
369 if (on) {
370 power |= MMCI_POWER_ROD;
371 } else {
372 power &= ~MMCI_POWER_ROD;
373 }
374 MMCI_WRITE(sc, MMCI_POWER_REG, power);
375
376 return 0;
377 }
378
379 static void
plmmc_do_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)380 plmmc_do_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
381 {
382 struct plmmc_softc *sc = sch;
383 uint32_t cmdval = MMCI_COMMAND_ENABLE;
384
385 KASSERT(mutex_owned(&sc->sc_lock));
386
387 const int xferlen = uimin(cmd->c_resid, PLMMC_MAXXFER);
388
389 sc->sc_cmd = cmd;
390 sc->sc_fifo_resid = xferlen;
391 sc->sc_status_mask = ~0U;
392 sc->sc_intr_status = 0;
393
394 #ifdef PLMMC_DEBUG
395 device_printf(sc->sc_dev,
396 "opcode %d flags %#x datalen %d resid %d xferlen %d\n",
397 cmd->c_opcode, cmd->c_flags, cmd->c_datalen, cmd->c_resid, xferlen);
398 #endif
399
400 MMCI_WRITE(sc, MMCI_COMMAND_REG, 0);
401 MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
402 MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
403 MMCI_WRITE(sc, MMCI_MASK0_REG, PLMMC_INT_DATA_MASK | PLMMC_INT_CMD_MASK);
404
405 if (cmd->c_flags & SCF_RSP_PRESENT)
406 cmdval |= MMCI_COMMAND_RESPONSE;
407 if (cmd->c_flags & SCF_RSP_136)
408 cmdval |= MMCI_COMMAND_LONGRSP;
409
410 uint32_t arg = cmd->c_arg;
411
412 if (xferlen > 0) {
413 unsigned int nblks = xferlen / cmd->c_blklen;
414 if (nblks == 0 || (xferlen % cmd->c_blklen) != 0)
415 ++nblks;
416
417 const uint32_t dir = (cmd->c_flags & SCF_CMD_READ) ? 1 : 0;
418 const uint32_t blksize = ffs(cmd->c_blklen) - 1;
419
420 MMCI_WRITE(sc, MMCI_DATA_TIMER_REG, 0xffffffff);
421 MMCI_WRITE(sc, MMCI_DATA_LENGTH_REG, nblks * cmd->c_blklen);
422 MMCI_WRITE(sc, MMCI_DATA_CTRL_REG,
423 __SHIFTIN(dir, MMCI_DATA_CTRL_DIRECTION) |
424 __SHIFTIN(blksize, MMCI_DATA_CTRL_BLOCKSIZE) |
425 MMCI_DATA_CTRL_ENABLE);
426
427 /* Adjust blkno if necessary */
428 u_int blkoff =
429 (cmd->c_datalen - cmd->c_resid) / SDMMC_SECTOR_SIZE;
430 if (!ISSET(cmd->c_flags, SCF_XFER_SDHC))
431 blkoff <<= SDMMC_SECTOR_SIZE_SB;
432 arg += blkoff;
433 }
434
435 MMCI_WRITE(sc, MMCI_ARGUMENT_REG, arg);
436 MMCI_WRITE(sc, MMCI_COMMAND_REG, cmdval | cmd->c_opcode);
437
438 if (xferlen > 0) {
439 cmd->c_error = plmmc_pio_transfer(sc, cmd, xferlen);
440 if (cmd->c_error) {
441 #ifdef PLMMC_DEBUG
442 device_printf(sc->sc_dev,
443 "MMCI_STATUS_REG = %08x\n", MMCI_READ(sc, MMCI_STATUS_REG));
444 #endif
445 device_printf(sc->sc_dev,
446 "error (%d) waiting for xfer\n", cmd->c_error);
447 goto done;
448 }
449 }
450
451 if ((cmd->c_flags & SCF_RSP_PRESENT) && cmd->c_resid == 0) {
452 cmd->c_error = plmmc_wait_cmd(sc);
453 if (cmd->c_error) {
454 #ifdef PLMMC_DEBUG
455 device_printf(sc->sc_dev,
456 "error (%d) waiting for resp\n", cmd->c_error);
457 #endif
458 goto done;
459 }
460
461 if (cmd->c_flags & SCF_RSP_136) {
462 cmd->c_resp[3] = MMCI_READ(sc, MMCI_RESP0_REG);
463 cmd->c_resp[2] = MMCI_READ(sc, MMCI_RESP1_REG);
464 cmd->c_resp[1] = MMCI_READ(sc, MMCI_RESP2_REG);
465 cmd->c_resp[0] = MMCI_READ(sc, MMCI_RESP3_REG);
466 if (cmd->c_flags & SCF_RSP_CRC) {
467 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
468 (cmd->c_resp[1] << 24);
469 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
470 (cmd->c_resp[2] << 24);
471 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
472 (cmd->c_resp[3] << 24);
473 cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
474 }
475 } else {
476 cmd->c_resp[0] = MMCI_READ(sc, MMCI_RESP0_REG);
477 }
478 }
479
480 done:
481 sc->sc_cmd = NULL;
482
483 MMCI_WRITE(sc, MMCI_COMMAND_REG, 0);
484 MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
485 MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
486 MMCI_WRITE(sc, MMCI_DATA_CNT_REG, 0);
487
488 #ifdef PLMMC_DEBUG
489 device_printf(sc->sc_dev, "status = %#x\n", sc->sc_intr_status);
490 #endif
491 }
492
493 static void
plmmc_exec_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)494 plmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
495 {
496 struct plmmc_softc *sc = sch;
497
498 #ifdef PLMMC_DEBUG
499 device_printf(sc->sc_dev, "opcode %d flags %#x data %p datalen %d\n",
500 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen);
501 #endif
502
503 mutex_enter(&sc->sc_lock);
504 cmd->c_resid = cmd->c_datalen;
505 cmd->c_buf = cmd->c_data;
506 do {
507 plmmc_do_command(sch, cmd);
508
509 if (cmd->c_resid > 0 && cmd->c_error == 0) {
510 /*
511 * Multi block transfer and there is still data
512 * remaining. Send a stop cmd between transfers.
513 */
514 struct sdmmc_command stop_cmd;
515 memset(&stop_cmd, 0, sizeof(stop_cmd));
516 stop_cmd.c_opcode = MMC_STOP_TRANSMISSION;
517 stop_cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B |
518 SCF_RSP_SPI_R1B;
519 plmmc_do_command(sch, &stop_cmd);
520 }
521 } while (cmd->c_resid > 0 && cmd->c_error == 0);
522 cmd->c_flags |= SCF_ITSDONE;
523 mutex_exit(&sc->sc_lock);
524 }
525
526 static void
plmmc_card_enable_intr(sdmmc_chipset_handle_t sch,int enable)527 plmmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
528 {
529 }
530
531 static void
plmmc_card_intr_ack(sdmmc_chipset_handle_t sch)532 plmmc_card_intr_ack(sdmmc_chipset_handle_t sch)
533 {
534 }
535